1 // SPDX-License-Identifier: GPL-2.0-only
3 * tegra20_ac97.c - Tegra20 AC97 platform driver
5 * Copyright (c) 2012 Lucas Stach <dev@lynxeye.de>
7 * Partly based on code copyright/by:
9 * Copyright (c) 2011,2012 Toradex Inc.
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/gpio.h>
17 #include <linux/jiffies.h>
18 #include <linux/module.h>
20 #include <linux/of_gpio.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/regmap.h>
24 #include <linux/reset.h>
25 #include <linux/slab.h>
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/dmaengine_pcm.h>
32 #include "tegra20_ac97.h"
34 #define DRV_NAME "tegra20-ac97"
36 static struct tegra20_ac97 *workdata;
38 static void tegra20_ac97_codec_reset(struct snd_ac97 *ac97)
41 unsigned long timeout;
43 /* reset line is not driven by DAC pad group, have to toggle GPIO */
44 gpio_set_value(workdata->reset_gpio, 0);
47 gpio_set_value(workdata->reset_gpio, 1);
50 timeout = jiffies + msecs_to_jiffies(100);
53 regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
54 if (readback & TEGRA20_AC97_STATUS1_CODEC1_RDY)
56 usleep_range(1000, 2000);
57 } while (!time_after(jiffies, timeout));
60 static void tegra20_ac97_codec_warm_reset(struct snd_ac97 *ac97)
63 unsigned long timeout;
66 * although sync line is driven by the DAC pad group warm reset using
67 * the controller cmd is not working, have to toggle sync line
70 gpio_request(workdata->sync_gpio, "codec-sync");
72 gpio_direction_output(workdata->sync_gpio, 1);
75 gpio_set_value(workdata->sync_gpio, 0);
77 gpio_free(workdata->sync_gpio);
79 timeout = jiffies + msecs_to_jiffies(100);
82 regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
83 if (readback & TEGRA20_AC97_STATUS1_CODEC1_RDY)
85 usleep_range(1000, 2000);
86 } while (!time_after(jiffies, timeout));
89 static unsigned short tegra20_ac97_codec_read(struct snd_ac97 *ac97_snd,
93 unsigned long timeout;
95 regmap_write(workdata->regmap, TEGRA20_AC97_CMD,
96 (((reg | 0x80) << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT) &
97 TEGRA20_AC97_CMD_CMD_ADDR_MASK) |
98 TEGRA20_AC97_CMD_BUSY);
100 timeout = jiffies + msecs_to_jiffies(100);
103 regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
104 if (readback & TEGRA20_AC97_STATUS1_STA_VALID1)
106 usleep_range(1000, 2000);
107 } while (!time_after(jiffies, timeout));
109 return ((readback & TEGRA20_AC97_STATUS1_STA_DATA1_MASK) >>
110 TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT);
113 static void tegra20_ac97_codec_write(struct snd_ac97 *ac97_snd,
114 unsigned short reg, unsigned short val)
117 unsigned long timeout;
119 regmap_write(workdata->regmap, TEGRA20_AC97_CMD,
120 ((reg << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT) &
121 TEGRA20_AC97_CMD_CMD_ADDR_MASK) |
122 ((val << TEGRA20_AC97_CMD_CMD_DATA_SHIFT) &
123 TEGRA20_AC97_CMD_CMD_DATA_MASK) |
124 TEGRA20_AC97_CMD_BUSY);
126 timeout = jiffies + msecs_to_jiffies(100);
129 regmap_read(workdata->regmap, TEGRA20_AC97_CMD, &readback);
130 if (!(readback & TEGRA20_AC97_CMD_BUSY))
132 usleep_range(1000, 2000);
133 } while (!time_after(jiffies, timeout));
136 static struct snd_ac97_bus_ops tegra20_ac97_ops = {
137 .read = tegra20_ac97_codec_read,
138 .write = tegra20_ac97_codec_write,
139 .reset = tegra20_ac97_codec_reset,
140 .warm_reset = tegra20_ac97_codec_warm_reset,
143 static inline void tegra20_ac97_start_playback(struct tegra20_ac97 *ac97)
145 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
146 TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN,
147 TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN);
149 regmap_update_bits(ac97->regmap, TEGRA20_AC97_CTRL,
150 TEGRA20_AC97_CTRL_PCM_DAC_EN |
151 TEGRA20_AC97_CTRL_STM_EN,
152 TEGRA20_AC97_CTRL_PCM_DAC_EN |
153 TEGRA20_AC97_CTRL_STM_EN);
156 static inline void tegra20_ac97_stop_playback(struct tegra20_ac97 *ac97)
158 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
159 TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN, 0);
161 regmap_update_bits(ac97->regmap, TEGRA20_AC97_CTRL,
162 TEGRA20_AC97_CTRL_PCM_DAC_EN, 0);
165 static inline void tegra20_ac97_start_capture(struct tegra20_ac97 *ac97)
167 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
168 TEGRA20_AC97_FIFO_SCR_REC_FULL_EN,
169 TEGRA20_AC97_FIFO_SCR_REC_FULL_EN);
172 static inline void tegra20_ac97_stop_capture(struct tegra20_ac97 *ac97)
174 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
175 TEGRA20_AC97_FIFO_SCR_REC_FULL_EN, 0);
178 static int tegra20_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
179 struct snd_soc_dai *dai)
181 struct tegra20_ac97 *ac97 = snd_soc_dai_get_drvdata(dai);
184 case SNDRV_PCM_TRIGGER_START:
185 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
186 case SNDRV_PCM_TRIGGER_RESUME:
187 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
188 tegra20_ac97_start_playback(ac97);
190 tegra20_ac97_start_capture(ac97);
192 case SNDRV_PCM_TRIGGER_STOP:
193 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
194 case SNDRV_PCM_TRIGGER_SUSPEND:
195 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
196 tegra20_ac97_stop_playback(ac97);
198 tegra20_ac97_stop_capture(ac97);
207 static const struct snd_soc_dai_ops tegra20_ac97_dai_ops = {
208 .trigger = tegra20_ac97_trigger,
211 static int tegra20_ac97_probe(struct snd_soc_dai *dai)
213 struct tegra20_ac97 *ac97 = snd_soc_dai_get_drvdata(dai);
215 dai->capture_dma_data = &ac97->capture_dma_data;
216 dai->playback_dma_data = &ac97->playback_dma_data;
221 static struct snd_soc_dai_driver tegra20_ac97_dai = {
222 .name = "tegra-ac97-pcm",
223 .probe = tegra20_ac97_probe,
225 .stream_name = "PCM Playback",
228 .rates = SNDRV_PCM_RATE_8000_48000,
229 .formats = SNDRV_PCM_FMTBIT_S16_LE,
232 .stream_name = "PCM Capture",
235 .rates = SNDRV_PCM_RATE_8000_48000,
236 .formats = SNDRV_PCM_FMTBIT_S16_LE,
238 .ops = &tegra20_ac97_dai_ops,
241 static const struct snd_soc_component_driver tegra20_ac97_component = {
245 static bool tegra20_ac97_wr_rd_reg(struct device *dev, unsigned int reg)
248 case TEGRA20_AC97_CTRL:
249 case TEGRA20_AC97_CMD:
250 case TEGRA20_AC97_STATUS1:
251 case TEGRA20_AC97_FIFO1_SCR:
252 case TEGRA20_AC97_FIFO_TX1:
253 case TEGRA20_AC97_FIFO_RX1:
262 static bool tegra20_ac97_volatile_reg(struct device *dev, unsigned int reg)
265 case TEGRA20_AC97_STATUS1:
266 case TEGRA20_AC97_FIFO1_SCR:
267 case TEGRA20_AC97_FIFO_TX1:
268 case TEGRA20_AC97_FIFO_RX1:
277 static bool tegra20_ac97_precious_reg(struct device *dev, unsigned int reg)
280 case TEGRA20_AC97_FIFO_TX1:
281 case TEGRA20_AC97_FIFO_RX1:
290 static const struct regmap_config tegra20_ac97_regmap_config = {
294 .max_register = TEGRA20_AC97_FIFO_RX1,
295 .writeable_reg = tegra20_ac97_wr_rd_reg,
296 .readable_reg = tegra20_ac97_wr_rd_reg,
297 .volatile_reg = tegra20_ac97_volatile_reg,
298 .precious_reg = tegra20_ac97_precious_reg,
299 .cache_type = REGCACHE_FLAT,
302 static int tegra20_ac97_platform_probe(struct platform_device *pdev)
304 struct tegra20_ac97 *ac97;
305 struct resource *mem;
309 ac97 = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_ac97),
315 dev_set_drvdata(&pdev->dev, ac97);
317 ac97->reset = devm_reset_control_get_exclusive(&pdev->dev, "ac97");
318 if (IS_ERR(ac97->reset)) {
319 dev_err(&pdev->dev, "Can't retrieve ac97 reset\n");
320 return PTR_ERR(ac97->reset);
323 ac97->clk_ac97 = devm_clk_get(&pdev->dev, NULL);
324 if (IS_ERR(ac97->clk_ac97)) {
325 dev_err(&pdev->dev, "Can't retrieve ac97 clock\n");
326 ret = PTR_ERR(ac97->clk_ac97);
330 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
331 regs = devm_ioremap_resource(&pdev->dev, mem);
337 ac97->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
338 &tegra20_ac97_regmap_config);
339 if (IS_ERR(ac97->regmap)) {
340 dev_err(&pdev->dev, "regmap init failed\n");
341 ret = PTR_ERR(ac97->regmap);
345 ac97->reset_gpio = of_get_named_gpio(pdev->dev.of_node,
346 "nvidia,codec-reset-gpio", 0);
347 if (gpio_is_valid(ac97->reset_gpio)) {
348 ret = devm_gpio_request_one(&pdev->dev, ac97->reset_gpio,
349 GPIOF_OUT_INIT_HIGH, "codec-reset");
351 dev_err(&pdev->dev, "could not get codec-reset GPIO\n");
355 dev_err(&pdev->dev, "no codec-reset GPIO supplied\n");
359 ac97->sync_gpio = of_get_named_gpio(pdev->dev.of_node,
360 "nvidia,codec-sync-gpio", 0);
361 if (!gpio_is_valid(ac97->sync_gpio)) {
362 dev_err(&pdev->dev, "no codec-sync GPIO supplied\n");
366 ac97->capture_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_RX1;
367 ac97->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
368 ac97->capture_dma_data.maxburst = 4;
370 ac97->playback_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_TX1;
371 ac97->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
372 ac97->playback_dma_data.maxburst = 4;
374 ret = reset_control_assert(ac97->reset);
376 dev_err(&pdev->dev, "Failed to assert AC'97 reset: %d\n", ret);
380 ret = clk_prepare_enable(ac97->clk_ac97);
382 dev_err(&pdev->dev, "clk_enable failed: %d\n", ret);
386 usleep_range(10, 100);
388 ret = reset_control_deassert(ac97->reset);
390 dev_err(&pdev->dev, "Failed to deassert AC'97 reset: %d\n", ret);
391 goto err_clk_disable_unprepare;
394 ret = snd_soc_set_ac97_ops(&tegra20_ac97_ops);
396 dev_err(&pdev->dev, "Failed to set AC'97 ops: %d\n", ret);
397 goto err_clk_disable_unprepare;
400 ret = snd_soc_register_component(&pdev->dev, &tegra20_ac97_component,
401 &tegra20_ac97_dai, 1);
403 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
405 goto err_clk_disable_unprepare;
408 ret = tegra_pcm_platform_register(&pdev->dev);
410 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
411 goto err_unregister_component;
414 /* XXX: crufty ASoC AC97 API - only one AC97 codec allowed */
419 err_unregister_component:
420 snd_soc_unregister_component(&pdev->dev);
421 err_clk_disable_unprepare:
422 clk_disable_unprepare(ac97->clk_ac97);
425 snd_soc_set_ac97_ops(NULL);
429 static int tegra20_ac97_platform_remove(struct platform_device *pdev)
431 struct tegra20_ac97 *ac97 = dev_get_drvdata(&pdev->dev);
433 tegra_pcm_platform_unregister(&pdev->dev);
434 snd_soc_unregister_component(&pdev->dev);
436 clk_disable_unprepare(ac97->clk_ac97);
438 snd_soc_set_ac97_ops(NULL);
443 static const struct of_device_id tegra20_ac97_of_match[] = {
444 { .compatible = "nvidia,tegra20-ac97", },
448 static struct platform_driver tegra20_ac97_driver = {
451 .of_match_table = tegra20_ac97_of_match,
453 .probe = tegra20_ac97_platform_probe,
454 .remove = tegra20_ac97_platform_remove,
456 module_platform_driver(tegra20_ac97_driver);
458 MODULE_AUTHOR("Lucas Stach");
459 MODULE_DESCRIPTION("Tegra20 AC97 ASoC driver");
460 MODULE_LICENSE("GPL v2");
461 MODULE_ALIAS("platform:" DRV_NAME);
462 MODULE_DEVICE_TABLE(of, tegra20_ac97_of_match);