1 // SPDX-License-Identifier: GPL-2.0-only
3 * STM32 ALSA SoC Digital Audio Interface (SPDIF-rx) driver.
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/completion.h>
12 #include <linux/delay.h>
13 #include <linux/module.h>
14 #include <linux/of_platform.h>
15 #include <linux/pinctrl/consumer.h>
16 #include <linux/regmap.h>
17 #include <linux/reset.h>
19 #include <sound/dmaengine_pcm.h>
20 #include <sound/pcm_params.h>
22 /* SPDIF-rx Register Map */
23 #define STM32_SPDIFRX_CR 0x00
24 #define STM32_SPDIFRX_IMR 0x04
25 #define STM32_SPDIFRX_SR 0x08
26 #define STM32_SPDIFRX_IFCR 0x0C
27 #define STM32_SPDIFRX_DR 0x10
28 #define STM32_SPDIFRX_CSR 0x14
29 #define STM32_SPDIFRX_DIR 0x18
30 #define STM32_SPDIFRX_VERR 0x3F4
31 #define STM32_SPDIFRX_IDR 0x3F8
32 #define STM32_SPDIFRX_SIDR 0x3FC
34 /* Bit definition for SPDIF_CR register */
35 #define SPDIFRX_CR_SPDIFEN_SHIFT 0
36 #define SPDIFRX_CR_SPDIFEN_MASK GENMASK(1, SPDIFRX_CR_SPDIFEN_SHIFT)
37 #define SPDIFRX_CR_SPDIFENSET(x) ((x) << SPDIFRX_CR_SPDIFEN_SHIFT)
39 #define SPDIFRX_CR_RXDMAEN BIT(2)
40 #define SPDIFRX_CR_RXSTEO BIT(3)
42 #define SPDIFRX_CR_DRFMT_SHIFT 4
43 #define SPDIFRX_CR_DRFMT_MASK GENMASK(5, SPDIFRX_CR_DRFMT_SHIFT)
44 #define SPDIFRX_CR_DRFMTSET(x) ((x) << SPDIFRX_CR_DRFMT_SHIFT)
46 #define SPDIFRX_CR_PMSK BIT(6)
47 #define SPDIFRX_CR_VMSK BIT(7)
48 #define SPDIFRX_CR_CUMSK BIT(8)
49 #define SPDIFRX_CR_PTMSK BIT(9)
50 #define SPDIFRX_CR_CBDMAEN BIT(10)
51 #define SPDIFRX_CR_CHSEL_SHIFT 11
52 #define SPDIFRX_CR_CHSEL BIT(SPDIFRX_CR_CHSEL_SHIFT)
54 #define SPDIFRX_CR_NBTR_SHIFT 12
55 #define SPDIFRX_CR_NBTR_MASK GENMASK(13, SPDIFRX_CR_NBTR_SHIFT)
56 #define SPDIFRX_CR_NBTRSET(x) ((x) << SPDIFRX_CR_NBTR_SHIFT)
58 #define SPDIFRX_CR_WFA BIT(14)
60 #define SPDIFRX_CR_INSEL_SHIFT 16
61 #define SPDIFRX_CR_INSEL_MASK GENMASK(18, PDIFRX_CR_INSEL_SHIFT)
62 #define SPDIFRX_CR_INSELSET(x) ((x) << SPDIFRX_CR_INSEL_SHIFT)
64 #define SPDIFRX_CR_CKSEN_SHIFT 20
65 #define SPDIFRX_CR_CKSEN BIT(20)
66 #define SPDIFRX_CR_CKSBKPEN BIT(21)
68 /* Bit definition for SPDIFRX_IMR register */
69 #define SPDIFRX_IMR_RXNEI BIT(0)
70 #define SPDIFRX_IMR_CSRNEIE BIT(1)
71 #define SPDIFRX_IMR_PERRIE BIT(2)
72 #define SPDIFRX_IMR_OVRIE BIT(3)
73 #define SPDIFRX_IMR_SBLKIE BIT(4)
74 #define SPDIFRX_IMR_SYNCDIE BIT(5)
75 #define SPDIFRX_IMR_IFEIE BIT(6)
77 #define SPDIFRX_XIMR_MASK GENMASK(6, 0)
79 /* Bit definition for SPDIFRX_SR register */
80 #define SPDIFRX_SR_RXNE BIT(0)
81 #define SPDIFRX_SR_CSRNE BIT(1)
82 #define SPDIFRX_SR_PERR BIT(2)
83 #define SPDIFRX_SR_OVR BIT(3)
84 #define SPDIFRX_SR_SBD BIT(4)
85 #define SPDIFRX_SR_SYNCD BIT(5)
86 #define SPDIFRX_SR_FERR BIT(6)
87 #define SPDIFRX_SR_SERR BIT(7)
88 #define SPDIFRX_SR_TERR BIT(8)
90 #define SPDIFRX_SR_WIDTH5_SHIFT 16
91 #define SPDIFRX_SR_WIDTH5_MASK GENMASK(30, PDIFRX_SR_WIDTH5_SHIFT)
92 #define SPDIFRX_SR_WIDTH5SET(x) ((x) << SPDIFRX_SR_WIDTH5_SHIFT)
94 /* Bit definition for SPDIFRX_IFCR register */
95 #define SPDIFRX_IFCR_PERRCF BIT(2)
96 #define SPDIFRX_IFCR_OVRCF BIT(3)
97 #define SPDIFRX_IFCR_SBDCF BIT(4)
98 #define SPDIFRX_IFCR_SYNCDCF BIT(5)
100 #define SPDIFRX_XIFCR_MASK GENMASK(5, 2)
102 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b00) */
103 #define SPDIFRX_DR0_DR_SHIFT 0
104 #define SPDIFRX_DR0_DR_MASK GENMASK(23, SPDIFRX_DR0_DR_SHIFT)
105 #define SPDIFRX_DR0_DRSET(x) ((x) << SPDIFRX_DR0_DR_SHIFT)
107 #define SPDIFRX_DR0_PE BIT(24)
109 #define SPDIFRX_DR0_V BIT(25)
110 #define SPDIFRX_DR0_U BIT(26)
111 #define SPDIFRX_DR0_C BIT(27)
113 #define SPDIFRX_DR0_PT_SHIFT 28
114 #define SPDIFRX_DR0_PT_MASK GENMASK(29, SPDIFRX_DR0_PT_SHIFT)
115 #define SPDIFRX_DR0_PTSET(x) ((x) << SPDIFRX_DR0_PT_SHIFT)
117 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b01) */
118 #define SPDIFRX_DR1_PE BIT(0)
119 #define SPDIFRX_DR1_V BIT(1)
120 #define SPDIFRX_DR1_U BIT(2)
121 #define SPDIFRX_DR1_C BIT(3)
123 #define SPDIFRX_DR1_PT_SHIFT 4
124 #define SPDIFRX_DR1_PT_MASK GENMASK(5, SPDIFRX_DR1_PT_SHIFT)
125 #define SPDIFRX_DR1_PTSET(x) ((x) << SPDIFRX_DR1_PT_SHIFT)
127 #define SPDIFRX_DR1_DR_SHIFT 8
128 #define SPDIFRX_DR1_DR_MASK GENMASK(31, SPDIFRX_DR1_DR_SHIFT)
129 #define SPDIFRX_DR1_DRSET(x) ((x) << SPDIFRX_DR1_DR_SHIFT)
131 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b10) */
132 #define SPDIFRX_DR1_DRNL1_SHIFT 0
133 #define SPDIFRX_DR1_DRNL1_MASK GENMASK(15, SPDIFRX_DR1_DRNL1_SHIFT)
134 #define SPDIFRX_DR1_DRNL1SET(x) ((x) << SPDIFRX_DR1_DRNL1_SHIFT)
136 #define SPDIFRX_DR1_DRNL2_SHIFT 16
137 #define SPDIFRX_DR1_DRNL2_MASK GENMASK(31, SPDIFRX_DR1_DRNL2_SHIFT)
138 #define SPDIFRX_DR1_DRNL2SET(x) ((x) << SPDIFRX_DR1_DRNL2_SHIFT)
140 /* Bit definition for SPDIFRX_CSR register */
141 #define SPDIFRX_CSR_USR_SHIFT 0
142 #define SPDIFRX_CSR_USR_MASK GENMASK(15, SPDIFRX_CSR_USR_SHIFT)
143 #define SPDIFRX_CSR_USRGET(x) (((x) & SPDIFRX_CSR_USR_MASK)\
144 >> SPDIFRX_CSR_USR_SHIFT)
146 #define SPDIFRX_CSR_CS_SHIFT 16
147 #define SPDIFRX_CSR_CS_MASK GENMASK(23, SPDIFRX_CSR_CS_SHIFT)
148 #define SPDIFRX_CSR_CSGET(x) (((x) & SPDIFRX_CSR_CS_MASK)\
149 >> SPDIFRX_CSR_CS_SHIFT)
151 #define SPDIFRX_CSR_SOB BIT(24)
153 /* Bit definition for SPDIFRX_DIR register */
154 #define SPDIFRX_DIR_THI_SHIFT 0
155 #define SPDIFRX_DIR_THI_MASK GENMASK(12, SPDIFRX_DIR_THI_SHIFT)
156 #define SPDIFRX_DIR_THI_SET(x) ((x) << SPDIFRX_DIR_THI_SHIFT)
158 #define SPDIFRX_DIR_TLO_SHIFT 16
159 #define SPDIFRX_DIR_TLO_MASK GENMASK(28, SPDIFRX_DIR_TLO_SHIFT)
160 #define SPDIFRX_DIR_TLO_SET(x) ((x) << SPDIFRX_DIR_TLO_SHIFT)
162 #define SPDIFRX_SPDIFEN_DISABLE 0x0
163 #define SPDIFRX_SPDIFEN_SYNC 0x1
164 #define SPDIFRX_SPDIFEN_ENABLE 0x3
166 /* Bit definition for SPDIFRX_VERR register */
167 #define SPDIFRX_VERR_MIN_MASK GENMASK(3, 0)
168 #define SPDIFRX_VERR_MAJ_MASK GENMASK(7, 4)
170 /* Bit definition for SPDIFRX_IDR register */
171 #define SPDIFRX_IDR_ID_MASK GENMASK(31, 0)
173 /* Bit definition for SPDIFRX_SIDR register */
174 #define SPDIFRX_SIDR_SID_MASK GENMASK(31, 0)
176 #define SPDIFRX_IPIDR_NUMBER 0x00130041
178 #define SPDIFRX_IN1 0x1
179 #define SPDIFRX_IN2 0x2
180 #define SPDIFRX_IN3 0x3
181 #define SPDIFRX_IN4 0x4
182 #define SPDIFRX_IN5 0x5
183 #define SPDIFRX_IN6 0x6
184 #define SPDIFRX_IN7 0x7
185 #define SPDIFRX_IN8 0x8
187 #define SPDIFRX_NBTR_NONE 0x0
188 #define SPDIFRX_NBTR_3 0x1
189 #define SPDIFRX_NBTR_15 0x2
190 #define SPDIFRX_NBTR_63 0x3
192 #define SPDIFRX_DRFMT_RIGHT 0x0
193 #define SPDIFRX_DRFMT_LEFT 0x1
194 #define SPDIFRX_DRFMT_PACKED 0x2
196 /* 192 CS bits in S/PDIF frame. i.e 24 CS bytes */
197 #define SPDIFRX_CS_BYTES_NB 24
198 #define SPDIFRX_UB_BYTES_NB 48
201 * CSR register is retrieved as a 32 bits word
202 * It contains 1 channel status byte and 2 user data bytes
203 * 2 S/PDIF frames are acquired to get all CS/UB bits
205 #define SPDIFRX_CSR_BUF_LENGTH (SPDIFRX_CS_BYTES_NB * 4 * 2)
208 * struct stm32_spdifrx_data - private data of SPDIFRX
209 * @pdev: device data pointer
210 * @base: mmio register base virtual address
211 * @regmap: SPDIFRX register map pointer
212 * @regmap_conf: SPDIFRX register map configuration pointer
213 * @cs_completion: channel status retrieving completion
214 * @kclk: kernel clock feeding the SPDIFRX clock generator
215 * @dma_params: dma configuration data for rx channel
216 * @substream: PCM substream data pointer
217 * @dmab: dma buffer info pointer
218 * @ctrl_chan: dma channel for S/PDIF control bits
219 * @desc:dma async transaction descriptor
220 * @slave_config: dma slave channel runtime config pointer
221 * @phys_addr: SPDIFRX registers physical base address
222 * @lock: synchronization enabling lock
223 * @irq_lock: prevent race condition with IRQ on stream state
224 * @cs: channel status buffer
225 * @ub: user data buffer
226 * @irq: SPDIFRX interrupt line
227 * @refcount: keep count of opened DMA channels
229 struct stm32_spdifrx_data {
230 struct platform_device *pdev;
232 struct regmap *regmap;
233 const struct regmap_config *regmap_conf;
234 struct completion cs_completion;
236 struct snd_dmaengine_dai_dma_data dma_params;
237 struct snd_pcm_substream *substream;
238 struct snd_dma_buffer *dmab;
239 struct dma_chan *ctrl_chan;
240 struct dma_async_tx_descriptor *desc;
241 struct dma_slave_config slave_config;
242 dma_addr_t phys_addr;
243 spinlock_t lock; /* Sync enabling lock */
244 spinlock_t irq_lock; /* Prevent race condition on stream state */
245 unsigned char cs[SPDIFRX_CS_BYTES_NB];
246 unsigned char ub[SPDIFRX_UB_BYTES_NB];
251 static void stm32_spdifrx_dma_complete(void *data)
253 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)data;
254 struct platform_device *pdev = spdifrx->pdev;
255 u32 *p_start = (u32 *)spdifrx->dmab->area;
256 u32 *p_end = p_start + (2 * SPDIFRX_CS_BYTES_NB) - 1;
258 u16 *ub_ptr = (short *)spdifrx->ub;
261 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
263 (unsigned int)~SPDIFRX_CR_CBDMAEN);
265 if (!spdifrx->dmab->area)
268 while (ptr <= p_end) {
269 if (*ptr & SPDIFRX_CSR_SOB)
275 dev_err(&pdev->dev, "Start of S/PDIF block not found\n");
279 while (i < SPDIFRX_CS_BYTES_NB) {
280 spdifrx->cs[i] = (unsigned char)SPDIFRX_CSR_CSGET(*ptr);
281 *ub_ptr++ = SPDIFRX_CSR_USRGET(*ptr++);
283 dev_err(&pdev->dev, "Failed to get channel status\n");
289 complete(&spdifrx->cs_completion);
292 static int stm32_spdifrx_dma_ctrl_start(struct stm32_spdifrx_data *spdifrx)
297 spdifrx->desc = dmaengine_prep_slave_single(spdifrx->ctrl_chan,
299 SPDIFRX_CSR_BUF_LENGTH,
305 spdifrx->desc->callback = stm32_spdifrx_dma_complete;
306 spdifrx->desc->callback_param = spdifrx;
307 cookie = dmaengine_submit(spdifrx->desc);
308 err = dma_submit_error(cookie);
312 dma_async_issue_pending(spdifrx->ctrl_chan);
317 static void stm32_spdifrx_dma_ctrl_stop(struct stm32_spdifrx_data *spdifrx)
319 dmaengine_terminate_async(spdifrx->ctrl_chan);
322 static int stm32_spdifrx_start_sync(struct stm32_spdifrx_data *spdifrx)
324 int cr, cr_mask, imr, ret;
328 imr = SPDIFRX_IMR_IFEIE | SPDIFRX_IMR_SYNCDIE | SPDIFRX_IMR_PERRIE;
329 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, imr, imr);
333 spin_lock_irqsave(&spdifrx->lock, flags);
337 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr);
339 if (!(cr & SPDIFRX_CR_SPDIFEN_MASK)) {
341 * Start sync if SPDIFRX is still in idle state.
342 * SPDIFRX reception enabled when sync done
344 dev_dbg(&spdifrx->pdev->dev, "start synchronization\n");
347 * SPDIFRX configuration:
348 * Wait for activity before starting sync process. This avoid
349 * to issue sync errors when spdif signal is missing on input.
350 * Preamble, CS, user, validity and parity error bits not copied
353 cr = SPDIFRX_CR_WFA | SPDIFRX_CR_PMSK | SPDIFRX_CR_VMSK |
354 SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK | SPDIFRX_CR_RXSTEO;
357 cr |= SPDIFRX_CR_NBTRSET(SPDIFRX_NBTR_63);
358 cr_mask |= SPDIFRX_CR_NBTR_MASK;
359 cr |= SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC);
360 cr_mask |= SPDIFRX_CR_SPDIFEN_MASK;
361 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
364 dev_err(&spdifrx->pdev->dev,
365 "Failed to start synchronization\n");
368 spin_unlock_irqrestore(&spdifrx->lock, flags);
373 static void stm32_spdifrx_stop(struct stm32_spdifrx_data *spdifrx)
375 int cr, cr_mask, reg;
378 spin_lock_irqsave(&spdifrx->lock, flags);
380 if (--spdifrx->refcount) {
381 spin_unlock_irqrestore(&spdifrx->lock, flags);
385 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE);
386 cr_mask = SPDIFRX_CR_SPDIFEN_MASK | SPDIFRX_CR_RXDMAEN;
388 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, cr_mask, cr);
390 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR,
391 SPDIFRX_XIMR_MASK, 0);
393 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR,
394 SPDIFRX_XIFCR_MASK, SPDIFRX_XIFCR_MASK);
396 /* dummy read to clear CSRNE and RXNE in status register */
397 regmap_read(spdifrx->regmap, STM32_SPDIFRX_DR, ®);
398 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CSR, ®);
400 spin_unlock_irqrestore(&spdifrx->lock, flags);
403 static int stm32_spdifrx_dma_ctrl_register(struct device *dev,
404 struct stm32_spdifrx_data *spdifrx)
408 spdifrx->ctrl_chan = dma_request_chan(dev, "rx-ctrl");
409 if (IS_ERR(spdifrx->ctrl_chan)) {
410 dev_err(dev, "dma_request_slave_channel failed\n");
411 return PTR_ERR(spdifrx->ctrl_chan);
414 spdifrx->dmab = devm_kzalloc(dev, sizeof(struct snd_dma_buffer),
419 spdifrx->dmab->dev.type = SNDRV_DMA_TYPE_DEV_IRAM;
420 spdifrx->dmab->dev.dev = dev;
421 ret = snd_dma_alloc_pages(spdifrx->dmab->dev.type, dev,
422 SPDIFRX_CSR_BUF_LENGTH, spdifrx->dmab);
424 dev_err(dev, "snd_dma_alloc_pages returned error %d\n", ret);
428 spdifrx->slave_config.direction = DMA_DEV_TO_MEM;
429 spdifrx->slave_config.src_addr = (dma_addr_t)(spdifrx->phys_addr +
431 spdifrx->slave_config.dst_addr = spdifrx->dmab->addr;
432 spdifrx->slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
433 spdifrx->slave_config.src_maxburst = 1;
435 ret = dmaengine_slave_config(spdifrx->ctrl_chan,
436 &spdifrx->slave_config);
438 dev_err(dev, "dmaengine_slave_config returned error %d\n", ret);
439 spdifrx->ctrl_chan = NULL;
445 static const char * const spdifrx_enum_input[] = {
446 "in0", "in1", "in2", "in3"
449 /* By default CS bits are retrieved from channel A */
450 static const char * const spdifrx_enum_cs_channel[] = {
454 static SOC_ENUM_SINGLE_DECL(ctrl_enum_input,
455 STM32_SPDIFRX_CR, SPDIFRX_CR_INSEL_SHIFT,
458 static SOC_ENUM_SINGLE_DECL(ctrl_enum_cs_channel,
459 STM32_SPDIFRX_CR, SPDIFRX_CR_CHSEL_SHIFT,
460 spdifrx_enum_cs_channel);
462 static int stm32_spdifrx_info(struct snd_kcontrol *kcontrol,
463 struct snd_ctl_elem_info *uinfo)
465 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
471 static int stm32_spdifrx_ub_info(struct snd_kcontrol *kcontrol,
472 struct snd_ctl_elem_info *uinfo)
474 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
480 static int stm32_spdifrx_get_ctrl_data(struct stm32_spdifrx_data *spdifrx)
484 memset(spdifrx->cs, 0, SPDIFRX_CS_BYTES_NB);
485 memset(spdifrx->ub, 0, SPDIFRX_UB_BYTES_NB);
487 pinctrl_pm_select_default_state(&spdifrx->pdev->dev);
489 ret = stm32_spdifrx_dma_ctrl_start(spdifrx);
493 ret = clk_prepare_enable(spdifrx->kclk);
495 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret);
499 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
500 SPDIFRX_CR_CBDMAEN, SPDIFRX_CR_CBDMAEN);
504 ret = stm32_spdifrx_start_sync(spdifrx);
508 if (wait_for_completion_interruptible_timeout(&spdifrx->cs_completion,
509 msecs_to_jiffies(100))
511 dev_dbg(&spdifrx->pdev->dev, "Failed to get control data\n");
515 stm32_spdifrx_stop(spdifrx);
516 stm32_spdifrx_dma_ctrl_stop(spdifrx);
519 clk_disable_unprepare(spdifrx->kclk);
520 pinctrl_pm_select_sleep_state(&spdifrx->pdev->dev);
525 static int stm32_spdifrx_capture_get(struct snd_kcontrol *kcontrol,
526 struct snd_ctl_elem_value *ucontrol)
528 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
529 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
531 stm32_spdifrx_get_ctrl_data(spdifrx);
533 ucontrol->value.iec958.status[0] = spdifrx->cs[0];
534 ucontrol->value.iec958.status[1] = spdifrx->cs[1];
535 ucontrol->value.iec958.status[2] = spdifrx->cs[2];
536 ucontrol->value.iec958.status[3] = spdifrx->cs[3];
537 ucontrol->value.iec958.status[4] = spdifrx->cs[4];
542 static int stm32_spdif_user_bits_get(struct snd_kcontrol *kcontrol,
543 struct snd_ctl_elem_value *ucontrol)
545 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
546 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
548 stm32_spdifrx_get_ctrl_data(spdifrx);
550 ucontrol->value.iec958.status[0] = spdifrx->ub[0];
551 ucontrol->value.iec958.status[1] = spdifrx->ub[1];
552 ucontrol->value.iec958.status[2] = spdifrx->ub[2];
553 ucontrol->value.iec958.status[3] = spdifrx->ub[3];
554 ucontrol->value.iec958.status[4] = spdifrx->ub[4];
559 static struct snd_kcontrol_new stm32_spdifrx_iec_ctrls[] = {
560 /* Channel status control */
562 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
563 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
564 .access = SNDRV_CTL_ELEM_ACCESS_READ |
565 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
566 .info = stm32_spdifrx_info,
567 .get = stm32_spdifrx_capture_get,
569 /* User bits control */
571 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
572 .name = "IEC958 User Bit Capture Default",
573 .access = SNDRV_CTL_ELEM_ACCESS_READ |
574 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
575 .info = stm32_spdifrx_ub_info,
576 .get = stm32_spdif_user_bits_get,
580 static struct snd_kcontrol_new stm32_spdifrx_ctrls[] = {
581 SOC_ENUM("SPDIFRX input", ctrl_enum_input),
582 SOC_ENUM("SPDIFRX CS channel", ctrl_enum_cs_channel),
585 static int stm32_spdifrx_dai_register_ctrls(struct snd_soc_dai *cpu_dai)
589 ret = snd_soc_add_dai_controls(cpu_dai, stm32_spdifrx_iec_ctrls,
590 ARRAY_SIZE(stm32_spdifrx_iec_ctrls));
594 return snd_soc_add_component_controls(cpu_dai->component,
596 ARRAY_SIZE(stm32_spdifrx_ctrls));
599 static int stm32_spdifrx_dai_probe(struct snd_soc_dai *cpu_dai)
601 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(cpu_dai->dev);
603 spdifrx->dma_params.addr = (dma_addr_t)(spdifrx->phys_addr +
605 spdifrx->dma_params.maxburst = 1;
607 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params);
609 return stm32_spdifrx_dai_register_ctrls(cpu_dai);
612 static bool stm32_spdifrx_readable_reg(struct device *dev, unsigned int reg)
615 case STM32_SPDIFRX_CR:
616 case STM32_SPDIFRX_IMR:
617 case STM32_SPDIFRX_SR:
618 case STM32_SPDIFRX_IFCR:
619 case STM32_SPDIFRX_DR:
620 case STM32_SPDIFRX_CSR:
621 case STM32_SPDIFRX_DIR:
622 case STM32_SPDIFRX_VERR:
623 case STM32_SPDIFRX_IDR:
624 case STM32_SPDIFRX_SIDR:
631 static bool stm32_spdifrx_volatile_reg(struct device *dev, unsigned int reg)
634 case STM32_SPDIFRX_DR:
635 case STM32_SPDIFRX_CSR:
636 case STM32_SPDIFRX_SR:
637 case STM32_SPDIFRX_DIR:
644 static bool stm32_spdifrx_writeable_reg(struct device *dev, unsigned int reg)
647 case STM32_SPDIFRX_CR:
648 case STM32_SPDIFRX_IMR:
649 case STM32_SPDIFRX_IFCR:
656 static const struct regmap_config stm32_h7_spdifrx_regmap_conf = {
660 .max_register = STM32_SPDIFRX_SIDR,
661 .readable_reg = stm32_spdifrx_readable_reg,
662 .volatile_reg = stm32_spdifrx_volatile_reg,
663 .writeable_reg = stm32_spdifrx_writeable_reg,
664 .num_reg_defaults_raw = STM32_SPDIFRX_SIDR / sizeof(u32) + 1,
666 .cache_type = REGCACHE_FLAT,
669 static irqreturn_t stm32_spdifrx_isr(int irq, void *devid)
671 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)devid;
672 struct platform_device *pdev = spdifrx->pdev;
673 unsigned int cr, mask, sr, imr;
674 unsigned int flags, sync_state;
675 int err = 0, err_xrun = 0;
677 regmap_read(spdifrx->regmap, STM32_SPDIFRX_SR, &sr);
678 regmap_read(spdifrx->regmap, STM32_SPDIFRX_IMR, &imr);
680 mask = imr & SPDIFRX_XIMR_MASK;
681 /* SERR, TERR, FERR IRQs are generated if IFEIE is set */
682 if (mask & SPDIFRX_IMR_IFEIE)
683 mask |= (SPDIFRX_IMR_IFEIE << 1) | (SPDIFRX_IMR_IFEIE << 2);
687 dev_err(&pdev->dev, "Unexpected IRQ. rflags=%#x, imr=%#x\n",
693 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR,
694 SPDIFRX_XIFCR_MASK, flags);
696 if (flags & SPDIFRX_SR_PERR) {
697 dev_dbg(&pdev->dev, "Parity error\n");
701 if (flags & SPDIFRX_SR_OVR) {
702 dev_dbg(&pdev->dev, "Overrun error\n");
706 if (flags & SPDIFRX_SR_SBD)
707 dev_dbg(&pdev->dev, "Synchronization block detected\n");
709 if (flags & SPDIFRX_SR_SYNCD) {
710 dev_dbg(&pdev->dev, "Synchronization done\n");
713 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_ENABLE);
714 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
715 SPDIFRX_CR_SPDIFEN_MASK, cr);
718 if (flags & SPDIFRX_SR_FERR) {
719 dev_dbg(&pdev->dev, "Frame error\n");
723 if (flags & SPDIFRX_SR_SERR) {
724 dev_dbg(&pdev->dev, "Synchronization error\n");
728 if (flags & SPDIFRX_SR_TERR) {
729 dev_dbg(&pdev->dev, "Timeout error\n");
734 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr);
735 sync_state = FIELD_GET(SPDIFRX_CR_SPDIFEN_MASK, cr) &&
736 SPDIFRX_SPDIFEN_SYNC;
738 /* SPDIFRX is in STATE_STOP. Disable SPDIFRX to clear errors */
739 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE);
740 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
741 SPDIFRX_CR_SPDIFEN_MASK, cr);
743 /* If SPDIFRX was in STATE_SYNC, retry synchro */
745 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC);
746 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
747 SPDIFRX_CR_SPDIFEN_MASK, cr);
751 spin_lock(&spdifrx->irq_lock);
752 if (spdifrx->substream)
753 snd_pcm_stop(spdifrx->substream,
754 SNDRV_PCM_STATE_DISCONNECTED);
755 spin_unlock(&spdifrx->irq_lock);
760 spin_lock(&spdifrx->irq_lock);
761 if (err_xrun && spdifrx->substream)
762 snd_pcm_stop_xrun(spdifrx->substream);
763 spin_unlock(&spdifrx->irq_lock);
768 static int stm32_spdifrx_startup(struct snd_pcm_substream *substream,
769 struct snd_soc_dai *cpu_dai)
771 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
775 spin_lock_irqsave(&spdifrx->irq_lock, flags);
776 spdifrx->substream = substream;
777 spin_unlock_irqrestore(&spdifrx->irq_lock, flags);
779 ret = clk_prepare_enable(spdifrx->kclk);
781 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret);
786 static int stm32_spdifrx_hw_params(struct snd_pcm_substream *substream,
787 struct snd_pcm_hw_params *params,
788 struct snd_soc_dai *cpu_dai)
790 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
791 int data_size = params_width(params);
796 fmt = SPDIFRX_DRFMT_PACKED;
799 fmt = SPDIFRX_DRFMT_LEFT;
802 dev_err(&spdifrx->pdev->dev, "Unexpected data format\n");
807 * Set buswidth to 4 bytes for all data formats.
808 * Packed format: transfer 2 x 2 bytes samples
809 * Left format: transfer 1 x 3 bytes samples + 1 dummy byte
811 spdifrx->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
812 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params);
814 return regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
815 SPDIFRX_CR_DRFMT_MASK,
816 SPDIFRX_CR_DRFMTSET(fmt));
819 static int stm32_spdifrx_trigger(struct snd_pcm_substream *substream, int cmd,
820 struct snd_soc_dai *cpu_dai)
822 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
826 case SNDRV_PCM_TRIGGER_START:
827 case SNDRV_PCM_TRIGGER_RESUME:
828 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
829 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR,
830 SPDIFRX_IMR_OVRIE, SPDIFRX_IMR_OVRIE);
832 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
833 SPDIFRX_CR_RXDMAEN, SPDIFRX_CR_RXDMAEN);
835 ret = stm32_spdifrx_start_sync(spdifrx);
837 case SNDRV_PCM_TRIGGER_SUSPEND:
838 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
839 case SNDRV_PCM_TRIGGER_STOP:
840 stm32_spdifrx_stop(spdifrx);
849 static void stm32_spdifrx_shutdown(struct snd_pcm_substream *substream,
850 struct snd_soc_dai *cpu_dai)
852 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
855 spin_lock_irqsave(&spdifrx->irq_lock, flags);
856 spdifrx->substream = NULL;
857 spin_unlock_irqrestore(&spdifrx->irq_lock, flags);
859 clk_disable_unprepare(spdifrx->kclk);
862 static const struct snd_soc_dai_ops stm32_spdifrx_pcm_dai_ops = {
863 .startup = stm32_spdifrx_startup,
864 .hw_params = stm32_spdifrx_hw_params,
865 .trigger = stm32_spdifrx_trigger,
866 .shutdown = stm32_spdifrx_shutdown,
869 static struct snd_soc_dai_driver stm32_spdifrx_dai[] = {
871 .probe = stm32_spdifrx_dai_probe,
873 .stream_name = "CPU-Capture",
876 .rates = SNDRV_PCM_RATE_8000_192000,
877 .formats = SNDRV_PCM_FMTBIT_S32_LE |
878 SNDRV_PCM_FMTBIT_S16_LE,
880 .ops = &stm32_spdifrx_pcm_dai_ops,
884 static const struct snd_pcm_hardware stm32_spdifrx_pcm_hw = {
885 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
886 .buffer_bytes_max = 8 * PAGE_SIZE,
887 .period_bytes_min = 1024,
888 .period_bytes_max = 4 * PAGE_SIZE,
893 static const struct snd_soc_component_driver stm32_spdifrx_component = {
894 .name = "stm32-spdifrx",
897 static const struct snd_dmaengine_pcm_config stm32_spdifrx_pcm_config = {
898 .pcm_hardware = &stm32_spdifrx_pcm_hw,
899 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
902 static const struct of_device_id stm32_spdifrx_ids[] = {
904 .compatible = "st,stm32h7-spdifrx",
905 .data = &stm32_h7_spdifrx_regmap_conf
910 static int stm32_spdifrx_parse_of(struct platform_device *pdev,
911 struct stm32_spdifrx_data *spdifrx)
913 struct device_node *np = pdev->dev.of_node;
914 const struct of_device_id *of_id;
915 struct resource *res;
920 of_id = of_match_device(stm32_spdifrx_ids, &pdev->dev);
922 spdifrx->regmap_conf =
923 (const struct regmap_config *)of_id->data;
927 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
928 spdifrx->base = devm_ioremap_resource(&pdev->dev, res);
929 if (IS_ERR(spdifrx->base))
930 return PTR_ERR(spdifrx->base);
932 spdifrx->phys_addr = res->start;
934 spdifrx->kclk = devm_clk_get(&pdev->dev, "kclk");
935 if (IS_ERR(spdifrx->kclk)) {
936 dev_err(&pdev->dev, "Could not get kclk\n");
937 return PTR_ERR(spdifrx->kclk);
940 spdifrx->irq = platform_get_irq(pdev, 0);
941 if (spdifrx->irq < 0)
947 static int stm32_spdifrx_probe(struct platform_device *pdev)
949 struct stm32_spdifrx_data *spdifrx;
950 struct reset_control *rst;
951 const struct snd_dmaengine_pcm_config *pcm_config = NULL;
955 spdifrx = devm_kzalloc(&pdev->dev, sizeof(*spdifrx), GFP_KERNEL);
959 spdifrx->pdev = pdev;
960 init_completion(&spdifrx->cs_completion);
961 spin_lock_init(&spdifrx->lock);
962 spin_lock_init(&spdifrx->irq_lock);
964 platform_set_drvdata(pdev, spdifrx);
966 ret = stm32_spdifrx_parse_of(pdev, spdifrx);
970 spdifrx->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "kclk",
972 spdifrx->regmap_conf);
973 if (IS_ERR(spdifrx->regmap)) {
974 dev_err(&pdev->dev, "Regmap init failed\n");
975 return PTR_ERR(spdifrx->regmap);
978 ret = devm_request_irq(&pdev->dev, spdifrx->irq, stm32_spdifrx_isr, 0,
979 dev_name(&pdev->dev), spdifrx);
981 dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
985 rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
987 reset_control_assert(rst);
989 reset_control_deassert(rst);
992 ret = devm_snd_soc_register_component(&pdev->dev,
993 &stm32_spdifrx_component,
995 ARRAY_SIZE(stm32_spdifrx_dai));
999 ret = stm32_spdifrx_dma_ctrl_register(&pdev->dev, spdifrx);
1003 pcm_config = &stm32_spdifrx_pcm_config;
1004 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, pcm_config, 0);
1006 dev_err(&pdev->dev, "PCM DMA register returned %d\n", ret);
1010 ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_IDR, &idr);
1014 if (idr == SPDIFRX_IPIDR_NUMBER) {
1015 ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_VERR, &ver);
1017 dev_dbg(&pdev->dev, "SPDIFRX version: %lu.%lu registered\n",
1018 FIELD_GET(SPDIFRX_VERR_MAJ_MASK, ver),
1019 FIELD_GET(SPDIFRX_VERR_MIN_MASK, ver));
1025 if (!IS_ERR(spdifrx->ctrl_chan))
1026 dma_release_channel(spdifrx->ctrl_chan);
1028 snd_dma_free_pages(spdifrx->dmab);
1033 static int stm32_spdifrx_remove(struct platform_device *pdev)
1035 struct stm32_spdifrx_data *spdifrx = platform_get_drvdata(pdev);
1037 if (spdifrx->ctrl_chan)
1038 dma_release_channel(spdifrx->ctrl_chan);
1041 snd_dma_free_pages(spdifrx->dmab);
1046 MODULE_DEVICE_TABLE(of, stm32_spdifrx_ids);
1048 #ifdef CONFIG_PM_SLEEP
1049 static int stm32_spdifrx_suspend(struct device *dev)
1051 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev);
1053 regcache_cache_only(spdifrx->regmap, true);
1054 regcache_mark_dirty(spdifrx->regmap);
1059 static int stm32_spdifrx_resume(struct device *dev)
1061 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev);
1063 regcache_cache_only(spdifrx->regmap, false);
1065 return regcache_sync(spdifrx->regmap);
1067 #endif /* CONFIG_PM_SLEEP */
1069 static const struct dev_pm_ops stm32_spdifrx_pm_ops = {
1070 SET_SYSTEM_SLEEP_PM_OPS(stm32_spdifrx_suspend, stm32_spdifrx_resume)
1073 static struct platform_driver stm32_spdifrx_driver = {
1075 .name = "st,stm32-spdifrx",
1076 .of_match_table = stm32_spdifrx_ids,
1077 .pm = &stm32_spdifrx_pm_ops,
1079 .probe = stm32_spdifrx_probe,
1080 .remove = stm32_spdifrx_remove,
1083 module_platform_driver(stm32_spdifrx_driver);
1085 MODULE_DESCRIPTION("STM32 Soc spdifrx Interface");
1086 MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
1087 MODULE_ALIAS("platform:stm32-spdifrx");
1088 MODULE_LICENSE("GPL v2");