sound/soc/stm/stm32_sai.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * STM32 ALSA SoC Digital Audio Interface (SAI) driver.
   4  *
   5  * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
   6  * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
   7  */
   8
   9 #include <linux/bitfield.h>
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/module.h>
  13 #include <linux/of_platform.h>
  14 #include <linux/pinctrl/consumer.h>
  15 #include <linux/reset.h>
  16
  17 #include <sound/dmaengine_pcm.h>
  18 #include <sound/core.h>
  19
  20 #include "stm32_sai.h"
  21
  22 static const struct stm32_sai_conf stm32_sai_conf_f4 = {
  23         .version = STM_SAI_STM32F4,
  24         .fifo_size = 8,
  25         .has_spdif_pdm = false,
  26 };
  27
  28 /*
  29  * Default settings for stm32 H7 socs and next.
  30  * These default settings will be overridden if the soc provides
  31  * support of hardware configuration registers.
  32  */
  33 static const struct stm32_sai_conf stm32_sai_conf_h7 = {
  34         .version = STM_SAI_STM32H7,
  35         .fifo_size = 8,
  36         .has_spdif_pdm = true,
  37 };
  38
  39 static const struct of_device_id stm32_sai_ids[] = {
  40         { .compatible = "st,stm32f4-sai", .data = (void *)&stm32_sai_conf_f4 },
  41         { .compatible = "st,stm32h7-sai", .data = (void *)&stm32_sai_conf_h7 },
  42         {}
  43 };
  44
  45 static int stm32_sai_pclk_disable(struct device *dev)
  46 {
  47         struct stm32_sai_data *sai = dev_get_drvdata(dev);
  48
  49         clk_disable_unprepare(sai->pclk);
  50
  51         return 0;
  52 }
  53
  54 static int stm32_sai_pclk_enable(struct device *dev)
  55 {
  56         struct stm32_sai_data *sai = dev_get_drvdata(dev);
  57         int ret;
  58
  59         ret = clk_prepare_enable(sai->pclk);
  60         if (ret) {
  61                 dev_err(&sai->pdev->dev, "failed to enable clock: %d\n", ret);
  62                 return ret;
  63         }
  64
  65         return 0;
  66 }
  67
  68 static int stm32_sai_sync_conf_client(struct stm32_sai_data *sai, int synci)
  69 {
  70         int ret;
  71
  72         /* Enable peripheral clock to allow GCR register access */
  73         ret = stm32_sai_pclk_enable(&sai->pdev->dev);
  74         if (ret)
  75                 return ret;
  76
  77         writel_relaxed(FIELD_PREP(SAI_GCR_SYNCIN_MASK, (synci - 1)), sai->base);
  78
  79         stm32_sai_pclk_disable(&sai->pdev->dev);
  80
  81         return 0;
  82 }
  83
  84 static int stm32_sai_sync_conf_provider(struct stm32_sai_data *sai, int synco)
  85 {
  86         u32 prev_synco;
  87         int ret;
  88
  89         /* Enable peripheral clock to allow GCR register access */
  90         ret = stm32_sai_pclk_enable(&sai->pdev->dev);
  91         if (ret)
  92                 return ret;
  93
  94         dev_dbg(&sai->pdev->dev, "Set %pOFn%s as synchro provider\n",
  95                 sai->pdev->dev.of_node,
  96                 synco == STM_SAI_SYNC_OUT_A ? "A" : "B");
  97
  98         prev_synco = FIELD_GET(SAI_GCR_SYNCOUT_MASK, readl_relaxed(sai->base));
  99         if (prev_synco != STM_SAI_SYNC_OUT_NONE && synco != prev_synco) {
 100                 dev_err(&sai->pdev->dev, "%pOFn%s already set as sync provider\n",
 101                         sai->pdev->dev.of_node,
 102                         prev_synco == STM_SAI_SYNC_OUT_A ? "A" : "B");
 103                 stm32_sai_pclk_disable(&sai->pdev->dev);
 104                 return -EINVAL;
 105         }
 106
 107         writel_relaxed(FIELD_PREP(SAI_GCR_SYNCOUT_MASK, synco), sai->base);
 108
 109         stm32_sai_pclk_disable(&sai->pdev->dev);
 110
 111         return 0;
 112 }
 113
 114 static int stm32_sai_set_sync(struct stm32_sai_data *sai_client,
 115                               struct device_node *np_provider,
 116                               int synco, int synci)
 117 {
 118         struct platform_device *pdev = of_find_device_by_node(np_provider);
 119         struct stm32_sai_data *sai_provider;
 120         int ret;
 121
 122         if (!pdev) {
 123                 dev_err(&sai_client->pdev->dev,
 124                         "Device not found for node %pOFn\n", np_provider);
 125                 of_node_put(np_provider);
 126                 return -ENODEV;
 127         }
 128
 129         sai_provider = platform_get_drvdata(pdev);
 130         if (!sai_provider) {
 131                 dev_err(&sai_client->pdev->dev,
 132                         "SAI sync provider data not found\n");
 133                 ret = -EINVAL;
 134                 goto error;
 135         }
 136
 137         /* Configure sync client */
 138         ret = stm32_sai_sync_conf_client(sai_client, synci);
 139         if (ret < 0)
 140                 goto error;
 141
 142         /* Configure sync provider */
 143         ret = stm32_sai_sync_conf_provider(sai_provider, synco);
 144
 145 error:
 146         put_device(&pdev->dev);
 147         of_node_put(np_provider);
 148         return ret;
 149 }
 150
 151 static int stm32_sai_probe(struct platform_device *pdev)
 152 {
 153         struct stm32_sai_data *sai;
 154         struct reset_control *rst;
 155         const struct of_device_id *of_id;
 156         u32 val;
 157         int ret;
 158
 159         sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
 160         if (!sai)
 161                 return -ENOMEM;
 162
 163         sai->base = devm_platform_ioremap_resource(pdev, 0);
 164         if (IS_ERR(sai->base))
 165                 return PTR_ERR(sai->base);
 166
 167         of_id = of_match_device(stm32_sai_ids, &pdev->dev);
 168         if (of_id)
 169                 memcpy(&sai->conf, (const struct stm32_sai_conf *)of_id->data,
 170                        sizeof(struct stm32_sai_conf));
 171         else
 172                 return -EINVAL;
 173
 174         if (!STM_SAI_IS_F4(sai)) {
 175                 sai->pclk = devm_clk_get(&pdev->dev, "pclk");
 176                 if (IS_ERR(sai->pclk))
 177                         return dev_err_probe(&pdev->dev, PTR_ERR(sai->pclk),
 178                                              "missing bus clock pclk\n");
 179         }
 180
 181         sai->clk_x8k = devm_clk_get(&pdev->dev, "x8k");
 182         if (IS_ERR(sai->clk_x8k))
 183                 return dev_err_probe(&pdev->dev, PTR_ERR(sai->clk_x8k),
 184                                      "missing x8k parent clock\n");
 185
 186         sai->clk_x11k = devm_clk_get(&pdev->dev, "x11k");
 187         if (IS_ERR(sai->clk_x11k))
 188                 return dev_err_probe(&pdev->dev, PTR_ERR(sai->clk_x11k),
 189                                      "missing x11k parent clock\n");
 190
 191         /* init irqs */
 192         sai->irq = platform_get_irq(pdev, 0);
 193         if (sai->irq < 0)
 194                 return sai->irq;
 195
 196         /* reset */
 197         rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
 198         if (IS_ERR(rst))
 199                 return dev_err_probe(&pdev->dev, PTR_ERR(rst),
 200                                      "Reset controller error\n");
 201
 202         reset_control_assert(rst);
 203         udelay(2);
 204         reset_control_deassert(rst);
 205
 206         /* Enable peripheral clock to allow register access */
 207         ret = clk_prepare_enable(sai->pclk);
 208         if (ret) {
 209                 dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
 210                 return ret;
 211         }
 212
 213         val = FIELD_GET(SAI_IDR_ID_MASK,
 214                         readl_relaxed(sai->base + STM_SAI_IDR));
 215         if (val == SAI_IPIDR_NUMBER) {
 216                 val = readl_relaxed(sai->base + STM_SAI_HWCFGR);
 217                 sai->conf.fifo_size = FIELD_GET(SAI_HWCFGR_FIFO_SIZE, val);
 218                 sai->conf.has_spdif_pdm = !!FIELD_GET(SAI_HWCFGR_SPDIF_PDM,
 219                                                       val);
 220
 221                 val = readl_relaxed(sai->base + STM_SAI_VERR);
 222                 sai->conf.version = val;
 223
 224                 dev_dbg(&pdev->dev, "SAI version: %lu.%lu registered\n",
 225                         FIELD_GET(SAI_VERR_MAJ_MASK, val),
 226                         FIELD_GET(SAI_VERR_MIN_MASK, val));
 227         }
 228         clk_disable_unprepare(sai->pclk);
 229
 230         sai->pdev = pdev;
 231         sai->set_sync = &stm32_sai_set_sync;
 232         platform_set_drvdata(pdev, sai);
 233
 234         return devm_of_platform_populate(&pdev->dev);
 235 }
 236
 237 #ifdef CONFIG_PM_SLEEP
 238 /*
 239  * When pins are shared by two sai sub instances, pins have to be defined
 240  * in sai parent node. In this case, pins state is not managed by alsa fw.
 241  * These pins are managed in suspend/resume callbacks.
 242  */
 243 static int stm32_sai_suspend(struct device *dev)
 244 {
 245         struct stm32_sai_data *sai = dev_get_drvdata(dev);
 246         int ret;
 247
 248         ret = stm32_sai_pclk_enable(dev);
 249         if (ret)
 250                 return ret;
 251
 252         sai->gcr = readl_relaxed(sai->base);
 253         stm32_sai_pclk_disable(dev);
 254
 255         return pinctrl_pm_select_sleep_state(dev);
 256 }
 257
 258 static int stm32_sai_resume(struct device *dev)
 259 {
 260         struct stm32_sai_data *sai = dev_get_drvdata(dev);
 261         int ret;
 262
 263         ret = stm32_sai_pclk_enable(dev);
 264         if (ret)
 265                 return ret;
 266
 267         writel_relaxed(sai->gcr, sai->base);
 268         stm32_sai_pclk_disable(dev);
 269
 270         return pinctrl_pm_select_default_state(dev);
 271 }
 272 #endif /* CONFIG_PM_SLEEP */
 273
 274 static const struct dev_pm_ops stm32_sai_pm_ops = {
 275         SET_SYSTEM_SLEEP_PM_OPS(stm32_sai_suspend, stm32_sai_resume)
 276 };
 277
 278 MODULE_DEVICE_TABLE(of, stm32_sai_ids);
 279
 280 static struct platform_driver stm32_sai_driver = {
 281         .driver = {
 282                 .name = "st,stm32-sai",
 283                 .of_match_table = stm32_sai_ids,
 284                 .pm = &stm32_sai_pm_ops,
 285         },
 286         .probe = stm32_sai_probe,
 287 };
 288
 289 module_platform_driver(stm32_sai_driver);
 290
 291 MODULE_DESCRIPTION("STM32 Soc SAI Interface");
 292 MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>");
 293 MODULE_ALIAS("platform:st,stm32-sai");
 294 MODULE_LICENSE("GPL v2");