sound/soc/stm/stm32_i2s.c

   1 /*
   2  *  STM32 ALSA SoC Digital Audio Interface (I2S) driver.
   3  *
   4  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   5  * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
   6  *
   7  * License terms: GPL V2.0.
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License version 2 as published by
  11  * the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
  16  * details.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/delay.h>
  21 #include <linux/module.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/regmap.h>
  25 #include <linux/reset.h>
  26 #include <linux/spinlock.h>
  27
  28 #include <sound/dmaengine_pcm.h>
  29 #include <sound/pcm_params.h>
  30
  31 #define STM32_I2S_CR1_REG       0x0
  32 #define STM32_I2S_CFG1_REG      0x08
  33 #define STM32_I2S_CFG2_REG      0x0C
  34 #define STM32_I2S_IER_REG       0x10
  35 #define STM32_I2S_SR_REG        0x14
  36 #define STM32_I2S_IFCR_REG      0x18
  37 #define STM32_I2S_TXDR_REG      0X20
  38 #define STM32_I2S_RXDR_REG      0x30
  39 #define STM32_I2S_CGFR_REG      0X50
  40
  41 /* Bit definition for SPI2S_CR1 register */
  42 #define I2S_CR1_SPE             BIT(0)
  43 #define I2S_CR1_CSTART          BIT(9)
  44 #define I2S_CR1_CSUSP           BIT(10)
  45 #define I2S_CR1_HDDIR           BIT(11)
  46 #define I2S_CR1_SSI             BIT(12)
  47 #define I2S_CR1_CRC33_17        BIT(13)
  48 #define I2S_CR1_RCRCI           BIT(14)
  49 #define I2S_CR1_TCRCI           BIT(15)
  50
  51 /* Bit definition for SPI_CFG2 register */
  52 #define I2S_CFG2_IOSWP_SHIFT    15
  53 #define I2S_CFG2_IOSWP          BIT(I2S_CFG2_IOSWP_SHIFT)
  54 #define I2S_CFG2_LSBFRST        BIT(23)
  55 #define I2S_CFG2_AFCNTR         BIT(31)
  56
  57 /* Bit definition for SPI_CFG1 register */
  58 #define I2S_CFG1_FTHVL_SHIFT    5
  59 #define I2S_CFG1_FTHVL_MASK     GENMASK(8, I2S_CFG1_FTHVL_SHIFT)
  60 #define I2S_CFG1_FTHVL_SET(x)   ((x) << I2S_CFG1_FTHVL_SHIFT)
  61
  62 #define I2S_CFG1_TXDMAEN        BIT(15)
  63 #define I2S_CFG1_RXDMAEN        BIT(14)
  64
  65 /* Bit definition for SPI2S_IER register */
  66 #define I2S_IER_RXPIE           BIT(0)
  67 #define I2S_IER_TXPIE           BIT(1)
  68 #define I2S_IER_DPXPIE          BIT(2)
  69 #define I2S_IER_EOTIE           BIT(3)
  70 #define I2S_IER_TXTFIE          BIT(4)
  71 #define I2S_IER_UDRIE           BIT(5)
  72 #define I2S_IER_OVRIE           BIT(6)
  73 #define I2S_IER_CRCEIE          BIT(7)
  74 #define I2S_IER_TIFREIE         BIT(8)
  75 #define I2S_IER_MODFIE          BIT(9)
  76 #define I2S_IER_TSERFIE         BIT(10)
  77
  78 /* Bit definition for SPI2S_SR register */
  79 #define I2S_SR_RXP              BIT(0)
  80 #define I2S_SR_TXP              BIT(1)
  81 #define I2S_SR_DPXP             BIT(2)
  82 #define I2S_SR_EOT              BIT(3)
  83 #define I2S_SR_TXTF             BIT(4)
  84 #define I2S_SR_UDR              BIT(5)
  85 #define I2S_SR_OVR              BIT(6)
  86 #define I2S_SR_CRCERR           BIT(7)
  87 #define I2S_SR_TIFRE            BIT(8)
  88 #define I2S_SR_MODF             BIT(9)
  89 #define I2S_SR_TSERF            BIT(10)
  90 #define I2S_SR_SUSP             BIT(11)
  91 #define I2S_SR_TXC              BIT(12)
  92 #define I2S_SR_RXPLVL           GENMASK(14, 13)
  93 #define I2S_SR_RXWNE            BIT(15)
  94
  95 #define I2S_SR_MASK             GENMASK(15, 0)
  96
  97 /* Bit definition for SPI_IFCR register */
  98 #define I2S_IFCR_EOTC           BIT(3)
  99 #define I2S_IFCR_TXTFC          BIT(4)
 100 #define I2S_IFCR_UDRC           BIT(5)
 101 #define I2S_IFCR_OVRC           BIT(6)
 102 #define I2S_IFCR_CRCEC          BIT(7)
 103 #define I2S_IFCR_TIFREC         BIT(8)
 104 #define I2S_IFCR_MODFC          BIT(9)
 105 #define I2S_IFCR_TSERFC         BIT(10)
 106 #define I2S_IFCR_SUSPC          BIT(11)
 107
 108 #define I2S_IFCR_MASK           GENMASK(11, 3)
 109
 110 /* Bit definition for SPI_I2SCGFR register */
 111 #define I2S_CGFR_I2SMOD         BIT(0)
 112
 113 #define I2S_CGFR_I2SCFG_SHIFT   1
 114 #define I2S_CGFR_I2SCFG_MASK    GENMASK(3, I2S_CGFR_I2SCFG_SHIFT)
 115 #define I2S_CGFR_I2SCFG_SET(x)  ((x) << I2S_CGFR_I2SCFG_SHIFT)
 116
 117 #define I2S_CGFR_I2SSTD_SHIFT   4
 118 #define I2S_CGFR_I2SSTD_MASK    GENMASK(5, I2S_CGFR_I2SSTD_SHIFT)
 119 #define I2S_CGFR_I2SSTD_SET(x)  ((x) << I2S_CGFR_I2SSTD_SHIFT)
 120
 121 #define I2S_CGFR_PCMSYNC        BIT(7)
 122
 123 #define I2S_CGFR_DATLEN_SHIFT   8
 124 #define I2S_CGFR_DATLEN_MASK    GENMASK(9, I2S_CGFR_DATLEN_SHIFT)
 125 #define I2S_CGFR_DATLEN_SET(x)  ((x) << I2S_CGFR_DATLEN_SHIFT)
 126
 127 #define I2S_CGFR_CHLEN_SHIFT    10
 128 #define I2S_CGFR_CHLEN          BIT(I2S_CGFR_CHLEN_SHIFT)
 129 #define I2S_CGFR_CKPOL          BIT(11)
 130 #define I2S_CGFR_FIXCH          BIT(12)
 131 #define I2S_CGFR_WSINV          BIT(13)
 132 #define I2S_CGFR_DATFMT         BIT(14)
 133
 134 #define I2S_CGFR_I2SDIV_SHIFT   16
 135 #define I2S_CGFR_I2SDIV_BIT_H   23
 136 #define I2S_CGFR_I2SDIV_MASK    GENMASK(I2S_CGFR_I2SDIV_BIT_H,\
 137                                 I2S_CGFR_I2SDIV_SHIFT)
 138 #define I2S_CGFR_I2SDIV_SET(x)  ((x) << I2S_CGFR_I2SDIV_SHIFT)
 139 #define I2S_CGFR_I2SDIV_MAX     ((1 << (I2S_CGFR_I2SDIV_BIT_H -\
 140                                 I2S_CGFR_I2SDIV_SHIFT)) - 1)
 141
 142 #define I2S_CGFR_ODD_SHIFT      24
 143 #define I2S_CGFR_ODD            BIT(I2S_CGFR_ODD_SHIFT)
 144 #define I2S_CGFR_MCKOE          BIT(25)
 145
 146 enum i2s_master_mode {
 147         I2S_MS_NOT_SET,
 148         I2S_MS_MASTER,
 149         I2S_MS_SLAVE,
 150 };
 151
 152 enum i2s_mode {
 153         I2S_I2SMOD_TX_SLAVE,
 154         I2S_I2SMOD_RX_SLAVE,
 155         I2S_I2SMOD_TX_MASTER,
 156         I2S_I2SMOD_RX_MASTER,
 157         I2S_I2SMOD_FD_SLAVE,
 158         I2S_I2SMOD_FD_MASTER,
 159 };
 160
 161 enum i2s_fifo_th {
 162         I2S_FIFO_TH_NONE,
 163         I2S_FIFO_TH_ONE_QUARTER,
 164         I2S_FIFO_TH_HALF,
 165         I2S_FIFO_TH_THREE_QUARTER,
 166         I2S_FIFO_TH_FULL,
 167 };
 168
 169 enum i2s_std {
 170         I2S_STD_I2S,
 171         I2S_STD_LEFT_J,
 172         I2S_STD_RIGHT_J,
 173         I2S_STD_DSP,
 174 };
 175
 176 enum i2s_datlen {
 177         I2S_I2SMOD_DATLEN_16,
 178         I2S_I2SMOD_DATLEN_24,
 179         I2S_I2SMOD_DATLEN_32,
 180 };
 181
 182 #define STM32_I2S_DAI_NAME_SIZE         20
 183 #define STM32_I2S_FIFO_SIZE             16
 184
 185 #define STM32_I2S_IS_MASTER(x)          ((x)->ms_flg == I2S_MS_MASTER)
 186 #define STM32_I2S_IS_SLAVE(x)           ((x)->ms_flg == I2S_MS_SLAVE)
 187
 188 /**
 189  * struct stm32_i2s_data - private data of I2S
 190  * @regmap_conf: I2S register map configuration pointer
 191  * @regmap: I2S register map pointer
 192  * @pdev: device data pointer
 193  * @dai_drv: DAI driver pointer
 194  * @dma_data_tx: dma configuration data for tx channel
 195  * @dma_data_rx: dma configuration data for tx channel
 196  * @substream: PCM substream data pointer
 197  * @i2sclk: kernel clock feeding the I2S clock generator
 198  * @pclk: peripheral clock driving bus interface
 199  * @x8kclk: I2S parent clock for sampling frequencies multiple of 8kHz
 200  * @x11kclk: I2S parent clock for sampling frequencies multiple of 11kHz
 201  * @base:  mmio register base virtual address
 202  * @phys_addr: I2S registers physical base address
 203  * @lock_fd: lock to manage race conditions in full duplex mode
 204  * @irq_lock: prevent race condition with IRQ
 205  * @dais_name: DAI name
 206  * @mclk_rate: master clock frequency (Hz)
 207  * @fmt: DAI protocol
 208  * @refcount: keep count of opened streams on I2S
 209  * @ms_flg: master mode flag.
 210  */
 211 struct stm32_i2s_data {
 212         const struct regmap_config *regmap_conf;
 213         struct regmap *regmap;
 214         struct platform_device *pdev;
 215         struct snd_soc_dai_driver *dai_drv;
 216         struct snd_dmaengine_dai_dma_data dma_data_tx;
 217         struct snd_dmaengine_dai_dma_data dma_data_rx;
 218         struct snd_pcm_substream *substream;
 219         struct clk *i2sclk;
 220         struct clk *pclk;
 221         struct clk *x8kclk;
 222         struct clk *x11kclk;
 223         void __iomem *base;
 224         dma_addr_t phys_addr;
 225         spinlock_t lock_fd; /* Manage race conditions for full duplex */
 226         spinlock_t irq_lock; /* used to prevent race condition with IRQ */
 227         char dais_name[STM32_I2S_DAI_NAME_SIZE];
 228         unsigned int mclk_rate;
 229         unsigned int fmt;
 230         int refcount;
 231         int ms_flg;
 232 };
 233
 234 static irqreturn_t stm32_i2s_isr(int irq, void *devid)
 235 {
 236         struct stm32_i2s_data *i2s = (struct stm32_i2s_data *)devid;
 237         struct platform_device *pdev = i2s->pdev;
 238         u32 sr, ier;
 239         unsigned long flags;
 240         int err = 0;
 241
 242         regmap_read(i2s->regmap, STM32_I2S_SR_REG, &sr);
 243         regmap_read(i2s->regmap, STM32_I2S_IER_REG, &ier);
 244
 245         flags = sr & ier;
 246         if (!flags) {
 247                 dev_dbg(&pdev->dev, "Spurious IRQ sr=0x%08x, ier=0x%08x\n",
 248                         sr, ier);
 249                 return IRQ_NONE;
 250         }
 251
 252         regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
 253                           I2S_IFCR_MASK, flags);
 254
 255         if (flags & I2S_SR_OVR) {
 256                 dev_dbg(&pdev->dev, "Overrun\n");
 257                 err = 1;
 258         }
 259
 260         if (flags & I2S_SR_UDR) {
 261                 dev_dbg(&pdev->dev, "Underrun\n");
 262                 err = 1;
 263         }
 264
 265         if (flags & I2S_SR_TIFRE)
 266                 dev_dbg(&pdev->dev, "Frame error\n");
 267
 268         spin_lock(&i2s->irq_lock);
 269         if (err && i2s->substream)
 270                 snd_pcm_stop_xrun(i2s->substream);
 271         spin_unlock(&i2s->irq_lock);
 272
 273         return IRQ_HANDLED;
 274 }
 275
 276 static bool stm32_i2s_readable_reg(struct device *dev, unsigned int reg)
 277 {
 278         switch (reg) {
 279         case STM32_I2S_CR1_REG:
 280         case STM32_I2S_CFG1_REG:
 281         case STM32_I2S_CFG2_REG:
 282         case STM32_I2S_IER_REG:
 283         case STM32_I2S_SR_REG:
 284         case STM32_I2S_TXDR_REG:
 285         case STM32_I2S_RXDR_REG:
 286         case STM32_I2S_CGFR_REG:
 287                 return true;
 288         default:
 289                 return false;
 290         }
 291 }
 292
 293 static bool stm32_i2s_volatile_reg(struct device *dev, unsigned int reg)
 294 {
 295         switch (reg) {
 296         case STM32_I2S_TXDR_REG:
 297         case STM32_I2S_RXDR_REG:
 298                 return true;
 299         default:
 300                 return false;
 301         }
 302 }
 303
 304 static bool stm32_i2s_writeable_reg(struct device *dev, unsigned int reg)
 305 {
 306         switch (reg) {
 307         case STM32_I2S_CR1_REG:
 308         case STM32_I2S_CFG1_REG:
 309         case STM32_I2S_CFG2_REG:
 310         case STM32_I2S_IER_REG:
 311         case STM32_I2S_IFCR_REG:
 312         case STM32_I2S_TXDR_REG:
 313         case STM32_I2S_CGFR_REG:
 314                 return true;
 315         default:
 316                 return false;
 317         }
 318 }
 319
 320 static int stm32_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
 321 {
 322         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 323         u32 cgfr;
 324         u32 cgfr_mask =  I2S_CGFR_I2SSTD_MASK | I2S_CGFR_CKPOL |
 325                          I2S_CGFR_WSINV | I2S_CGFR_I2SCFG_MASK;
 326
 327         dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
 328
 329         /*
 330          * winv = 0 : default behavior (high/low) for all standards
 331          * ckpol = 0 for all standards.
 332          */
 333         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 334         case SND_SOC_DAIFMT_I2S:
 335                 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_I2S);
 336                 break;
 337         case SND_SOC_DAIFMT_MSB:
 338                 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_LEFT_J);
 339                 break;
 340         case SND_SOC_DAIFMT_LSB:
 341                 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_RIGHT_J);
 342                 break;
 343         case SND_SOC_DAIFMT_DSP_A:
 344                 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_DSP);
 345                 break;
 346         /* DSP_B not mapped on I2S PCM long format. 1 bit offset does not fit */
 347         default:
 348                 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
 349                         fmt & SND_SOC_DAIFMT_FORMAT_MASK);
 350                 return -EINVAL;
 351         }
 352
 353         /* DAI clock strobing */
 354         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 355         case SND_SOC_DAIFMT_NB_NF:
 356                 break;
 357         case SND_SOC_DAIFMT_IB_NF:
 358                 cgfr |= I2S_CGFR_CKPOL;
 359                 break;
 360         case SND_SOC_DAIFMT_NB_IF:
 361                 cgfr |= I2S_CGFR_WSINV;
 362                 break;
 363         case SND_SOC_DAIFMT_IB_IF:
 364                 cgfr |= I2S_CGFR_CKPOL;
 365                 cgfr |= I2S_CGFR_WSINV;
 366                 break;
 367         default:
 368                 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
 369                         fmt & SND_SOC_DAIFMT_INV_MASK);
 370                 return -EINVAL;
 371         }
 372
 373         /* DAI clock master masks */
 374         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 375         case SND_SOC_DAIFMT_CBM_CFM:
 376                 i2s->ms_flg = I2S_MS_SLAVE;
 377                 break;
 378         case SND_SOC_DAIFMT_CBS_CFS:
 379                 i2s->ms_flg = I2S_MS_MASTER;
 380                 break;
 381         default:
 382                 dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
 383                         fmt & SND_SOC_DAIFMT_MASTER_MASK);
 384                 return -EINVAL;
 385         }
 386
 387         i2s->fmt = fmt;
 388         return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 389                                   cgfr_mask, cgfr);
 390 }
 391
 392 static int stm32_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
 393                                 int clk_id, unsigned int freq, int dir)
 394 {
 395         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 396
 397         dev_dbg(cpu_dai->dev, "I2S MCLK frequency is %uHz\n", freq);
 398
 399         if ((dir == SND_SOC_CLOCK_OUT) && STM32_I2S_IS_MASTER(i2s)) {
 400                 i2s->mclk_rate = freq;
 401
 402                 /* Enable master clock if master mode and mclk-fs are set */
 403                 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 404                                           I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
 405         }
 406
 407         return 0;
 408 }
 409
 410 static int stm32_i2s_configure_clock(struct snd_soc_dai *cpu_dai,
 411                                      struct snd_pcm_hw_params *params)
 412 {
 413         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 414         unsigned long i2s_clock_rate;
 415         unsigned int tmp, div, real_div, nb_bits, frame_len;
 416         unsigned int rate = params_rate(params);
 417         int ret;
 418         u32 cgfr, cgfr_mask;
 419         bool odd;
 420
 421         if (!(rate % 11025))
 422                 clk_set_parent(i2s->i2sclk, i2s->x11kclk);
 423         else
 424                 clk_set_parent(i2s->i2sclk, i2s->x8kclk);
 425         i2s_clock_rate = clk_get_rate(i2s->i2sclk);
 426
 427         /*
 428          * mckl = mclk_ratio x ws
 429          *   i2s mode : mclk_ratio = 256
 430          *   dsp mode : mclk_ratio = 128
 431          *
 432          * mclk on
 433          *   i2s mode : div = i2s_clk / (mclk_ratio * ws)
 434          *   dsp mode : div = i2s_clk / (mclk_ratio * ws)
 435          * mclk off
 436          *   i2s mode : div = i2s_clk / (nb_bits x ws)
 437          *   dsp mode : div = i2s_clk / (nb_bits x ws)
 438          */
 439         if (i2s->mclk_rate) {
 440                 tmp = DIV_ROUND_CLOSEST(i2s_clock_rate, i2s->mclk_rate);
 441         } else {
 442                 frame_len = 32;
 443                 if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
 444                     SND_SOC_DAIFMT_DSP_A)
 445                         frame_len = 16;
 446
 447                 /* master clock not enabled */
 448                 ret = regmap_read(i2s->regmap, STM32_I2S_CGFR_REG, &cgfr);
 449                 if (ret < 0)
 450                         return ret;
 451
 452                 nb_bits = frame_len * ((cgfr & I2S_CGFR_CHLEN) + 1);
 453                 tmp = DIV_ROUND_CLOSEST(i2s_clock_rate, (nb_bits * rate));
 454         }
 455
 456         /* Check the parity of the divider */
 457         odd = tmp & 0x1;
 458
 459         /* Compute the div prescaler */
 460         div = tmp >> 1;
 461
 462         cgfr = I2S_CGFR_I2SDIV_SET(div) | (odd << I2S_CGFR_ODD_SHIFT);
 463         cgfr_mask = I2S_CGFR_I2SDIV_MASK | I2S_CGFR_ODD;
 464
 465         real_div = ((2 * div) + odd);
 466         dev_dbg(cpu_dai->dev, "I2S clk: %ld, SCLK: %d\n",
 467                 i2s_clock_rate, rate);
 468         dev_dbg(cpu_dai->dev, "Divider: 2*%d(div)+%d(odd) = %d\n",
 469                 div, odd, real_div);
 470
 471         if (((div == 1) && odd) || (div > I2S_CGFR_I2SDIV_MAX)) {
 472                 dev_err(cpu_dai->dev, "Wrong divider setting\n");
 473                 return -EINVAL;
 474         }
 475
 476         if (!div && !odd)
 477                 dev_warn(cpu_dai->dev, "real divider forced to 1\n");
 478
 479         ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 480                                  cgfr_mask, cgfr);
 481         if (ret < 0)
 482                 return ret;
 483
 484         /* Set bitclock and frameclock to their inactive state */
 485         return regmap_update_bits(i2s->regmap, STM32_I2S_CFG2_REG,
 486                                   I2S_CFG2_AFCNTR, I2S_CFG2_AFCNTR);
 487 }
 488
 489 static int stm32_i2s_configure(struct snd_soc_dai *cpu_dai,
 490                                struct snd_pcm_hw_params *params,
 491                                struct snd_pcm_substream *substream)
 492 {
 493         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 494         int format = params_width(params);
 495         u32 cfgr, cfgr_mask, cfg1;
 496         unsigned int fthlv;
 497         int ret;
 498
 499         if ((params_channels(params) == 1) &&
 500             ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_DSP_A)) {
 501                 dev_err(cpu_dai->dev, "Mono mode supported only by DSP_A\n");
 502                 return -EINVAL;
 503         }
 504
 505         switch (format) {
 506         case 16:
 507                 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_16);
 508                 cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
 509                 break;
 510         case 32:
 511                 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_32) |
 512                                            I2S_CGFR_CHLEN;
 513                 cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
 514                 break;
 515         default:
 516                 dev_err(cpu_dai->dev, "Unexpected format %d", format);
 517                 return -EINVAL;
 518         }
 519
 520         if (STM32_I2S_IS_SLAVE(i2s)) {
 521                 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_SLAVE);
 522
 523                 /* As data length is either 16 or 32 bits, fixch always set */
 524                 cfgr |= I2S_CGFR_FIXCH;
 525                 cfgr_mask |= I2S_CGFR_FIXCH;
 526         } else {
 527                 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_MASTER);
 528         }
 529         cfgr_mask |= I2S_CGFR_I2SCFG_MASK;
 530
 531         ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 532                                  cfgr_mask, cfgr);
 533         if (ret < 0)
 534                 return ret;
 535
 536         fthlv = STM32_I2S_FIFO_SIZE * I2S_FIFO_TH_ONE_QUARTER / 4;
 537         cfg1 = I2S_CFG1_FTHVL_SET(fthlv - 1);
 538
 539         return regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
 540                                   I2S_CFG1_FTHVL_MASK, cfg1);
 541 }
 542
 543 static int stm32_i2s_startup(struct snd_pcm_substream *substream,
 544                              struct snd_soc_dai *cpu_dai)
 545 {
 546         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 547         unsigned long flags;
 548         int ret;
 549
 550         spin_lock_irqsave(&i2s->irq_lock, flags);
 551         i2s->substream = substream;
 552         spin_unlock_irqrestore(&i2s->irq_lock, flags);
 553
 554         ret = clk_prepare_enable(i2s->i2sclk);
 555         if (ret < 0) {
 556                 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
 557                 return ret;
 558         }
 559
 560         return regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
 561                                  I2S_IFCR_MASK, I2S_IFCR_MASK);
 562 }
 563
 564 static int stm32_i2s_hw_params(struct snd_pcm_substream *substream,
 565                                struct snd_pcm_hw_params *params,
 566                                struct snd_soc_dai *cpu_dai)
 567 {
 568         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 569         int ret;
 570
 571         ret = stm32_i2s_configure(cpu_dai, params, substream);
 572         if (ret < 0) {
 573                 dev_err(cpu_dai->dev, "Configuration returned error %d\n", ret);
 574                 return ret;
 575         }
 576
 577         if (STM32_I2S_IS_MASTER(i2s))
 578                 ret = stm32_i2s_configure_clock(cpu_dai, params);
 579
 580         return ret;
 581 }
 582
 583 static int stm32_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 584                              struct snd_soc_dai *cpu_dai)
 585 {
 586         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 587         bool playback_flg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 588         u32 cfg1_mask, ier;
 589         int ret;
 590
 591         switch (cmd) {
 592         case SNDRV_PCM_TRIGGER_START:
 593         case SNDRV_PCM_TRIGGER_RESUME:
 594         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 595                 /* Enable i2s */
 596                 dev_dbg(cpu_dai->dev, "start I2S\n");
 597
 598                 cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
 599                 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
 600                                    cfg1_mask, cfg1_mask);
 601
 602                 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
 603                                          I2S_CR1_SPE, I2S_CR1_SPE);
 604                 if (ret < 0) {
 605                         dev_err(cpu_dai->dev, "Error %d enabling I2S\n", ret);
 606                         return ret;
 607                 }
 608
 609                 ret = regmap_write_bits(i2s->regmap, STM32_I2S_CR1_REG,
 610                                         I2S_CR1_CSTART, I2S_CR1_CSTART);
 611                 if (ret < 0) {
 612                         dev_err(cpu_dai->dev, "Error %d starting I2S\n", ret);
 613                         return ret;
 614                 }
 615
 616                 regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
 617                                   I2S_IFCR_MASK, I2S_IFCR_MASK);
 618
 619                 spin_lock(&i2s->lock_fd);
 620                 i2s->refcount++;
 621                 if (playback_flg) {
 622                         ier = I2S_IER_UDRIE;
 623                 } else {
 624                         ier = I2S_IER_OVRIE;
 625
 626                         if (STM32_I2S_IS_MASTER(i2s) && i2s->refcount == 1)
 627                                 /* dummy write to gate bus clocks */
 628                                 regmap_write(i2s->regmap,
 629                                              STM32_I2S_TXDR_REG, 0);
 630                 }
 631                 spin_unlock(&i2s->lock_fd);
 632
 633                 if (STM32_I2S_IS_SLAVE(i2s))
 634                         ier |= I2S_IER_TIFREIE;
 635
 636                 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, ier, ier);
 637                 break;
 638         case SNDRV_PCM_TRIGGER_STOP:
 639         case SNDRV_PCM_TRIGGER_SUSPEND:
 640         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 641                 if (playback_flg)
 642                         regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
 643                                            I2S_IER_UDRIE,
 644                                            (unsigned int)~I2S_IER_UDRIE);
 645                 else
 646                         regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
 647                                            I2S_IER_OVRIE,
 648                                            (unsigned int)~I2S_IER_OVRIE);
 649
 650                 spin_lock(&i2s->lock_fd);
 651                 i2s->refcount--;
 652                 if (i2s->refcount) {
 653                         spin_unlock(&i2s->lock_fd);
 654                         break;
 655                 }
 656
 657                 dev_dbg(cpu_dai->dev, "stop I2S\n");
 658
 659                 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
 660                                          I2S_CR1_SPE, 0);
 661                 if (ret < 0) {
 662                         dev_err(cpu_dai->dev, "Error %d disabling I2S\n", ret);
 663                         spin_unlock(&i2s->lock_fd);
 664                         return ret;
 665                 }
 666                 spin_unlock(&i2s->lock_fd);
 667
 668                 cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
 669                 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
 670                                    cfg1_mask, 0);
 671                 break;
 672         default:
 673                 return -EINVAL;
 674         }
 675
 676         return 0;
 677 }
 678
 679 static void stm32_i2s_shutdown(struct snd_pcm_substream *substream,
 680                                struct snd_soc_dai *cpu_dai)
 681 {
 682         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 683         unsigned long flags;
 684
 685         regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 686                            I2S_CGFR_MCKOE, (unsigned int)~I2S_CGFR_MCKOE);
 687
 688         clk_disable_unprepare(i2s->i2sclk);
 689
 690         spin_lock_irqsave(&i2s->irq_lock, flags);
 691         i2s->substream = NULL;
 692         spin_unlock_irqrestore(&i2s->irq_lock, flags);
 693 }
 694
 695 static int stm32_i2s_dai_probe(struct snd_soc_dai *cpu_dai)
 696 {
 697         struct stm32_i2s_data *i2s = dev_get_drvdata(cpu_dai->dev);
 698         struct snd_dmaengine_dai_dma_data *dma_data_tx = &i2s->dma_data_tx;
 699         struct snd_dmaengine_dai_dma_data *dma_data_rx = &i2s->dma_data_rx;
 700
 701         /* Buswidth will be set by framework */
 702         dma_data_tx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
 703         dma_data_tx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_TXDR_REG;
 704         dma_data_tx->maxburst = 1;
 705         dma_data_rx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
 706         dma_data_rx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_RXDR_REG;
 707         dma_data_rx->maxburst = 1;
 708
 709         snd_soc_dai_init_dma_data(cpu_dai, dma_data_tx, dma_data_rx);
 710
 711         return 0;
 712 }
 713
 714 static const struct regmap_config stm32_h7_i2s_regmap_conf = {
 715         .reg_bits = 32,
 716         .reg_stride = 4,
 717         .val_bits = 32,
 718         .max_register = STM32_I2S_CGFR_REG,
 719         .readable_reg = stm32_i2s_readable_reg,
 720         .volatile_reg = stm32_i2s_volatile_reg,
 721         .writeable_reg = stm32_i2s_writeable_reg,
 722         .fast_io = true,
 723         .cache_type = REGCACHE_FLAT,
 724 };
 725
 726 static const struct snd_soc_dai_ops stm32_i2s_pcm_dai_ops = {
 727         .set_sysclk     = stm32_i2s_set_sysclk,
 728         .set_fmt        = stm32_i2s_set_dai_fmt,
 729         .startup        = stm32_i2s_startup,
 730         .hw_params      = stm32_i2s_hw_params,
 731         .trigger        = stm32_i2s_trigger,
 732         .shutdown       = stm32_i2s_shutdown,
 733 };
 734
 735 static const struct snd_pcm_hardware stm32_i2s_pcm_hw = {
 736         .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
 737         .buffer_bytes_max = 8 * PAGE_SIZE,
 738         .period_bytes_max = 2048,
 739         .periods_min = 2,
 740         .periods_max = 8,
 741 };
 742
 743 static const struct snd_dmaengine_pcm_config stm32_i2s_pcm_config = {
 744         .pcm_hardware   = &stm32_i2s_pcm_hw,
 745         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
 746         .prealloc_buffer_size = PAGE_SIZE * 8,
 747 };
 748
 749 static const struct snd_soc_component_driver stm32_i2s_component = {
 750         .name = "stm32-i2s",
 751 };
 752
 753 static void stm32_i2s_dai_init(struct snd_soc_pcm_stream *stream,
 754                                char *stream_name)
 755 {
 756         stream->stream_name = stream_name;
 757         stream->channels_min = 1;
 758         stream->channels_max = 2;
 759         stream->rates = SNDRV_PCM_RATE_8000_192000;
 760         stream->formats = SNDRV_PCM_FMTBIT_S16_LE |
 761                                    SNDRV_PCM_FMTBIT_S32_LE;
 762 }
 763
 764 static int stm32_i2s_dais_init(struct platform_device *pdev,
 765                                struct stm32_i2s_data *i2s)
 766 {
 767         struct snd_soc_dai_driver *dai_ptr;
 768
 769         dai_ptr = devm_kzalloc(&pdev->dev, sizeof(struct snd_soc_dai_driver),
 770                                GFP_KERNEL);
 771         if (!dai_ptr)
 772                 return -ENOMEM;
 773
 774         snprintf(i2s->dais_name, STM32_I2S_DAI_NAME_SIZE,
 775                  "%s", dev_name(&pdev->dev));
 776
 777         dai_ptr->probe = stm32_i2s_dai_probe;
 778         dai_ptr->ops = &stm32_i2s_pcm_dai_ops;
 779         dai_ptr->name = i2s->dais_name;
 780         dai_ptr->id = 1;
 781         stm32_i2s_dai_init(&dai_ptr->playback, "playback");
 782         stm32_i2s_dai_init(&dai_ptr->capture, "capture");
 783         i2s->dai_drv = dai_ptr;
 784
 785         return 0;
 786 }
 787
 788 static const struct of_device_id stm32_i2s_ids[] = {
 789         {
 790                 .compatible = "st,stm32h7-i2s",
 791                 .data = &stm32_h7_i2s_regmap_conf
 792         },
 793         {},
 794 };
 795
 796 static int stm32_i2s_parse_dt(struct platform_device *pdev,
 797                               struct stm32_i2s_data *i2s)
 798 {
 799         struct device_node *np = pdev->dev.of_node;
 800         const struct of_device_id *of_id;
 801         struct reset_control *rst;
 802         struct resource *res;
 803         int irq, ret;
 804
 805         if (!np)
 806                 return -ENODEV;
 807
 808         of_id = of_match_device(stm32_i2s_ids, &pdev->dev);
 809         if (of_id)
 810                 i2s->regmap_conf = (const struct regmap_config *)of_id->data;
 811         else
 812                 return -EINVAL;
 813
 814         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 815         i2s->base = devm_ioremap_resource(&pdev->dev, res);
 816         if (IS_ERR(i2s->base))
 817                 return PTR_ERR(i2s->base);
 818
 819         i2s->phys_addr = res->start;
 820
 821         /* Get clocks */
 822         i2s->pclk = devm_clk_get(&pdev->dev, "pclk");
 823         if (IS_ERR(i2s->pclk)) {
 824                 dev_err(&pdev->dev, "Could not get pclk\n");
 825                 return PTR_ERR(i2s->pclk);
 826         }
 827
 828         i2s->i2sclk = devm_clk_get(&pdev->dev, "i2sclk");
 829         if (IS_ERR(i2s->i2sclk)) {
 830                 dev_err(&pdev->dev, "Could not get i2sclk\n");
 831                 return PTR_ERR(i2s->i2sclk);
 832         }
 833
 834         i2s->x8kclk = devm_clk_get(&pdev->dev, "x8k");
 835         if (IS_ERR(i2s->x8kclk)) {
 836                 dev_err(&pdev->dev, "missing x8k parent clock\n");
 837                 return PTR_ERR(i2s->x8kclk);
 838         }
 839
 840         i2s->x11kclk = devm_clk_get(&pdev->dev, "x11k");
 841         if (IS_ERR(i2s->x11kclk)) {
 842                 dev_err(&pdev->dev, "missing x11k parent clock\n");
 843                 return PTR_ERR(i2s->x11kclk);
 844         }
 845
 846         /* Get irqs */
 847         irq = platform_get_irq(pdev, 0);
 848         if (irq < 0) {
 849                 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
 850                 return -ENOENT;
 851         }
 852
 853         ret = devm_request_irq(&pdev->dev, irq, stm32_i2s_isr, IRQF_ONESHOT,
 854                                dev_name(&pdev->dev), i2s);
 855         if (ret) {
 856                 dev_err(&pdev->dev, "irq request returned %d\n", ret);
 857                 return ret;
 858         }
 859
 860         /* Reset */
 861         rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
 862         if (!IS_ERR(rst)) {
 863                 reset_control_assert(rst);
 864                 udelay(2);
 865                 reset_control_deassert(rst);
 866         }
 867
 868         return 0;
 869 }
 870
 871 static int stm32_i2s_probe(struct platform_device *pdev)
 872 {
 873         struct stm32_i2s_data *i2s;
 874         int ret;
 875
 876         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
 877         if (!i2s)
 878                 return -ENOMEM;
 879
 880         ret = stm32_i2s_parse_dt(pdev, i2s);
 881         if (ret)
 882                 return ret;
 883
 884         i2s->pdev = pdev;
 885         i2s->ms_flg = I2S_MS_NOT_SET;
 886         spin_lock_init(&i2s->lock_fd);
 887         spin_lock_init(&i2s->irq_lock);
 888         platform_set_drvdata(pdev, i2s);
 889
 890         ret = stm32_i2s_dais_init(pdev, i2s);
 891         if (ret)
 892                 return ret;
 893
 894         i2s->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "pclk",
 895                                                 i2s->base, i2s->regmap_conf);
 896         if (IS_ERR(i2s->regmap)) {
 897                 dev_err(&pdev->dev, "regmap init failed\n");
 898                 return PTR_ERR(i2s->regmap);
 899         }
 900
 901         ret = devm_snd_soc_register_component(&pdev->dev, &stm32_i2s_component,
 902                                               i2s->dai_drv, 1);
 903         if (ret)
 904                 return ret;
 905
 906         ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
 907                                               &stm32_i2s_pcm_config, 0);
 908         if (ret)
 909                 return ret;
 910
 911         /* Set SPI/I2S in i2s mode */
 912         return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 913                                   I2S_CGFR_I2SMOD, I2S_CGFR_I2SMOD);
 914 }
 915
 916 MODULE_DEVICE_TABLE(of, stm32_i2s_ids);
 917
 918 #ifdef CONFIG_PM_SLEEP
 919 static int stm32_i2s_suspend(struct device *dev)
 920 {
 921         struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
 922
 923         regcache_cache_only(i2s->regmap, true);
 924         regcache_mark_dirty(i2s->regmap);
 925
 926         return 0;
 927 }
 928
 929 static int stm32_i2s_resume(struct device *dev)
 930 {
 931         struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
 932
 933         regcache_cache_only(i2s->regmap, false);
 934         return regcache_sync(i2s->regmap);
 935 }
 936 #endif /* CONFIG_PM_SLEEP */
 937
 938 static const struct dev_pm_ops stm32_i2s_pm_ops = {
 939         SET_SYSTEM_SLEEP_PM_OPS(stm32_i2s_suspend, stm32_i2s_resume)
 940 };
 941
 942 static struct platform_driver stm32_i2s_driver = {
 943         .driver = {
 944                 .name = "st,stm32-i2s",
 945                 .of_match_table = stm32_i2s_ids,
 946                 .pm = &stm32_i2s_pm_ops,
 947         },
 948         .probe = stm32_i2s_probe,
 949 };
 950
 951 module_platform_driver(stm32_i2s_driver);
 952
 953 MODULE_DESCRIPTION("STM32 Soc i2s Interface");
 954 MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
 955 MODULE_ALIAS("platform:stm32-i2s");
 956 MODULE_LICENSE("GPL v2");