1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 // Copyright(c) 2021 Mediatek Inc. All rights reserved.
5 // Author: YC Hung <yc.hung@mediatek.com>
9 * Hardware interface for audio DSP on mt8195
12 #include <linux/delay.h>
13 #include <linux/firmware.h>
15 #include <linux/of_platform.h>
16 #include <linux/of_address.h>
17 #include <linux/of_irq.h>
18 #include <linux/of_platform.h>
19 #include <linux/of_reserved_mem.h>
20 #include <linux/module.h>
22 #include <sound/sof.h>
23 #include <sound/sof/xtensa.h>
24 #include "../../ops.h"
25 #include "../../sof-of-dev.h"
26 #include "../../sof-audio.h"
27 #include "../adsp_helper.h"
29 #include "mt8195-clk.h"
31 static int mt8195_get_mailbox_offset(struct snd_sof_dev *sdev)
36 static int mt8195_get_window_offset(struct snd_sof_dev *sdev, u32 id)
41 static int mt8195_send_msg(struct snd_sof_dev *sdev,
42 struct snd_sof_ipc_msg *msg)
44 struct adsp_priv *priv = sdev->pdata->hw_pdata;
46 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
49 return mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_REQ, MTK_ADSP_IPC_OP_REQ);
52 static void mt8195_get_reply(struct snd_sof_dev *sdev)
54 struct snd_sof_ipc_msg *msg = sdev->msg;
55 struct sof_ipc_reply reply;
59 dev_warn(sdev->dev, "unexpected ipc interrupt\n");
64 sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply));
65 if (reply.error < 0) {
66 memcpy(msg->reply_data, &reply, sizeof(reply));
69 /* reply has correct size? */
70 if (reply.hdr.size != msg->reply_size) {
71 dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n",
72 msg->reply_size, reply.hdr.size);
76 /* read the message */
77 if (msg->reply_size > 0)
78 sof_mailbox_read(sdev, sdev->host_box.offset,
79 msg->reply_data, msg->reply_size);
82 msg->reply_error = ret;
85 static void mt8195_dsp_handle_reply(struct mtk_adsp_ipc *ipc)
87 struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc);
90 spin_lock_irqsave(&priv->sdev->ipc_lock, flags);
91 mt8195_get_reply(priv->sdev);
92 snd_sof_ipc_reply(priv->sdev, 0);
93 spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags);
96 static void mt8195_dsp_handle_request(struct mtk_adsp_ipc *ipc)
98 struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc);
99 u32 p; /* panic code */
102 /* Read the message from the debug box. */
103 sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4,
106 /* Check to see if the message is a panic code 0x0dead*** */
107 if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
108 snd_sof_dsp_panic(priv->sdev, p, true);
110 snd_sof_ipc_msgs_rx(priv->sdev);
112 /* tell DSP cmd is done */
113 ret = mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_RSP, MTK_ADSP_IPC_OP_RSP);
115 dev_err(priv->dev, "request send ipc failed");
119 static struct mtk_adsp_ipc_ops dsp_ops = {
120 .handle_reply = mt8195_dsp_handle_reply,
121 .handle_request = mt8195_dsp_handle_request,
124 static int platform_parse_resource(struct platform_device *pdev, void *data)
126 struct resource *mmio;
128 struct device_node *mem_region;
129 struct device *dev = &pdev->dev;
130 struct mtk_adsp_chip_info *adsp = data;
133 mem_region = of_parse_phandle(dev->of_node, "memory-region", 0);
135 dev_err(dev, "no dma memory-region phandle\n");
139 ret = of_address_to_resource(mem_region, 0, &res);
140 of_node_put(mem_region);
142 dev_err(dev, "of_address_to_resource dma failed\n");
146 dev_dbg(dev, "DMA %pR\n", &res);
148 ret = of_reserved_mem_device_init(dev);
150 dev_err(dev, "of_reserved_mem_device_init failed\n");
154 mem_region = of_parse_phandle(dev->of_node, "memory-region", 1);
156 dev_err(dev, "no memory-region sysmem phandle\n");
160 ret = of_address_to_resource(mem_region, 0, &res);
161 of_node_put(mem_region);
163 dev_err(dev, "of_address_to_resource sysmem failed\n");
167 adsp->pa_dram = (phys_addr_t)res.start;
168 adsp->dramsize = resource_size(&res);
169 if (adsp->pa_dram & DRAM_REMAP_MASK) {
170 dev_err(dev, "adsp memory(%#x) is not 4K-aligned\n",
175 if (adsp->dramsize < TOTAL_SIZE_SHARED_DRAM_FROM_TAIL) {
176 dev_err(dev, "adsp memory(%#x) is not enough for share\n",
181 dev_dbg(dev, "dram pbase=%pa, dramsize=%#x\n",
182 &adsp->pa_dram, adsp->dramsize);
185 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
187 dev_err(dev, "no ADSP-CFG register resource\n");
190 /* remap for DSP register accessing */
191 adsp->va_cfgreg = devm_ioremap_resource(dev, mmio);
192 if (IS_ERR(adsp->va_cfgreg))
193 return PTR_ERR(adsp->va_cfgreg);
195 adsp->pa_cfgreg = (phys_addr_t)mmio->start;
196 adsp->cfgregsize = resource_size(mmio);
198 dev_dbg(dev, "cfgreg-vbase=%p, cfgregsize=%#x\n",
199 adsp->va_cfgreg, adsp->cfgregsize);
202 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
204 dev_err(dev, "no SRAM resource\n");
208 adsp->pa_sram = (phys_addr_t)mmio->start;
209 adsp->sramsize = resource_size(mmio);
210 if (adsp->sramsize < TOTAL_SIZE_SHARED_SRAM_FROM_TAIL) {
211 dev_err(dev, "adsp SRAM(%#x) is not enough for share\n",
216 dev_dbg(dev, "sram pbase=%pa,%#x\n", &adsp->pa_sram, adsp->sramsize);
221 static int adsp_sram_power_on(struct device *dev, bool on)
223 void __iomem *va_dspsysreg;
226 va_dspsysreg = ioremap(ADSP_SRAM_POOL_CON, 0x4);
228 dev_err(dev, "failed to ioremap sram pool base %#x\n",
233 srampool_con = readl(va_dspsysreg);
235 writel(srampool_con & ~DSP_SRAM_POOL_PD_MASK, va_dspsysreg);
237 writel(srampool_con | DSP_SRAM_POOL_PD_MASK, va_dspsysreg);
239 iounmap(va_dspsysreg);
243 /* Init the basic DSP DRAM address */
244 static int adsp_memory_remap_init(struct device *dev, struct mtk_adsp_chip_info *adsp)
246 void __iomem *vaddr_emi_map;
252 vaddr_emi_map = devm_ioremap(dev, DSP_EMI_MAP_ADDR, 0x4);
253 if (!vaddr_emi_map) {
254 dev_err(dev, "failed to ioremap emi map base %#x\n",
259 offset = adsp->pa_dram - DRAM_PHYS_BASE_FROM_DSP_VIEW;
260 adsp->dram_offset = offset;
261 offset >>= DRAM_REMAP_SHIFT;
262 dev_dbg(dev, "adsp->pa_dram %pa, offset %#x\n", &adsp->pa_dram, offset);
263 writel(offset, vaddr_emi_map);
264 if (offset != readl(vaddr_emi_map)) {
265 dev_err(dev, "write emi map fail : %#x\n", readl(vaddr_emi_map));
272 static int adsp_shared_base_ioremap(struct platform_device *pdev, void *data)
274 struct device *dev = &pdev->dev;
275 struct mtk_adsp_chip_info *adsp = data;
278 /* remap shared-dram base to be non-cachable */
279 shared_size = TOTAL_SIZE_SHARED_DRAM_FROM_TAIL;
280 adsp->pa_shared_dram = adsp->pa_dram + adsp->dramsize - shared_size;
282 adsp->shared_dram = adsp->va_dram + DSP_DRAM_SIZE - shared_size;
284 adsp->shared_dram = devm_ioremap(dev, adsp->pa_shared_dram,
286 if (!adsp->shared_dram) {
287 dev_err(dev, "ioremap failed for shared DRAM\n");
291 dev_dbg(dev, "shared-dram vbase=%p, phy addr :%pa, size=%#x\n",
292 adsp->shared_dram, &adsp->pa_shared_dram, shared_size);
297 static int mt8195_run(struct snd_sof_dev *sdev)
299 u32 adsp_bootup_addr;
301 adsp_bootup_addr = SRAM_PHYS_BASE_FROM_DSP_VIEW;
302 dev_dbg(sdev->dev, "HIFIxDSP boot from base : 0x%08X\n", adsp_bootup_addr);
303 sof_hifixdsp_boot_sequence(sdev, adsp_bootup_addr);
308 static int mt8195_dsp_probe(struct snd_sof_dev *sdev)
310 struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev);
311 struct adsp_priv *priv;
314 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
318 sdev->pdata->hw_pdata = priv;
319 priv->dev = sdev->dev;
322 priv->adsp = devm_kzalloc(&pdev->dev, sizeof(struct mtk_adsp_chip_info), GFP_KERNEL);
326 ret = platform_parse_resource(pdev, priv->adsp);
330 ret = mt8195_adsp_init_clock(sdev);
332 dev_err(sdev->dev, "mt8195_adsp_init_clock failed\n");
336 ret = adsp_clock_on(sdev);
338 dev_err(sdev->dev, "adsp_clock_on fail!\n");
342 ret = adsp_sram_power_on(sdev->dev, true);
344 dev_err(sdev->dev, "adsp_sram_power_on fail!\n");
345 goto exit_clk_disable;
348 ret = adsp_memory_remap_init(&pdev->dev, priv->adsp);
350 dev_err(sdev->dev, "adsp_memory_remap_init fail!\n");
351 goto err_adsp_sram_power_off;
354 sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev,
356 priv->adsp->sramsize);
357 if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) {
358 dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",
359 &priv->adsp->pa_sram, priv->adsp->sramsize);
361 goto err_adsp_sram_power_off;
364 sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev,
366 priv->adsp->dramsize);
367 if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) {
368 dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",
369 &priv->adsp->pa_dram, priv->adsp->dramsize);
371 goto err_adsp_sram_power_off;
373 priv->adsp->va_dram = sdev->bar[SOF_FW_BLK_TYPE_SRAM];
375 ret = adsp_shared_base_ioremap(pdev, priv->adsp);
377 dev_err(sdev->dev, "adsp_shared_base_ioremap fail!\n");
378 goto err_adsp_sram_power_off;
381 sdev->bar[DSP_REG_BAR] = priv->adsp->va_cfgreg;
383 sdev->mmio_bar = SOF_FW_BLK_TYPE_SRAM;
384 sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;
386 /* set default mailbox offset for FW ready message */
387 sdev->dsp_box.offset = mt8195_get_mailbox_offset(sdev);
389 priv->ipc_dev = platform_device_register_data(&pdev->dev, "mtk-adsp-ipc",
391 pdev, sizeof(*pdev));
392 if (IS_ERR(priv->ipc_dev)) {
393 ret = PTR_ERR(priv->ipc_dev);
394 dev_err(sdev->dev, "failed to register mtk-adsp-ipc device\n");
395 goto err_adsp_sram_power_off;
398 priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev);
399 if (!priv->dsp_ipc) {
401 dev_err(sdev->dev, "failed to get drvdata\n");
402 goto exit_pdev_unregister;
405 mtk_adsp_ipc_set_data(priv->dsp_ipc, priv);
406 priv->dsp_ipc->ops = &dsp_ops;
410 exit_pdev_unregister:
411 platform_device_unregister(priv->ipc_dev);
412 err_adsp_sram_power_off:
413 adsp_sram_power_on(&pdev->dev, false);
415 adsp_clock_off(sdev);
420 static int mt8195_dsp_shutdown(struct snd_sof_dev *sdev)
422 return snd_sof_suspend(sdev->dev);
425 static int mt8195_dsp_remove(struct snd_sof_dev *sdev)
427 struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev);
428 struct adsp_priv *priv = sdev->pdata->hw_pdata;
430 platform_device_unregister(priv->ipc_dev);
431 adsp_sram_power_on(&pdev->dev, false);
432 adsp_clock_off(sdev);
437 static int mt8195_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
439 struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev);
442 /* stall and reset dsp */
443 sof_hifixdsp_shutdown(sdev);
445 /* power down adsp sram */
446 ret = adsp_sram_power_on(&pdev->dev, false);
448 dev_err(sdev->dev, "adsp_sram_power_off fail!\n");
452 /* turn off adsp clock */
453 return adsp_clock_off(sdev);
456 static int mt8195_dsp_resume(struct snd_sof_dev *sdev)
460 /* turn on adsp clock */
461 ret = adsp_clock_on(sdev);
463 dev_err(sdev->dev, "adsp_clock_on fail!\n");
467 /* power on adsp sram */
468 ret = adsp_sram_power_on(sdev->dev, true);
470 dev_err(sdev->dev, "adsp_sram_power_on fail!\n");
475 /* on mt8195 there is 1 to 1 match between type and BAR idx */
476 static int mt8195_get_bar_index(struct snd_sof_dev *sdev, u32 type)
481 static int mt8195_ipc_msg_data(struct snd_sof_dev *sdev,
482 struct snd_pcm_substream *substream,
485 sof_mailbox_read(sdev, sdev->dsp_box.offset, p, sz);
489 static struct snd_soc_dai_driver mt8195_dai[] = {
521 static struct snd_sof_dsp_ops sof_mt8195_ops = {
522 /* probe and remove */
523 .probe = mt8195_dsp_probe,
524 .remove = mt8195_dsp_remove,
525 .shutdown = mt8195_dsp_shutdown,
531 .block_read = sof_block_read,
532 .block_write = sof_block_write,
535 .write = sof_io_write,
537 .write64 = sof_io_write64,
538 .read64 = sof_io_read64,
541 .send_msg = mt8195_send_msg,
542 .get_mailbox_offset = mt8195_get_mailbox_offset,
543 .get_window_offset = mt8195_get_window_offset,
544 .ipc_msg_data = mt8195_ipc_msg_data,
545 .set_stream_data_offset = sof_set_stream_data_offset,
548 .get_bar_index = mt8195_get_bar_index,
550 /* firmware loading */
551 .load_firmware = snd_sof_load_firmware_memcpy,
554 .dsp_arch_ops = &sof_xtensa_arch_ops,
558 .num_drv = ARRAY_SIZE(mt8195_dai),
561 .suspend = mt8195_dsp_suspend,
562 .resume = mt8195_dsp_resume,
564 /* ALSA HW info flags */
565 .hw_info = SNDRV_PCM_INFO_MMAP |
566 SNDRV_PCM_INFO_MMAP_VALID |
567 SNDRV_PCM_INFO_INTERLEAVED |
568 SNDRV_PCM_INFO_PAUSE |
569 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
572 static const struct sof_dev_desc sof_of_mt8195_desc = {
573 .ipc_supported_mask = BIT(SOF_IPC),
574 .ipc_default = SOF_IPC,
576 [SOF_IPC] = "mediatek/sof",
578 .default_tplg_path = {
579 [SOF_IPC] = "mediatek/sof-tplg",
581 .default_fw_filename = {
582 [SOF_IPC] = "sof-mt8195.ri",
584 .nocodec_tplg_filename = "sof-mt8195-nocodec.tplg",
585 .ops = &sof_mt8195_ops,
589 static const struct of_device_id sof_of_mt8195_ids[] = {
590 { .compatible = "mediatek,mt8195-dsp", .data = &sof_of_mt8195_desc},
593 MODULE_DEVICE_TABLE(of, sof_of_mt8195_ids);
595 /* DT driver definition */
596 static struct platform_driver snd_sof_of_mt8195_driver = {
597 .probe = sof_of_probe,
598 .remove = sof_of_remove,
599 .shutdown = sof_of_shutdown,
601 .name = "sof-audio-of-mt8195",
603 .of_match_table = sof_of_mt8195_ids,
606 module_platform_driver(snd_sof_of_mt8195_driver);
608 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
609 MODULE_LICENSE("Dual BSD/GPL");