1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 // Copyright(c) 2022 Mediatek Inc. All rights reserved.
5 // Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
6 // Tinghan Shen <tinghan.shen@mediatek.com>
9 * Hardware interface for audio DSP on mt8186
12 #include <linux/delay.h>
13 #include <linux/firmware.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/of_platform.h>
18 #include <linux/of_reserved_mem.h>
19 #include <linux/module.h>
21 #include <sound/sof.h>
22 #include <sound/sof/xtensa.h>
23 #include "../../ops.h"
24 #include "../../sof-of-dev.h"
25 #include "../../sof-audio.h"
26 #include "../adsp_helper.h"
27 #include "../mtk-adsp-common.h"
29 #include "mt8186-clk.h"
31 static int mt8186_get_mailbox_offset(struct snd_sof_dev *sdev)
36 static int mt8186_get_window_offset(struct snd_sof_dev *sdev, u32 id)
41 static int mt8186_send_msg(struct snd_sof_dev *sdev,
42 struct snd_sof_ipc_msg *msg)
44 struct adsp_priv *priv = sdev->pdata->hw_pdata;
46 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
49 return mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_REQ, MTK_ADSP_IPC_OP_REQ);
52 static void mt8186_dsp_handle_reply(struct mtk_adsp_ipc *ipc)
54 struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc);
57 spin_lock_irqsave(&priv->sdev->ipc_lock, flags);
58 snd_sof_ipc_process_reply(priv->sdev, 0);
59 spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags);
62 static void mt8186_dsp_handle_request(struct mtk_adsp_ipc *ipc)
64 struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc);
65 u32 p; /* panic code */
68 /* Read the message from the debug box. */
69 sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4,
72 /* Check to see if the message is a panic code 0x0dead*** */
73 if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
74 snd_sof_dsp_panic(priv->sdev, p, true);
76 snd_sof_ipc_msgs_rx(priv->sdev);
78 /* tell DSP cmd is done */
79 ret = mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_RSP, MTK_ADSP_IPC_OP_RSP);
81 dev_err(priv->dev, "request send ipc failed");
85 static struct mtk_adsp_ipc_ops dsp_ops = {
86 .handle_reply = mt8186_dsp_handle_reply,
87 .handle_request = mt8186_dsp_handle_request,
90 static int platform_parse_resource(struct platform_device *pdev, void *data)
92 struct resource *mmio;
94 struct device_node *mem_region;
95 struct device *dev = &pdev->dev;
96 struct mtk_adsp_chip_info *adsp = data;
99 mem_region = of_parse_phandle(dev->of_node, "memory-region", 0);
101 dev_err(dev, "no dma memory-region phandle\n");
105 ret = of_address_to_resource(mem_region, 0, &res);
106 of_node_put(mem_region);
108 dev_err(dev, "of_address_to_resource dma failed\n");
112 dev_dbg(dev, "DMA %pR\n", &res);
114 adsp->pa_shared_dram = (phys_addr_t)res.start;
115 adsp->shared_size = resource_size(&res);
116 if (adsp->pa_shared_dram & DRAM_REMAP_MASK) {
117 dev_err(dev, "adsp shared dma memory(%#x) is not 4K-aligned\n",
118 (u32)adsp->pa_shared_dram);
122 ret = of_reserved_mem_device_init(dev);
124 dev_err(dev, "of_reserved_mem_device_init failed\n");
128 mem_region = of_parse_phandle(dev->of_node, "memory-region", 1);
130 dev_err(dev, "no memory-region sysmem phandle\n");
134 ret = of_address_to_resource(mem_region, 0, &res);
135 of_node_put(mem_region);
137 dev_err(dev, "of_address_to_resource sysmem failed\n");
141 adsp->pa_dram = (phys_addr_t)res.start;
142 if (adsp->pa_dram & DRAM_REMAP_MASK) {
143 dev_err(dev, "adsp memory(%#x) is not 4K-aligned\n",
148 adsp->dramsize = resource_size(&res);
149 if (adsp->dramsize < TOTAL_SIZE_SHARED_DRAM_FROM_TAIL) {
150 dev_err(dev, "adsp memory(%#x) is not enough for share\n",
155 dev_dbg(dev, "dram pbase=%pa size=%#x\n", &adsp->pa_dram, adsp->dramsize);
157 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
159 dev_err(dev, "no ADSP-CFG register resource\n");
163 adsp->va_cfgreg = devm_ioremap_resource(dev, mmio);
164 if (IS_ERR(adsp->va_cfgreg))
165 return PTR_ERR(adsp->va_cfgreg);
167 adsp->pa_cfgreg = (phys_addr_t)mmio->start;
168 adsp->cfgregsize = resource_size(mmio);
170 dev_dbg(dev, "cfgreg pbase=%pa size=%#x\n", &adsp->pa_cfgreg, adsp->cfgregsize);
172 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
174 dev_err(dev, "no SRAM resource\n");
178 adsp->pa_sram = (phys_addr_t)mmio->start;
179 adsp->sramsize = resource_size(mmio);
181 dev_dbg(dev, "sram pbase=%pa size=%#x\n", &adsp->pa_sram, adsp->sramsize);
183 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sec");
185 dev_err(dev, "no SEC register resource\n");
189 adsp->va_secreg = devm_ioremap_resource(dev, mmio);
190 if (IS_ERR(adsp->va_secreg))
191 return PTR_ERR(adsp->va_secreg);
193 adsp->pa_secreg = (phys_addr_t)mmio->start;
194 adsp->secregsize = resource_size(mmio);
196 dev_dbg(dev, "secreg pbase=%pa size=%#x\n", &adsp->pa_secreg, adsp->secregsize);
198 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bus");
200 dev_err(dev, "no BUS register resource\n");
204 adsp->va_busreg = devm_ioremap_resource(dev, mmio);
205 if (IS_ERR(adsp->va_busreg))
206 return PTR_ERR(adsp->va_busreg);
208 adsp->pa_busreg = (phys_addr_t)mmio->start;
209 adsp->busregsize = resource_size(mmio);
211 dev_dbg(dev, "busreg pbase=%pa size=%#x\n", &adsp->pa_busreg, adsp->busregsize);
216 static void adsp_sram_power_on(struct snd_sof_dev *sdev)
218 snd_sof_dsp_update_bits(sdev, DSP_BUSREG_BAR, ADSP_SRAM_POOL_CON,
219 DSP_SRAM_POOL_PD_MASK, 0);
222 static void adsp_sram_power_off(struct snd_sof_dev *sdev)
224 snd_sof_dsp_update_bits(sdev, DSP_BUSREG_BAR, ADSP_SRAM_POOL_CON,
225 DSP_SRAM_POOL_PD_MASK, DSP_SRAM_POOL_PD_MASK);
228 /* Init the basic DSP DRAM address */
229 static int adsp_memory_remap_init(struct snd_sof_dev *sdev, struct mtk_adsp_chip_info *adsp)
233 offset = adsp->pa_dram - DRAM_PHYS_BASE_FROM_DSP_VIEW;
234 adsp->dram_offset = offset;
235 offset >>= DRAM_REMAP_SHIFT;
237 dev_dbg(sdev->dev, "adsp->pa_dram %pa, offset %#x\n", &adsp->pa_dram, offset);
239 snd_sof_dsp_write(sdev, DSP_BUSREG_BAR, DSP_C0_EMI_MAP_ADDR, offset);
240 snd_sof_dsp_write(sdev, DSP_BUSREG_BAR, DSP_C0_DMAEMI_MAP_ADDR, offset);
242 if (offset != snd_sof_dsp_read(sdev, DSP_BUSREG_BAR, DSP_C0_EMI_MAP_ADDR) ||
243 offset != snd_sof_dsp_read(sdev, DSP_BUSREG_BAR, DSP_C0_DMAEMI_MAP_ADDR)) {
244 dev_err(sdev->dev, "emi remap fail\n");
251 static int adsp_shared_base_ioremap(struct platform_device *pdev, void *data)
253 struct device *dev = &pdev->dev;
254 struct mtk_adsp_chip_info *adsp = data;
256 /* remap shared-dram base to be non-cachable */
257 adsp->shared_dram = devm_ioremap(dev, adsp->pa_shared_dram,
259 if (!adsp->shared_dram) {
260 dev_err(dev, "failed to ioremap base %pa size %#x\n",
261 adsp->shared_dram, adsp->shared_size);
265 dev_dbg(dev, "shared-dram vbase=%p, phy addr :%pa, size=%#x\n",
266 adsp->shared_dram, &adsp->pa_shared_dram, adsp->shared_size);
271 static int mt8186_run(struct snd_sof_dev *sdev)
273 u32 adsp_bootup_addr;
275 adsp_bootup_addr = SRAM_PHYS_BASE_FROM_DSP_VIEW;
276 dev_dbg(sdev->dev, "HIFIxDSP boot from base : 0x%08X\n", adsp_bootup_addr);
277 mt8186_sof_hifixdsp_boot_sequence(sdev, adsp_bootup_addr);
282 static int mt8186_dsp_probe(struct snd_sof_dev *sdev)
284 struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev);
285 struct adsp_priv *priv;
288 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
292 sdev->pdata->hw_pdata = priv;
293 priv->dev = sdev->dev;
296 priv->adsp = devm_kzalloc(&pdev->dev, sizeof(struct mtk_adsp_chip_info), GFP_KERNEL);
300 ret = platform_parse_resource(pdev, priv->adsp);
304 sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev,
306 priv->adsp->sramsize);
307 if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) {
308 dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",
309 &priv->adsp->pa_sram, priv->adsp->sramsize);
313 priv->adsp->va_sram = sdev->bar[SOF_FW_BLK_TYPE_IRAM];
315 sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap(sdev->dev,
317 priv->adsp->dramsize);
319 if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) {
320 dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",
321 &priv->adsp->pa_dram, priv->adsp->dramsize);
325 priv->adsp->va_dram = sdev->bar[SOF_FW_BLK_TYPE_SRAM];
327 ret = adsp_shared_base_ioremap(pdev, priv->adsp);
329 dev_err(sdev->dev, "adsp_shared_base_ioremap fail!\n");
333 sdev->bar[DSP_REG_BAR] = priv->adsp->va_cfgreg;
334 sdev->bar[DSP_SECREG_BAR] = priv->adsp->va_secreg;
335 sdev->bar[DSP_BUSREG_BAR] = priv->adsp->va_busreg;
337 sdev->mmio_bar = SOF_FW_BLK_TYPE_SRAM;
338 sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;
340 /* set default mailbox offset for FW ready message */
341 sdev->dsp_box.offset = mt8186_get_mailbox_offset(sdev);
343 ret = adsp_memory_remap_init(sdev, priv->adsp);
345 dev_err(sdev->dev, "adsp_memory_remap_init fail!\n");
349 /* enable adsp clock before touching registers */
350 ret = mt8186_adsp_init_clock(sdev);
352 dev_err(sdev->dev, "mt8186_adsp_init_clock failed\n");
356 ret = mt8186_adsp_clock_on(sdev);
358 dev_err(sdev->dev, "mt8186_adsp_clock_on fail!\n");
362 adsp_sram_power_on(sdev);
364 priv->ipc_dev = platform_device_register_data(&pdev->dev, "mtk-adsp-ipc",
366 pdev, sizeof(*pdev));
367 if (IS_ERR(priv->ipc_dev)) {
368 ret = PTR_ERR(priv->ipc_dev);
369 dev_err(sdev->dev, "failed to create mtk-adsp-ipc device\n");
373 priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev);
374 if (!priv->dsp_ipc) {
376 dev_err(sdev->dev, "failed to get drvdata\n");
377 goto exit_pdev_unregister;
380 mtk_adsp_ipc_set_data(priv->dsp_ipc, priv);
381 priv->dsp_ipc->ops = &dsp_ops;
385 exit_pdev_unregister:
386 platform_device_unregister(priv->ipc_dev);
388 adsp_sram_power_off(sdev);
389 mt8186_adsp_clock_off(sdev);
394 static void mt8186_dsp_remove(struct snd_sof_dev *sdev)
396 struct adsp_priv *priv = sdev->pdata->hw_pdata;
398 platform_device_unregister(priv->ipc_dev);
399 mt8186_sof_hifixdsp_shutdown(sdev);
400 adsp_sram_power_off(sdev);
401 mt8186_adsp_clock_off(sdev);
404 static int mt8186_dsp_shutdown(struct snd_sof_dev *sdev)
406 return snd_sof_suspend(sdev->dev);
409 static int mt8186_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
411 mt8186_sof_hifixdsp_shutdown(sdev);
412 adsp_sram_power_off(sdev);
413 mt8186_adsp_clock_off(sdev);
418 static int mt8186_dsp_resume(struct snd_sof_dev *sdev)
422 ret = mt8186_adsp_clock_on(sdev);
424 dev_err(sdev->dev, "mt8186_adsp_clock_on fail!\n");
428 adsp_sram_power_on(sdev);
433 /* on mt8186 there is 1 to 1 match between type and BAR idx */
434 static int mt8186_get_bar_index(struct snd_sof_dev *sdev, u32 type)
439 static int mt8186_pcm_hw_params(struct snd_sof_dev *sdev,
440 struct snd_pcm_substream *substream,
441 struct snd_pcm_hw_params *params,
442 struct snd_sof_platform_stream_params *platform_params)
444 platform_params->cont_update_posn = 1;
449 static snd_pcm_uframes_t mt8186_pcm_pointer(struct snd_sof_dev *sdev,
450 struct snd_pcm_substream *substream)
453 snd_pcm_uframes_t pos;
454 struct snd_sof_pcm *spcm;
455 struct sof_ipc_stream_posn posn;
456 struct snd_sof_pcm_stream *stream;
457 struct snd_soc_component *scomp = sdev->component;
458 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
460 spcm = snd_sof_find_spcm_dai(scomp, rtd);
462 dev_warn_ratelimited(sdev->dev, "warn: can't find PCM with DAI ID %d\n",
467 stream = &spcm->stream[substream->stream];
468 ret = snd_sof_ipc_msg_data(sdev, stream, &posn, sizeof(posn));
470 dev_warn(sdev->dev, "failed to read stream position: %d\n", ret);
474 memcpy(&stream->posn, &posn, sizeof(posn));
475 pos = spcm->stream[substream->stream].posn.host_posn;
476 pos = bytes_to_frames(substream->runtime, pos);
481 static void mt8186_adsp_dump(struct snd_sof_dev *sdev, u32 flags)
483 u32 dbg_pc, dbg_data, dbg_inst, dbg_ls0stat, dbg_status, faultinfo;
485 /* dump debug registers */
486 dbg_pc = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGPC);
487 dbg_data = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGDATA);
488 dbg_inst = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGINST);
489 dbg_ls0stat = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGLS0STAT);
490 dbg_status = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGSTATUS);
491 faultinfo = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PFAULTINFO);
493 dev_info(sdev->dev, "adsp dump : pc %#x, data %#x, dbg_inst %#x,",
494 dbg_pc, dbg_data, dbg_inst);
495 dev_info(sdev->dev, "ls0stat %#x, status %#x, faultinfo %#x",
496 dbg_ls0stat, dbg_status, faultinfo);
498 mtk_adsp_dump(sdev, flags);
501 static struct snd_soc_dai_driver mt8186_dai[] = {
533 static struct snd_sof_dsp_ops sof_mt8186_ops = {
534 /* probe and remove */
535 .probe = mt8186_dsp_probe,
536 .remove = mt8186_dsp_remove,
537 .shutdown = mt8186_dsp_shutdown,
543 .block_read = sof_block_read,
544 .block_write = sof_block_write,
547 .mailbox_read = sof_mailbox_read,
548 .mailbox_write = sof_mailbox_write,
551 .write = sof_io_write,
553 .write64 = sof_io_write64,
554 .read64 = sof_io_read64,
557 .send_msg = mt8186_send_msg,
558 .get_mailbox_offset = mt8186_get_mailbox_offset,
559 .get_window_offset = mt8186_get_window_offset,
560 .ipc_msg_data = sof_ipc_msg_data,
561 .set_stream_data_offset = sof_set_stream_data_offset,
564 .get_bar_index = mt8186_get_bar_index,
566 /* stream callbacks */
567 .pcm_open = sof_stream_pcm_open,
568 .pcm_hw_params = mt8186_pcm_hw_params,
569 .pcm_pointer = mt8186_pcm_pointer,
570 .pcm_close = sof_stream_pcm_close,
572 /* firmware loading */
573 .load_firmware = snd_sof_load_firmware_memcpy,
576 .dsp_arch_ops = &sof_xtensa_arch_ops,
580 .num_drv = ARRAY_SIZE(mt8186_dai),
582 /* Debug information */
583 .dbg_dump = mt8186_adsp_dump,
584 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
587 .suspend = mt8186_dsp_suspend,
588 .resume = mt8186_dsp_resume,
590 /* ALSA HW info flags */
591 .hw_info = SNDRV_PCM_INFO_MMAP |
592 SNDRV_PCM_INFO_MMAP_VALID |
593 SNDRV_PCM_INFO_INTERLEAVED |
594 SNDRV_PCM_INFO_PAUSE |
595 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
598 static struct snd_sof_of_mach sof_mt8186_machs[] = {
600 .compatible = "google,steelix",
601 .sof_tplg_filename = "sof-mt8186-google-steelix.tplg"
603 .compatible = "mediatek,mt8186",
604 .sof_tplg_filename = "sof-mt8186.tplg",
609 static const struct sof_dev_desc sof_of_mt8186_desc = {
610 .of_machines = sof_mt8186_machs,
611 .ipc_supported_mask = BIT(SOF_IPC_TYPE_3),
612 .ipc_default = SOF_IPC_TYPE_3,
614 [SOF_IPC_TYPE_3] = "mediatek/sof",
616 .default_tplg_path = {
617 [SOF_IPC_TYPE_3] = "mediatek/sof-tplg",
619 .default_fw_filename = {
620 [SOF_IPC_TYPE_3] = "sof-mt8186.ri",
622 .nocodec_tplg_filename = "sof-mt8186-nocodec.tplg",
623 .ops = &sof_mt8186_ops,
627 * DL2, DL3, UL4, UL5 are registered as SOF FE, so creating the corresponding
628 * SOF BE to complete the pipeline.
630 static struct snd_soc_dai_driver mt8188_dai[] = {
662 static struct snd_sof_dsp_ops sof_mt8188_ops;
664 static int sof_mt8188_ops_init(struct snd_sof_dev *sdev)
666 /* common defaults */
667 memcpy(&sof_mt8188_ops, &sof_mt8186_ops, sizeof(sof_mt8188_ops));
669 sof_mt8188_ops.drv = mt8188_dai;
670 sof_mt8188_ops.num_drv = ARRAY_SIZE(mt8188_dai);
675 static struct snd_sof_of_mach sof_mt8188_machs[] = {
677 .compatible = "mediatek,mt8188",
678 .sof_tplg_filename = "sof-mt8188.tplg",
683 static const struct sof_dev_desc sof_of_mt8188_desc = {
684 .of_machines = sof_mt8188_machs,
685 .ipc_supported_mask = BIT(SOF_IPC_TYPE_3),
686 .ipc_default = SOF_IPC_TYPE_3,
688 [SOF_IPC_TYPE_3] = "mediatek/sof",
690 .default_tplg_path = {
691 [SOF_IPC_TYPE_3] = "mediatek/sof-tplg",
693 .default_fw_filename = {
694 [SOF_IPC_TYPE_3] = "sof-mt8188.ri",
696 .nocodec_tplg_filename = "sof-mt8188-nocodec.tplg",
697 .ops = &sof_mt8188_ops,
698 .ops_init = sof_mt8188_ops_init,
701 static const struct of_device_id sof_of_mt8186_ids[] = {
702 { .compatible = "mediatek,mt8186-dsp", .data = &sof_of_mt8186_desc},
703 { .compatible = "mediatek,mt8188-dsp", .data = &sof_of_mt8188_desc},
706 MODULE_DEVICE_TABLE(of, sof_of_mt8186_ids);
708 /* DT driver definition */
709 static struct platform_driver snd_sof_of_mt8186_driver = {
710 .probe = sof_of_probe,
711 .remove_new = sof_of_remove,
712 .shutdown = sof_of_shutdown,
714 .name = "sof-audio-of-mt8186",
716 .of_match_table = sof_of_mt8186_ids,
719 module_platform_driver(snd_sof_of_mt8186_driver);
721 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
722 MODULE_IMPORT_NS(SND_SOC_SOF_MTK_COMMON);
723 MODULE_LICENSE("Dual BSD/GPL");