1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 // Copyright(c) 2020 Intel Corporation. All rights reserved.
5 // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
9 * Hardware interface for audio DSP on Tigerlake.
15 #include "../sof-audio.h"
17 static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = {
18 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
19 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
20 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
24 const struct snd_sof_dsp_ops sof_tgl_ops = {
25 /* probe and remove */
26 .probe = hda_dsp_probe,
27 .remove = hda_dsp_remove,
30 .write = sof_io_write,
32 .write64 = sof_io_write64,
33 .read64 = sof_io_read64,
36 .block_read = sof_block_read,
37 .block_write = sof_block_write,
40 .irq_thread = cnl_ipc_irq_thread,
43 .send_msg = cnl_ipc_send_msg,
44 .fw_ready = sof_fw_ready,
45 .get_mailbox_offset = hda_dsp_ipc_get_mailbox_offset,
46 .get_window_offset = hda_dsp_ipc_get_window_offset,
48 .ipc_msg_data = hda_ipc_msg_data,
49 .ipc_pcm_params = hda_ipc_pcm_params,
52 .machine_select = hda_machine_select,
53 .machine_register = sof_machine_register,
54 .machine_unregister = sof_machine_unregister,
55 .set_mach_params = hda_set_mach_params,
58 .debug_map = tgl_dsp_debugfs,
59 .debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs),
60 .dbg_dump = hda_dsp_dump,
61 .ipc_dump = cnl_ipc_dump,
63 /* stream callbacks */
64 .pcm_open = hda_dsp_pcm_open,
65 .pcm_close = hda_dsp_pcm_close,
66 .pcm_hw_params = hda_dsp_pcm_hw_params,
67 .pcm_hw_free = hda_dsp_stream_hw_free,
68 .pcm_trigger = hda_dsp_pcm_trigger,
69 .pcm_pointer = hda_dsp_pcm_pointer,
71 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
73 .probe_assign = hda_probe_compr_assign,
74 .probe_free = hda_probe_compr_free,
75 .probe_set_params = hda_probe_compr_set_params,
76 .probe_trigger = hda_probe_compr_trigger,
77 .probe_pointer = hda_probe_compr_pointer,
80 /* firmware loading */
81 .load_firmware = snd_sof_load_firmware_raw,
84 .pre_fw_run = hda_dsp_pre_fw_run,
85 .post_fw_run = hda_dsp_post_fw_run,
87 /* dsp core power up/down */
88 .core_power_up = hda_dsp_enable_core,
89 .core_power_down = hda_dsp_core_reset_power_down,
92 .run = hda_dsp_cl_boot_firmware_iccmax,
95 .trace_init = hda_dsp_trace_init,
96 .trace_release = hda_dsp_trace_release,
97 .trace_trigger = hda_dsp_trace_trigger,
101 .num_drv = SOF_SKL_NUM_DAIS,
104 .suspend = hda_dsp_suspend,
105 .resume = hda_dsp_resume,
106 .runtime_suspend = hda_dsp_runtime_suspend,
107 .runtime_resume = hda_dsp_runtime_resume,
108 .runtime_idle = hda_dsp_runtime_idle,
109 .set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume,
110 .set_power_state = hda_dsp_set_power_state,
112 /* ALSA HW info flags */
113 .hw_info = SNDRV_PCM_INFO_MMAP |
114 SNDRV_PCM_INFO_MMAP_VALID |
115 SNDRV_PCM_INFO_INTERLEAVED |
116 SNDRV_PCM_INFO_PAUSE |
117 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
119 .arch_ops = &sof_xtensa_arch_ops,
121 EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
123 const struct sof_intel_dsp_desc tgl_chip_info = {
127 .host_managed_cores_mask = BIT(0),
128 .ipc_req = CNL_DSP_REG_HIPCIDR,
129 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
130 .ipc_ack = CNL_DSP_REG_HIPCIDA,
131 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
132 .ipc_ctl = CNL_DSP_REG_HIPCCTL,
133 .rom_init_timeout = 300,
134 .ssp_count = ICL_SSP_COUNT,
135 .ssp_base_offset = CNL_SSP_BASE_OFFSET,
137 EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
139 const struct sof_intel_dsp_desc tglh_chip_info = {
143 .host_managed_cores_mask = BIT(0),
144 .ipc_req = CNL_DSP_REG_HIPCIDR,
145 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
146 .ipc_ack = CNL_DSP_REG_HIPCIDA,
147 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
148 .ipc_ctl = CNL_DSP_REG_HIPCCTL,
149 .rom_init_timeout = 300,
150 .ssp_count = ICL_SSP_COUNT,
151 .ssp_base_offset = CNL_SSP_BASE_OFFSET,
153 EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);