1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
6 * Copyright(c) 2017 Intel Corporation. All rights reserved.
8 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
11 #ifndef __SOF_INTEL_HDA_H
12 #define __SOF_INTEL_HDA_H
14 #include <sound/hda_codec.h>
15 #include <sound/hdaudio_ext.h>
19 #define PCI_TCSEL 0x44
20 #define PCI_PGCTL PCI_TCSEL
21 #define PCI_CGCTL 0x48
24 #define PCI_PGCTL_ADSPPGD BIT(2)
25 #define PCI_PGCTL_LSRMD_MASK BIT(4)
28 #define PCI_CGCTL_MISCBDCGE_MASK BIT(6)
29 #define PCI_CGCTL_ADSPDCGE BIT(1)
31 /* Legacy HDA registers and bits used - widths are variable */
32 #define SOF_HDA_GCAP 0x0
33 #define SOF_HDA_GCTL 0x8
34 /* accept unsol. response enable */
35 #define SOF_HDA_GCTL_UNSOL BIT(8)
36 #define SOF_HDA_LLCH 0x14
37 #define SOF_HDA_INTCTL 0x20
38 #define SOF_HDA_INTSTS 0x24
39 #define SOF_HDA_WAKESTS 0x0E
40 #define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1)
41 #define SOF_HDA_RIRBSTS 0x5d
42 #define SOF_HDA_VS_EM2_L1SEN BIT(13)
44 /* SOF_HDA_GCTL register bist */
45 #define SOF_HDA_GCTL_RESET BIT(0)
47 /* SOF_HDA_INCTL and SOF_HDA_INTSTS regs */
48 #define SOF_HDA_INT_GLOBAL_EN BIT(31)
49 #define SOF_HDA_INT_CTRL_EN BIT(30)
50 #define SOF_HDA_INT_ALL_STREAM 0xff
52 #define SOF_HDA_MAX_CAPS 10
53 #define SOF_HDA_CAP_ID_OFF 16
54 #define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\
56 #define SOF_HDA_CAP_NEXT_MASK 0xFFFF
58 #define SOF_HDA_GTS_CAP_ID 0x1
59 #define SOF_HDA_ML_CAP_ID 0x2
61 #define SOF_HDA_PP_CAP_ID 0x3
62 #define SOF_HDA_REG_PP_PPCH 0x10
63 #define SOF_HDA_REG_PP_PPCTL 0x04
64 #define SOF_HDA_REG_PP_PPSTS 0x08
65 #define SOF_HDA_PPCTL_PIE BIT(31)
66 #define SOF_HDA_PPCTL_GPROCEN BIT(30)
68 /* DPIB entry size: 8 Bytes = 2 DWords */
69 #define SOF_HDA_DPIB_ENTRY_SIZE 0x8
71 #define SOF_HDA_SPIB_CAP_ID 0x4
72 #define SOF_HDA_DRSM_CAP_ID 0x5
74 #define SOF_HDA_SPIB_BASE 0x08
75 #define SOF_HDA_SPIB_INTERVAL 0x08
76 #define SOF_HDA_SPIB_SPIB 0x00
77 #define SOF_HDA_SPIB_MAXFIFO 0x04
79 #define SOF_HDA_PPHC_BASE 0x10
80 #define SOF_HDA_PPHC_INTERVAL 0x10
82 #define SOF_HDA_PPLC_BASE 0x10
83 #define SOF_HDA_PPLC_MULTI 0x10
84 #define SOF_HDA_PPLC_INTERVAL 0x10
86 #define SOF_HDA_DRSM_BASE 0x08
87 #define SOF_HDA_DRSM_INTERVAL 0x08
89 /* Descriptor error interrupt */
90 #define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10
92 /* FIFO error interrupt */
93 #define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08
95 /* Buffer completion interrupt */
96 #define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04
98 #define SOF_HDA_CL_DMA_SD_INT_MASK \
99 (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \
100 SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \
101 SOF_HDA_CL_DMA_SD_INT_COMPLETE)
102 #define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */
104 /* Intel HD Audio Code Loader DMA Registers */
105 #define SOF_HDA_ADSP_LOADER_BASE 0x80
106 #define SOF_HDA_ADSP_DPLBASE 0x70
107 #define SOF_HDA_ADSP_DPUBASE 0x74
108 #define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01
110 /* Stream Registers */
111 #define SOF_HDA_ADSP_REG_CL_SD_CTL 0x00
112 #define SOF_HDA_ADSP_REG_CL_SD_STS 0x03
113 #define SOF_HDA_ADSP_REG_CL_SD_LPIB 0x04
114 #define SOF_HDA_ADSP_REG_CL_SD_CBL 0x08
115 #define SOF_HDA_ADSP_REG_CL_SD_LVI 0x0C
116 #define SOF_HDA_ADSP_REG_CL_SD_FIFOW 0x0E
117 #define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE 0x10
118 #define SOF_HDA_ADSP_REG_CL_SD_FORMAT 0x12
119 #define SOF_HDA_ADSP_REG_CL_SD_FIFOL 0x14
120 #define SOF_HDA_ADSP_REG_CL_SD_BDLPL 0x18
121 #define SOF_HDA_ADSP_REG_CL_SD_BDLPU 0x1C
122 #define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20
124 /* CL: Software Position Based FIFO Capability Registers */
125 #define SOF_DSP_REG_CL_SPBFIFO \
126 (SOF_HDA_ADSP_LOADER_BASE + 0x20)
127 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0
128 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4
129 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8
130 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc
133 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20
134 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \
135 GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\
136 SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT)
138 #define HDA_DSP_HDA_BAR 0
139 #define HDA_DSP_PP_BAR 1
140 #define HDA_DSP_SPIB_BAR 2
141 #define HDA_DSP_DRSM_BAR 3
142 #define HDA_DSP_BAR 4
144 #define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000)
146 #define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0)
148 #define HDA_DSP_PANIC_OFFSET(x) \
149 (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET)
151 /* SRAM window 0 FW "registers" */
152 #define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0)
153 #define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4)
154 /* FW and ROM share offset 4 */
155 #define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4)
156 #define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8)
157 #define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc)
159 #define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000
161 #define HDA_DSP_STREAM_RESET_TIMEOUT 300
163 * Timeout in us, for setting the stream RUN bit, during
164 * start/stop the stream. The timeout expires if new RUN bit
165 * value cannot be read back within the specified time.
167 #define HDA_DSP_STREAM_RUN_TIMEOUT 300
168 #define HDA_DSP_CL_TRIGGER_TIMEOUT 300
170 #define HDA_DSP_SPIB_ENABLE 1
171 #define HDA_DSP_SPIB_DISABLE 0
173 #define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE)
175 #define HDA_DSP_STACK_DUMP_SIZE 32
177 /* ROM status/error values */
178 #define HDA_DSP_ROM_STS_MASK GENMASK(23, 0)
179 #define HDA_DSP_ROM_INIT 0x1
180 #define HDA_DSP_ROM_FW_MANIFEST_LOADED 0x3
181 #define HDA_DSP_ROM_FW_FW_LOADED 0x4
182 #define HDA_DSP_ROM_FW_ENTERED 0x5
183 #define HDA_DSP_ROM_RFW_START 0xf
184 #define HDA_DSP_ROM_CSE_ERROR 40
185 #define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41
186 #define HDA_DSP_ROM_IMR_TO_SMALL 42
187 #define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43
188 #define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44
189 #define HDA_DSP_ROM_IPC_FATAL_ERROR 45
190 #define HDA_DSP_ROM_L2_CACHE_ERROR 46
191 #define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47
192 #define HDA_DSP_ROM_API_PTR_INVALID 50
193 #define HDA_DSP_ROM_BASEFW_INCOMPAT 51
194 #define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000
195 #define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000
196 #define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000
197 #define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000
198 #define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000
199 #define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55
200 #define HDA_DSP_IPC_PURGE_FW 0x01004000
202 /* various timeout values */
203 #define HDA_DSP_PU_TIMEOUT 50
204 #define HDA_DSP_PD_TIMEOUT 50
205 #define HDA_DSP_RESET_TIMEOUT_US 50000
206 #define HDA_DSP_BASEFW_TIMEOUT_US 3000000
207 #define HDA_DSP_INIT_TIMEOUT_US 500000
208 #define HDA_DSP_CTRL_RESET_TIMEOUT 100
209 #define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */
210 #define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */
212 #define HDA_DSP_ADSPIC_IPC 1
213 #define HDA_DSP_ADSPIS_IPC 1
215 /* Intel HD Audio General DSP Registers */
216 #define HDA_DSP_GEN_BASE 0x0
217 #define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04)
218 #define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08)
219 #define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C)
220 #define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10)
221 #define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14)
223 /* Intel HD Audio Inter-Processor Communication Registers */
224 #define HDA_DSP_IPC_BASE 0x40
225 #define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00)
226 #define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04)
227 #define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08)
228 #define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C)
229 #define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10)
232 #define HDA_DSP_REG_HIPCI_BUSY BIT(31)
233 #define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF
236 #define HDA_DSP_REG_HIPCIE_DONE BIT(30)
237 #define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF
240 #define HDA_DSP_REG_HIPCCTL_DONE BIT(1)
241 #define HDA_DSP_REG_HIPCCTL_BUSY BIT(0)
244 #define HDA_DSP_REG_HIPCT_BUSY BIT(31)
245 #define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF
248 #define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF
250 #define HDA_DSP_ADSPIC_CL_DMA 0x2
251 #define HDA_DSP_ADSPIS_CL_DMA 0x2
253 /* Delay before scheduling D0i3 entry */
254 #define BXT_D0I3_DELAY 5000
256 #define FW_CL_STREAM_NUMBER 0x1
258 /* ADSPCS - Audio DSP Control & Status */
261 * Core Reset - asserted high
262 * CRST Mask for a given core mask pattern, cm
264 #define HDA_DSP_ADSPCS_CRST_SHIFT 0
265 #define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT)
268 * Core run/stall - when set to '1' core is stalled
269 * CSTALL Mask for a given core mask pattern, cm
271 #define HDA_DSP_ADSPCS_CSTALL_SHIFT 8
272 #define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT)
275 * Set Power Active - when set to '1' turn cores on
276 * SPA Mask for a given core mask pattern, cm
278 #define HDA_DSP_ADSPCS_SPA_SHIFT 16
279 #define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT)
282 * Current Power Active - power status of cores, set by hardware
283 * CPA Mask for a given core mask pattern, cm
285 #define HDA_DSP_ADSPCS_CPA_SHIFT 24
286 #define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT)
288 /* Mask for a given core index, c = 0.. number of supported cores - 1 */
289 #define HDA_DSP_CORE_MASK(c) BIT(c)
292 * Mask for a given number of cores
293 * nc = number of supported cores
295 #define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0)
297 /* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/
298 #define CNL_DSP_IPC_BASE 0xc0
299 #define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00)
300 #define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04)
301 #define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08)
302 #define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10)
303 #define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14)
304 #define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28)
307 #define CNL_DSP_REG_HIPCIDR_BUSY BIT(31)
308 #define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF
311 #define CNL_DSP_REG_HIPCIDA_DONE BIT(31)
312 #define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF
315 #define CNL_DSP_REG_HIPCCTL_DONE BIT(1)
316 #define CNL_DSP_REG_HIPCCTL_BUSY BIT(0)
319 #define CNL_DSP_REG_HIPCTDR_BUSY BIT(31)
320 #define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF
323 #define CNL_DSP_REG_HIPCTDA_DONE BIT(31)
324 #define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF
327 #define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF
330 #define HDA_DSP_BDL_SIZE 4096
331 #define HDA_DSP_MAX_BDL_ENTRIES \
332 (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl))
335 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
336 #define SOF_SKL_NUM_DAIS 14
338 #define SOF_SKL_NUM_DAIS 8
341 /* Intel HD Audio SRAM Window 0*/
342 #define HDA_ADSP_SRAM0_BASE_SKL 0x8000
344 /* Firmware status window */
345 #define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL
346 #define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4)
348 /* Host Device Memory Space */
349 #define APL_SSP_BASE_OFFSET 0x2000
350 #define CNL_SSP_BASE_OFFSET 0x10000
352 /* Host Device Memory Size of a Single SSP */
353 #define SSP_DEV_MEM_SIZE 0x1000
355 /* SSP Count of the Platform */
356 #define APL_SSP_COUNT 6
357 #define CNL_SSP_COUNT 3
358 #define ICL_SSP_COUNT 6
361 #define SSP_SSC1_OFFSET 0x4
362 #define SSP_SET_SCLK_SLAVE BIT(25)
363 #define SSP_SET_SFRM_SLAVE BIT(24)
364 #define SSP_SET_SLAVE (SSP_SET_SCLK_SLAVE | SSP_SET_SFRM_SLAVE)
366 #define HDA_IDISP_CODEC(x) ((x) & BIT(2))
368 struct sof_intel_dsp_bdl {
373 } __attribute((packed));
375 #define SOF_HDA_PLAYBACK_STREAMS 16
376 #define SOF_HDA_CAPTURE_STREAMS 16
377 #define SOF_HDA_PLAYBACK 0
378 #define SOF_HDA_CAPTURE 1
380 /* represents DSP HDA controller frontend - i.e. host facing control */
381 struct sof_intel_hda_dev {
386 const struct sof_intel_dsp_desc *desc;
389 struct hdac_ext_stream *dtrace_stream;
391 /* if position update IPC needed */
394 /* the maximum number of streams (playback + capture) supported */
400 struct platform_device *dmic_dev;
403 static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s)
405 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
407 return &hda->hbus.core;
410 static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s)
412 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
417 struct sof_intel_hda_stream {
418 struct snd_sof_dev *sdev;
419 struct hdac_ext_stream hda_stream;
420 struct sof_intel_stream stream;
421 int host_reserved; /* reserve host DMA channel */
424 #define hstream_to_sof_hda_stream(hstream) \
425 container_of(hstream, struct sof_intel_hda_stream, hda_stream)
427 #define bus_to_sof_hda(bus) \
428 container_of(bus, struct sof_intel_hda_dev, hbus.core)
430 #define SOF_STREAM_SD_OFFSET(s) \
431 (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \
432 + SOF_HDA_ADSP_LOADER_BASE)
437 int hda_dsp_probe(struct snd_sof_dev *sdev);
438 int hda_dsp_remove(struct snd_sof_dev *sdev);
439 int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev,
440 unsigned int core_mask);
441 int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev,
442 unsigned int core_mask);
443 int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask);
444 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask);
445 int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask);
446 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask);
447 int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask);
448 bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev,
449 unsigned int core_mask);
450 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
451 unsigned int core_mask);
452 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev);
453 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev);
455 int hda_dsp_suspend(struct snd_sof_dev *sdev);
456 int hda_dsp_resume(struct snd_sof_dev *sdev);
457 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev);
458 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev);
459 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev);
460 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev);
461 void hda_dsp_dump_skl(struct snd_sof_dev *sdev, u32 flags);
462 void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags);
463 void hda_ipc_dump(struct snd_sof_dev *sdev);
464 void hda_ipc_irq_dump(struct snd_sof_dev *sdev);
467 * DSP PCM Operations.
469 int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
470 struct snd_pcm_substream *substream);
471 int hda_dsp_pcm_close(struct snd_sof_dev *sdev,
472 struct snd_pcm_substream *substream);
473 int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev,
474 struct snd_pcm_substream *substream,
475 struct snd_pcm_hw_params *params,
476 struct sof_ipc_stream_params *ipc_params);
477 int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev,
478 struct snd_pcm_substream *substream);
479 int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev,
480 struct snd_pcm_substream *substream, int cmd);
481 snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev,
482 struct snd_pcm_substream *substream);
485 * DSP Stream Operations.
488 int hda_dsp_stream_init(struct snd_sof_dev *sdev);
489 void hda_dsp_stream_free(struct snd_sof_dev *sdev);
490 int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
491 struct hdac_ext_stream *stream,
492 struct snd_dma_buffer *dmab,
493 struct snd_pcm_hw_params *params);
494 int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
495 struct hdac_ext_stream *stream, int cmd);
496 irqreturn_t hda_dsp_stream_interrupt(int irq, void *context);
497 irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context);
498 int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
499 struct snd_dma_buffer *dmab,
500 struct hdac_stream *stream);
502 struct hdac_ext_stream *
503 hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction);
504 int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag);
505 int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
506 struct hdac_ext_stream *stream,
507 int enable, u32 size);
509 void hda_ipc_msg_data(struct snd_sof_dev *sdev,
510 struct snd_pcm_substream *substream,
512 int hda_ipc_pcm_params(struct snd_sof_dev *sdev,
513 struct snd_pcm_substream *substream,
514 const struct sof_ipc_pcm_params_reply *reply);
517 * DSP IPC Operations.
519 int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev,
520 struct snd_sof_ipc_msg *msg);
521 void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev);
522 int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
523 int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
525 irqreturn_t hda_dsp_ipc_irq_handler(int irq, void *context);
526 irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context);
527 int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir);
532 int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev);
533 int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev);
535 /* pre and post fw run ops */
536 int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev);
537 int hda_dsp_post_fw_run(struct snd_sof_dev *sdev);
540 * HDA Controller Operations.
542 int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev);
543 void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable);
544 void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable);
545 int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset);
546 void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable);
547 int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable);
548 int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset);
549 void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev);
551 * HDA bus operations.
553 void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev);
555 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
557 * HDA Codec operations.
559 int hda_codec_probe_bus(struct snd_sof_dev *sdev);
560 void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev);
561 void hda_codec_jack_check(struct snd_sof_dev *sdev);
563 #endif /* CONFIG_SND_SOC_SOF_HDA */
565 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)
567 void hda_codec_i915_get(struct snd_sof_dev *sdev);
568 void hda_codec_i915_put(struct snd_sof_dev *sdev);
569 int hda_codec_i915_init(struct snd_sof_dev *sdev);
570 int hda_codec_i915_exit(struct snd_sof_dev *sdev);
574 static inline void hda_codec_i915_get(struct snd_sof_dev *sdev) { }
575 static inline void hda_codec_i915_put(struct snd_sof_dev *sdev) { }
576 static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; }
577 static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; }
579 #endif /* CONFIG_SND_SOC_SOF_HDA && CONFIG_SND_SOC_HDAC_HDMI */
584 int hda_dsp_trace_init(struct snd_sof_dev *sdev, u32 *stream_tag);
585 int hda_dsp_trace_release(struct snd_sof_dev *sdev);
586 int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd);
588 /* common dai driver */
589 extern struct snd_soc_dai_driver skl_dai[];
592 * Platform Specific HW abstraction Ops.
594 extern const struct snd_sof_dsp_ops sof_apl_ops;
595 extern const struct snd_sof_dsp_ops sof_cnl_ops;
596 extern const struct snd_sof_dsp_ops sof_skl_ops;
598 extern const struct sof_intel_dsp_desc apl_chip_info;
599 extern const struct sof_intel_dsp_desc cnl_chip_info;
600 extern const struct sof_intel_dsp_desc skl_chip_info;
601 extern const struct sof_intel_dsp_desc icl_chip_info;
602 extern const struct sof_intel_dsp_desc tgl_chip_info;
603 extern const struct sof_intel_dsp_desc ehl_chip_info;