1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
6 // Copyright(c) 2018 Intel Corporation. All rights reserved.
8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
10 // Rander Wang <rander.wang@intel.com>
11 // Keyon Jie <yang.jie@linux.intel.com>
15 * Hardware interface for generic Intel audio DSP HDA IP
18 #include <sound/hdaudio_ext.h>
19 #include <sound/hda_register.h>
20 #include "../sof-audio.h"
29 int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, unsigned int core_mask)
35 /* set reset bits for cores */
36 reset = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
37 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
41 /* poll with timeout to check if operation successful */
42 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
43 HDA_DSP_REG_ADSPCS, adspcs,
44 ((adspcs & reset) == reset),
45 HDA_DSP_REG_POLL_INTERVAL_US,
46 HDA_DSP_RESET_TIMEOUT_US);
49 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
54 /* has core entered reset ? */
55 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
57 if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) !=
58 HDA_DSP_ADSPCS_CRST_MASK(core_mask)) {
60 "error: reset enter failed: core_mask %x adspcs 0x%x\n",
68 int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, unsigned int core_mask)
74 /* clear reset bits for cores */
75 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
77 HDA_DSP_ADSPCS_CRST_MASK(core_mask),
80 /* poll with timeout to check if operation successful */
81 crst = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
82 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
83 HDA_DSP_REG_ADSPCS, adspcs,
85 HDA_DSP_REG_POLL_INTERVAL_US,
86 HDA_DSP_RESET_TIMEOUT_US);
90 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
95 /* has core left reset ? */
96 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
98 if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) != 0) {
100 "error: reset leave failed: core_mask %x adspcs 0x%x\n",
108 int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask)
111 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
113 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
114 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
116 /* set reset state */
117 return hda_dsp_core_reset_enter(sdev, core_mask);
120 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask)
124 /* leave reset state */
125 ret = hda_dsp_core_reset_leave(sdev, core_mask);
130 dev_dbg(sdev->dev, "unstall/run core: core_mask = %x\n", core_mask);
131 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
133 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
136 /* is core now running ? */
137 if (!hda_dsp_core_is_enabled(sdev, core_mask)) {
138 hda_dsp_core_stall_reset(sdev, core_mask);
139 dev_err(sdev->dev, "error: DSP start core failed: core_mask %x\n",
151 int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask)
158 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS,
159 HDA_DSP_ADSPCS_SPA_MASK(core_mask),
160 HDA_DSP_ADSPCS_SPA_MASK(core_mask));
162 /* poll with timeout to check if operation successful */
163 cpa = HDA_DSP_ADSPCS_CPA_MASK(core_mask);
164 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
165 HDA_DSP_REG_ADSPCS, adspcs,
166 (adspcs & cpa) == cpa,
167 HDA_DSP_REG_POLL_INTERVAL_US,
168 HDA_DSP_RESET_TIMEOUT_US);
171 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
176 /* did core power up ? */
177 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
179 if ((adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) !=
180 HDA_DSP_ADSPCS_CPA_MASK(core_mask)) {
182 "error: power up core failed core_mask %xadspcs 0x%x\n",
190 int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask)
196 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
198 HDA_DSP_ADSPCS_SPA_MASK(core_mask), 0);
200 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
201 HDA_DSP_REG_ADSPCS, adspcs,
202 !(adspcs & HDA_DSP_ADSPCS_SPA_MASK(core_mask)),
203 HDA_DSP_REG_POLL_INTERVAL_US,
204 HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC);
207 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
213 bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev,
214 unsigned int core_mask)
219 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS);
221 is_enable = ((val & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) &&
222 (val & HDA_DSP_ADSPCS_SPA_MASK(core_mask)) &&
223 !(val & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) &&
224 !(val & HDA_DSP_ADSPCS_CSTALL_MASK(core_mask)));
226 dev_dbg(sdev->dev, "DSP core(s) enabled? %d : core_mask %x\n",
227 is_enable, core_mask);
232 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask)
236 /* return if core is already enabled */
237 if (hda_dsp_core_is_enabled(sdev, core_mask))
241 ret = hda_dsp_core_power_up(sdev, core_mask);
243 dev_err(sdev->dev, "error: dsp core power up failed: core_mask %x\n",
248 return hda_dsp_core_run(sdev, core_mask);
251 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
252 unsigned int core_mask)
256 /* place core in reset prior to power down */
257 ret = hda_dsp_core_stall_reset(sdev, core_mask);
259 dev_err(sdev->dev, "error: dsp core reset failed: core_mask %x\n",
264 /* power down core */
265 ret = hda_dsp_core_power_down(sdev, core_mask);
267 dev_err(sdev->dev, "error: dsp core power down fail mask %x: %d\n",
272 /* make sure we are in OFF state */
273 if (hda_dsp_core_is_enabled(sdev, core_mask)) {
274 dev_err(sdev->dev, "error: dsp core disable fail mask %x: %d\n",
282 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev)
284 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
285 const struct sof_intel_dsp_desc *chip = hda->desc;
287 /* enable IPC DONE and BUSY interrupts */
288 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
289 HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY,
290 HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY);
292 /* enable IPC interrupt */
293 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
294 HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC);
297 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev)
299 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
300 const struct sof_intel_dsp_desc *chip = hda->desc;
302 /* disable IPC interrupt */
303 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
304 HDA_DSP_ADSPIC_IPC, 0);
306 /* disable IPC BUSY and DONE interrupt */
307 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
308 HDA_DSP_REG_HIPCCTL_BUSY | HDA_DSP_REG_HIPCCTL_DONE, 0);
311 static int hda_dsp_wait_d0i3c_done(struct snd_sof_dev *sdev)
313 struct hdac_bus *bus = sof_to_bus(sdev);
314 int retry = HDA_DSP_REG_POLL_RETRY_COUNT;
316 while (snd_hdac_chip_readb(bus, VS_D0I3C) & SOF_HDA_VS_D0I3C_CIP) {
319 usleep_range(10, 15);
325 static int hda_dsp_send_pm_gate_ipc(struct snd_sof_dev *sdev, u32 flags)
327 struct sof_ipc_pm_gate pm_gate;
328 struct sof_ipc_reply reply;
330 memset(&pm_gate, 0, sizeof(pm_gate));
332 /* configure pm_gate ipc message */
333 pm_gate.hdr.size = sizeof(pm_gate);
334 pm_gate.hdr.cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE;
335 pm_gate.flags = flags;
337 /* send pm_gate ipc to dsp */
338 return sof_ipc_tx_message_no_pm(sdev->ipc, pm_gate.hdr.cmd,
339 &pm_gate, sizeof(pm_gate), &reply,
343 static int hda_dsp_update_d0i3c_register(struct snd_sof_dev *sdev, u8 value)
345 struct hdac_bus *bus = sof_to_bus(sdev);
348 /* Write to D0I3C after Command-In-Progress bit is cleared */
349 ret = hda_dsp_wait_d0i3c_done(sdev);
351 dev_err(bus->dev, "CIP timeout before D0I3C update!\n");
355 /* Update D0I3C register */
356 snd_hdac_chip_updateb(bus, VS_D0I3C, SOF_HDA_VS_D0I3C_I3, value);
358 /* Wait for cmd in progress to be cleared before exiting the function */
359 ret = hda_dsp_wait_d0i3c_done(sdev);
361 dev_err(bus->dev, "CIP timeout after D0I3C update!\n");
365 dev_vdbg(bus->dev, "D0I3C updated, register = 0x%x\n",
366 snd_hdac_chip_readb(bus, VS_D0I3C));
371 static int hda_dsp_set_D0_state(struct snd_sof_dev *sdev,
372 const struct sof_dsp_power_state *target_state)
379 * Sanity check for illegal state transitions
380 * The only allowed transitions are:
385 switch (sdev->dsp_power_state.state) {
387 /* Follow the sequence below for D0 substate transitions */
390 /* Follow regular flow for D3 -> D0 transition */
393 dev_err(sdev->dev, "error: transition from %d to %d not allowed\n",
394 sdev->dsp_power_state.state, target_state->state);
398 /* Set flags and register value for D0 target substate */
399 if (target_state->substate == SOF_HDA_DSP_PM_D0I3) {
400 value = SOF_HDA_VS_D0I3C_I3;
402 /* disable DMA trace in D0I3 */
403 flags = HDA_PM_NO_DMA_TRACE;
405 /* prevent power gating in D0I0 */
409 /* update D0I3C register */
410 ret = hda_dsp_update_d0i3c_register(sdev, value);
415 * Notify the DSP of the state change.
416 * If this IPC fails, revert the D0I3C register update in order
417 * to prevent partial state change.
419 ret = hda_dsp_send_pm_gate_ipc(sdev, flags);
422 "error: PM_GATE ipc error %d\n", ret);
429 /* fallback to the previous register value */
430 value = value ? 0 : SOF_HDA_VS_D0I3C_I3;
433 * This can fail but return the IPC error to signal that
434 * the state change failed.
436 hda_dsp_update_d0i3c_register(sdev, value);
442 * All DSP power state transitions are initiated by the driver.
443 * If the requested state change fails, the error is simply returned.
444 * Further state transitions are attempted only when the set_power_save() op
445 * is called again either because of a new IPC sent to the DSP or
446 * during system suspend/resume.
448 int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
449 const struct sof_dsp_power_state *target_state)
453 /* Nothing to do if the DSP is already in the requested state */
454 if (target_state->state == sdev->dsp_power_state.state &&
455 target_state->substate == sdev->dsp_power_state.substate)
458 switch (target_state->state) {
460 ret = hda_dsp_set_D0_state(sdev, target_state);
463 /* The only allowed transition is: D0I0 -> D3 */
464 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0 &&
465 sdev->dsp_power_state.substate == SOF_HDA_DSP_PM_D0I0)
469 "error: transition from %d to %d not allowed\n",
470 sdev->dsp_power_state.state, target_state->state);
473 dev_err(sdev->dev, "error: target state unsupported %d\n",
474 target_state->state);
479 "failed to set requested target DSP state %d substate %d\n",
480 target_state->state, target_state->substate);
484 sdev->dsp_power_state = *target_state;
485 dev_dbg(sdev->dev, "New DSP state %d substate %d\n",
486 target_state->state, target_state->substate);
491 * Audio DSP states may transform as below:-
493 * Opportunistic D0I3 in S0
494 * Runtime +---------------------+ Delayed D0i3 work timeout
495 * suspend | +--------------------+
496 * +------------+ D0I0(active) | |
497 * | | <---------------+ |
498 * | +--------> | New IPC | |
499 * | |Runtime +--^--+---------^--+--+ (via mailbox) | |
500 * | |resume | | | | | |
502 * | | System| | | | | |
503 * | | resume| | S3/S0IX | | | |
504 * | | | | suspend | | S0IX | |
505 * | | | | | |suspend | |
508 * +-v---+-----------+--v-------+ | | +------+----v----+
509 * | | | +-----------> |
510 * | D3 (suspended) | | | D0I3 |
511 * | | +--------------+ |
512 * | | System resume | |
513 * +----------------------------+ +----------------+
515 * S0IX suspend: The DSP is in D0I3 if any D0I3-compatible streams
516 * ignored the suspend trigger. Otherwise the DSP
520 static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend)
522 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
523 const struct sof_intel_dsp_desc *chip = hda->desc;
524 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
525 struct hdac_bus *bus = sof_to_bus(sdev);
529 /* disable IPC interrupts */
530 hda_dsp_ipc_int_disable(sdev);
532 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
534 hda_codec_jack_wake_enable(sdev);
536 /* power down all hda link */
537 snd_hdac_ext_bus_link_power_down_all(bus);
541 ret = hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
544 "error: failed to power down core during suspend\n");
548 /* disable ppcap interrupt */
549 hda_dsp_ctrl_ppcap_enable(sdev, false);
550 hda_dsp_ctrl_ppcap_int_enable(sdev, false);
552 /* disable hda bus irq and streams */
553 hda_dsp_ctrl_stop_chip(sdev);
555 /* disable LP retention mode */
556 snd_sof_pci_update_bits(sdev, PCI_PGCTL,
557 PCI_PGCTL_LSRMD_MASK, PCI_PGCTL_LSRMD_MASK);
559 /* reset controller */
560 ret = hda_dsp_ctrl_link_reset(sdev, true);
563 "error: failed to reset controller during suspend\n");
570 static int hda_resume(struct snd_sof_dev *sdev, bool runtime_resume)
572 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
573 struct hdac_bus *bus = sof_to_bus(sdev);
574 struct hdac_ext_link *hlink = NULL;
579 * clear TCSEL to clear playback on some HD Audio
580 * codecs. PCI TCSEL is defined in the Intel manuals.
582 snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);
584 /* reset and start hda controller */
585 ret = hda_dsp_ctrl_init_chip(sdev, true);
588 "error: failed to start controller after resume\n");
592 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
593 /* check jack status */
595 hda_codec_jack_check(sdev);
597 /* turn off the links that were off before suspend */
598 list_for_each_entry(hlink, &bus->hlink_list, list) {
599 if (!hlink->ref_count)
600 snd_hdac_ext_bus_link_power_down(hlink);
603 /* check dma status and clean up CORB/RIRB buffers */
604 if (!bus->cmd_dma_state)
605 snd_hdac_bus_stop_cmd_io(bus);
608 /* enable ppcap interrupt */
609 hda_dsp_ctrl_ppcap_enable(sdev, true);
610 hda_dsp_ctrl_ppcap_int_enable(sdev, true);
615 int hda_dsp_resume(struct snd_sof_dev *sdev)
617 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
618 struct pci_dev *pci = to_pci_dev(sdev->dev);
619 const struct sof_dsp_power_state target_state = {
620 .state = SOF_DSP_PM_D0,
621 .substate = SOF_HDA_DSP_PM_D0I0,
625 /* resume from D0I3 */
626 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0) {
627 /* Set DSP power state */
628 ret = hda_dsp_set_power_state(sdev, &target_state);
630 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
631 target_state.state, target_state.substate);
635 /* restore L1SEN bit */
636 if (hda->l1_support_changed)
637 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
639 HDA_VS_INTEL_EM2_L1SEN, 0);
641 /* restore and disable the system wakeup */
642 pci_restore_state(pci);
643 disable_irq_wake(pci->irq);
647 /* init hda controller. DSP cores will be powered up during fw boot */
648 ret = hda_resume(sdev, false);
652 hda_dsp_set_power_state(sdev, &target_state);
656 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev)
658 const struct sof_dsp_power_state target_state = {
659 .state = SOF_DSP_PM_D0,
663 /* init hda controller. DSP cores will be powered up during fw boot */
664 ret = hda_resume(sdev, true);
668 return hda_dsp_set_power_state(sdev, &target_state);
671 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev)
673 struct hdac_bus *hbus = sof_to_bus(sdev);
675 if (hbus->codec_powered) {
676 dev_dbg(sdev->dev, "some codecs still powered (%08X), not idle\n",
677 (unsigned int)hbus->codec_powered);
684 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev)
686 const struct sof_dsp_power_state target_state = {
687 .state = SOF_DSP_PM_D3,
691 /* stop hda controller and power dsp off */
692 ret = hda_suspend(sdev, true);
696 return hda_dsp_set_power_state(sdev, &target_state);
699 int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
701 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
702 struct hdac_bus *bus = sof_to_bus(sdev);
703 struct pci_dev *pci = to_pci_dev(sdev->dev);
704 const struct sof_dsp_power_state target_dsp_state = {
705 .state = target_state,
706 .substate = target_state == SOF_DSP_PM_D0 ?
707 SOF_HDA_DSP_PM_D0I3 : 0,
711 /* cancel any attempt for DSP D0I3 */
712 cancel_delayed_work_sync(&hda->d0i3_work);
714 if (target_state == SOF_DSP_PM_D0) {
715 /* Set DSP power state */
716 ret = hda_dsp_set_power_state(sdev, &target_dsp_state);
718 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
719 target_dsp_state.state,
720 target_dsp_state.substate);
724 /* enable L1SEN to make sure the system can enter S0Ix */
725 hda->l1_support_changed =
726 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
728 HDA_VS_INTEL_EM2_L1SEN,
729 HDA_VS_INTEL_EM2_L1SEN);
731 /* enable the system waking up via IPC IRQ */
732 enable_irq_wake(pci->irq);
737 /* stop hda controller and power dsp off */
738 ret = hda_suspend(sdev, false);
740 dev_err(bus->dev, "error: suspending dsp\n");
744 return hda_dsp_set_power_state(sdev, &target_dsp_state);
747 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev)
749 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
750 struct hdac_bus *bus = sof_to_bus(sdev);
751 struct snd_soc_pcm_runtime *rtd;
752 struct hdac_ext_stream *stream;
753 struct hdac_ext_link *link;
754 struct hdac_stream *s;
758 /* set internal flag for BE */
759 list_for_each_entry(s, &bus->stream_list, list) {
760 stream = stream_to_hdac_ext_stream(s);
763 * clear stream. This should already be taken care for running
764 * streams when the SUSPEND trigger is called. But paused
765 * streams do not get suspended, so this needs to be done
766 * explicitly during suspend.
768 if (stream->link_substream) {
769 rtd = snd_pcm_substream_chip(stream->link_substream);
770 name = rtd->codec_dai->component->name;
771 link = snd_hdac_ext_bus_get_link(bus, name);
775 stream->link_prepared = 0;
777 if (hdac_stream(stream)->direction ==
778 SNDRV_PCM_STREAM_CAPTURE)
781 stream_tag = hdac_stream(stream)->stream_tag;
782 snd_hdac_ext_link_clear_stream_id(link, stream_tag);
789 void hda_dsp_d0i3_work(struct work_struct *work)
791 struct sof_intel_hda_dev *hdev = container_of(work,
792 struct sof_intel_hda_dev,
794 struct hdac_bus *bus = &hdev->hbus.core;
795 struct snd_sof_dev *sdev = dev_get_drvdata(bus->dev);
796 struct sof_dsp_power_state target_state;
799 target_state.state = SOF_DSP_PM_D0;
801 /* DSP can enter D0I3 iff only D0I3-compatible streams are active */
802 if (snd_sof_dsp_only_d0i3_compatible_stream_active(sdev))
803 target_state.substate = SOF_HDA_DSP_PM_D0I3;
805 target_state.substate = SOF_HDA_DSP_PM_D0I0;
808 if (target_state.substate == SOF_HDA_DSP_PM_D0I0)
811 /* This can fail but error cannot be propagated */
812 ret = hda_dsp_set_power_state(sdev, &target_state);
814 dev_err_ratelimited(sdev->dev,
815 "error: failed to set DSP state %d substate %d\n",
816 target_state.state, target_state.substate);