1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
6 // Copyright(c) 2018 Intel Corporation. All rights reserved.
8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
10 // Rander Wang <rander.wang@intel.com>
11 // Keyon Jie <yang.jie@linux.intel.com>
15 * Hardware interface for generic Intel audio DSP HDA IP
18 #include <sound/hdaudio_ext.h>
19 #include <sound/hda_register.h>
28 int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, unsigned int core_mask)
34 /* set reset bits for cores */
35 reset = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
36 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
40 /* poll with timeout to check if operation successful */
41 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
42 HDA_DSP_REG_ADSPCS, adspcs,
43 ((adspcs & reset) == reset),
44 HDA_DSP_REG_POLL_INTERVAL_US,
45 HDA_DSP_RESET_TIMEOUT_US);
48 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
53 /* has core entered reset ? */
54 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
56 if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) !=
57 HDA_DSP_ADSPCS_CRST_MASK(core_mask)) {
59 "error: reset enter failed: core_mask %x adspcs 0x%x\n",
67 int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, unsigned int core_mask)
73 /* clear reset bits for cores */
74 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
76 HDA_DSP_ADSPCS_CRST_MASK(core_mask),
79 /* poll with timeout to check if operation successful */
80 crst = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
81 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
82 HDA_DSP_REG_ADSPCS, adspcs,
84 HDA_DSP_REG_POLL_INTERVAL_US,
85 HDA_DSP_RESET_TIMEOUT_US);
89 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
94 /* has core left reset ? */
95 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
97 if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) != 0) {
99 "error: reset leave failed: core_mask %x adspcs 0x%x\n",
107 int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask)
110 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
112 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
113 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
115 /* set reset state */
116 return hda_dsp_core_reset_enter(sdev, core_mask);
119 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask)
123 /* leave reset state */
124 ret = hda_dsp_core_reset_leave(sdev, core_mask);
129 dev_dbg(sdev->dev, "unstall/run core: core_mask = %x\n", core_mask);
130 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
132 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
135 /* is core now running ? */
136 if (!hda_dsp_core_is_enabled(sdev, core_mask)) {
137 hda_dsp_core_stall_reset(sdev, core_mask);
138 dev_err(sdev->dev, "error: DSP start core failed: core_mask %x\n",
150 int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask)
157 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS,
158 HDA_DSP_ADSPCS_SPA_MASK(core_mask),
159 HDA_DSP_ADSPCS_SPA_MASK(core_mask));
161 /* poll with timeout to check if operation successful */
162 cpa = HDA_DSP_ADSPCS_CPA_MASK(core_mask);
163 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
164 HDA_DSP_REG_ADSPCS, adspcs,
165 (adspcs & cpa) == cpa,
166 HDA_DSP_REG_POLL_INTERVAL_US,
167 HDA_DSP_RESET_TIMEOUT_US);
170 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
175 /* did core power up ? */
176 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
178 if ((adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) !=
179 HDA_DSP_ADSPCS_CPA_MASK(core_mask)) {
181 "error: power up core failed core_mask %xadspcs 0x%x\n",
189 int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask)
195 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
197 HDA_DSP_ADSPCS_SPA_MASK(core_mask), 0);
199 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
200 HDA_DSP_REG_ADSPCS, adspcs,
201 !(adspcs & HDA_DSP_ADSPCS_SPA_MASK(core_mask)),
202 HDA_DSP_REG_POLL_INTERVAL_US,
203 HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC);
206 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
212 bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev,
213 unsigned int core_mask)
218 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS);
220 is_enable = ((val & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) &&
221 (val & HDA_DSP_ADSPCS_SPA_MASK(core_mask)) &&
222 !(val & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) &&
223 !(val & HDA_DSP_ADSPCS_CSTALL_MASK(core_mask)));
225 dev_dbg(sdev->dev, "DSP core(s) enabled? %d : core_mask %x\n",
226 is_enable, core_mask);
231 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask)
235 /* return if core is already enabled */
236 if (hda_dsp_core_is_enabled(sdev, core_mask))
240 ret = hda_dsp_core_power_up(sdev, core_mask);
242 dev_err(sdev->dev, "error: dsp core power up failed: core_mask %x\n",
247 return hda_dsp_core_run(sdev, core_mask);
250 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
251 unsigned int core_mask)
255 /* place core in reset prior to power down */
256 ret = hda_dsp_core_stall_reset(sdev, core_mask);
258 dev_err(sdev->dev, "error: dsp core reset failed: core_mask %x\n",
263 /* power down core */
264 ret = hda_dsp_core_power_down(sdev, core_mask);
266 dev_err(sdev->dev, "error: dsp core power down fail mask %x: %d\n",
271 /* make sure we are in OFF state */
272 if (hda_dsp_core_is_enabled(sdev, core_mask)) {
273 dev_err(sdev->dev, "error: dsp core disable fail mask %x: %d\n",
281 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev)
283 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
284 const struct sof_intel_dsp_desc *chip = hda->desc;
286 /* enable IPC DONE and BUSY interrupts */
287 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
288 HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY,
289 HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY);
291 /* enable IPC interrupt */
292 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
293 HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC);
296 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev)
298 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
299 const struct sof_intel_dsp_desc *chip = hda->desc;
301 /* disable IPC interrupt */
302 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
303 HDA_DSP_ADSPIC_IPC, 0);
305 /* disable IPC BUSY and DONE interrupt */
306 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
307 HDA_DSP_REG_HIPCCTL_BUSY | HDA_DSP_REG_HIPCCTL_DONE, 0);
310 static int hda_dsp_wait_d0i3c_done(struct snd_sof_dev *sdev)
312 struct hdac_bus *bus = sof_to_bus(sdev);
313 int retry = HDA_DSP_REG_POLL_RETRY_COUNT;
315 while (snd_hdac_chip_readb(bus, VS_D0I3C) & SOF_HDA_VS_D0I3C_CIP) {
318 usleep_range(10, 15);
324 static int hda_dsp_send_pm_gate_ipc(struct snd_sof_dev *sdev, u32 flags)
326 struct sof_ipc_pm_gate pm_gate;
327 struct sof_ipc_reply reply;
329 memset(&pm_gate, 0, sizeof(pm_gate));
331 /* configure pm_gate ipc message */
332 pm_gate.hdr.size = sizeof(pm_gate);
333 pm_gate.hdr.cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE;
334 pm_gate.flags = flags;
336 /* send pm_gate ipc to dsp */
337 return sof_ipc_tx_message(sdev->ipc, pm_gate.hdr.cmd, &pm_gate,
338 sizeof(pm_gate), &reply, sizeof(reply));
341 static int hda_dsp_update_d0i3c_register(struct snd_sof_dev *sdev, u8 value)
343 struct hdac_bus *bus = sof_to_bus(sdev);
346 /* Write to D0I3C after Command-In-Progress bit is cleared */
347 ret = hda_dsp_wait_d0i3c_done(sdev);
349 dev_err(bus->dev, "CIP timeout before D0I3C update!\n");
353 /* Update D0I3C register */
354 snd_hdac_chip_updateb(bus, VS_D0I3C, SOF_HDA_VS_D0I3C_I3, value);
356 /* Wait for cmd in progress to be cleared before exiting the function */
357 ret = hda_dsp_wait_d0i3c_done(sdev);
359 dev_err(bus->dev, "CIP timeout after D0I3C update!\n");
363 dev_vdbg(bus->dev, "D0I3C updated, register = 0x%x\n",
364 snd_hdac_chip_readb(bus, VS_D0I3C));
369 static int hda_dsp_set_D0_state(struct snd_sof_dev *sdev,
370 const struct sof_dsp_power_state *target_state)
377 * Sanity check for illegal state transitions
378 * The only allowed transitions are:
383 switch (sdev->dsp_power_state.state) {
385 /* Follow the sequence below for D0 substate transitions */
388 /* Follow regular flow for D3 -> D0 transition */
391 dev_err(sdev->dev, "error: transition from %d to %d not allowed\n",
392 sdev->dsp_power_state.state, target_state->state);
396 /* Set flags and register value for D0 target substate */
397 if (target_state->substate == SOF_HDA_DSP_PM_D0I3) {
398 value = SOF_HDA_VS_D0I3C_I3;
400 /* disable DMA trace in D0I3 */
401 flags = HDA_PM_NO_DMA_TRACE;
403 /* prevent power gating in D0I0 */
407 /* update D0I3C register */
408 ret = hda_dsp_update_d0i3c_register(sdev, value);
413 * Notify the DSP of the state change.
414 * If this IPC fails, revert the D0I3C register update in order
415 * to prevent partial state change.
417 ret = hda_dsp_send_pm_gate_ipc(sdev, flags);
420 "error: PM_GATE ipc error %d\n", ret);
427 /* fallback to the previous register value */
428 value = value ? 0 : SOF_HDA_VS_D0I3C_I3;
431 * This can fail but return the IPC error to signal that
432 * the state change failed.
434 hda_dsp_update_d0i3c_register(sdev, value);
440 * All DSP power state transitions are initiated by the driver.
441 * If the requested state change fails, the error is simply returned.
442 * Further state transitions are attempted only when the set_power_save() op
443 * is called again either because of a new IPC sent to the DSP or
444 * during system suspend/resume.
446 int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
447 const struct sof_dsp_power_state *target_state)
451 /* Nothing to do if the DSP is already in the requested state */
452 if (target_state->state == sdev->dsp_power_state.state &&
453 target_state->substate == sdev->dsp_power_state.substate)
456 switch (target_state->state) {
458 ret = hda_dsp_set_D0_state(sdev, target_state);
461 /* The only allowed transition is: D0I0 -> D3 */
462 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0 &&
463 sdev->dsp_power_state.substate == SOF_HDA_DSP_PM_D0I0)
467 "error: transition from %d to %d not allowed\n",
468 sdev->dsp_power_state.state, target_state->state);
471 dev_err(sdev->dev, "error: target state unsupported %d\n",
472 target_state->state);
477 "failed to set requested target DSP state %d substate %d\n",
478 target_state->state, target_state->substate);
482 sdev->dsp_power_state = *target_state;
483 dev_dbg(sdev->dev, "New DSP state %d substate %d\n",
484 target_state->state, target_state->substate);
489 * Audio DSP states may transform as below:-
491 * D0I3 compatible stream
492 * Runtime +---------------------+ opened only, timeout
493 * suspend | +--------------------+
494 * +------------+ D0(active) | |
495 * | | <---------------+ |
497 * | |Runtime +--^--+---------^--+--+ The last | |
498 * | |resume | | | | opened D0I3 | |
499 * | | | | | | compatible | |
500 * | | resume| | | | stream closed | |
501 * | | from | | D3 | | | |
502 * | | D3 | |suspend | | d0i3 | |
503 * | | | | | |suspend | |
506 * +-v---+-----------+--v-------+ | | +------+----v----+
507 * | | | +-----------> |
508 * | D3 (suspended) | | | D0I3 +-----+
509 * | | +--------------+ | |
510 * | | resume from | | |
511 * +-------------------^--------+ d0i3 suspend +----------------+ |
514 * +------------------------------------------------+
516 * d0i3_suspend = s0_suspend && D0I3 stream opened,
517 * D3 suspend = !d0i3_suspend,
520 static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend)
522 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
523 const struct sof_intel_dsp_desc *chip = hda->desc;
524 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
525 struct hdac_bus *bus = sof_to_bus(sdev);
529 /* disable IPC interrupts */
530 hda_dsp_ipc_int_disable(sdev);
532 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
534 hda_codec_jack_wake_enable(sdev);
536 /* power down all hda link */
537 snd_hdac_ext_bus_link_power_down_all(bus);
541 ret = hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
544 "error: failed to power down core during suspend\n");
548 /* disable ppcap interrupt */
549 hda_dsp_ctrl_ppcap_enable(sdev, false);
550 hda_dsp_ctrl_ppcap_int_enable(sdev, false);
552 /* disable hda bus irq and streams */
553 hda_dsp_ctrl_stop_chip(sdev);
555 /* disable LP retention mode */
556 snd_sof_pci_update_bits(sdev, PCI_PGCTL,
557 PCI_PGCTL_LSRMD_MASK, PCI_PGCTL_LSRMD_MASK);
559 /* reset controller */
560 ret = hda_dsp_ctrl_link_reset(sdev, true);
563 "error: failed to reset controller during suspend\n");
570 static int hda_resume(struct snd_sof_dev *sdev, bool runtime_resume)
572 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
573 struct hdac_bus *bus = sof_to_bus(sdev);
574 struct hdac_ext_link *hlink = NULL;
579 * clear TCSEL to clear playback on some HD Audio
580 * codecs. PCI TCSEL is defined in the Intel manuals.
582 snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);
584 /* reset and start hda controller */
585 ret = hda_dsp_ctrl_init_chip(sdev, true);
588 "error: failed to start controller after resume\n");
592 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
593 /* check jack status */
595 hda_codec_jack_check(sdev);
597 /* turn off the links that were off before suspend */
598 list_for_each_entry(hlink, &bus->hlink_list, list) {
599 if (!hlink->ref_count)
600 snd_hdac_ext_bus_link_power_down(hlink);
603 /* check dma status and clean up CORB/RIRB buffers */
604 if (!bus->cmd_dma_state)
605 snd_hdac_bus_stop_cmd_io(bus);
608 /* enable ppcap interrupt */
609 hda_dsp_ctrl_ppcap_enable(sdev, true);
610 hda_dsp_ctrl_ppcap_int_enable(sdev, true);
615 int hda_dsp_resume(struct snd_sof_dev *sdev)
617 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
618 struct pci_dev *pci = to_pci_dev(sdev->dev);
619 const struct sof_dsp_power_state target_state = {
620 .state = SOF_DSP_PM_D0,
621 .substate = SOF_HDA_DSP_PM_D0I0,
625 /* resume from D0I3 */
626 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0) {
627 /* Set DSP power state */
628 ret = hda_dsp_set_power_state(sdev, &target_state);
630 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
631 target_state.state, target_state.substate);
635 /* restore L1SEN bit */
636 if (hda->l1_support_changed)
637 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
639 HDA_VS_INTEL_EM2_L1SEN, 0);
641 /* restore and disable the system wakeup */
642 pci_restore_state(pci);
643 disable_irq_wake(pci->irq);
647 /* init hda controller. DSP cores will be powered up during fw boot */
648 ret = hda_resume(sdev, false);
652 hda_dsp_set_power_state(sdev, &target_state);
656 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev)
658 const struct sof_dsp_power_state target_state = {
659 .state = SOF_DSP_PM_D0,
663 /* init hda controller. DSP cores will be powered up during fw boot */
664 ret = hda_resume(sdev, true);
668 return hda_dsp_set_power_state(sdev, &target_state);
671 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev)
673 struct hdac_bus *hbus = sof_to_bus(sdev);
675 if (hbus->codec_powered) {
676 dev_dbg(sdev->dev, "some codecs still powered (%08X), not idle\n",
677 (unsigned int)hbus->codec_powered);
684 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev)
686 const struct sof_dsp_power_state target_state = {
687 .state = SOF_DSP_PM_D3,
691 /* stop hda controller and power dsp off */
692 ret = hda_suspend(sdev, true);
696 return hda_dsp_set_power_state(sdev, &target_state);
699 int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
701 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
702 struct hdac_bus *bus = sof_to_bus(sdev);
703 struct pci_dev *pci = to_pci_dev(sdev->dev);
704 const struct sof_dsp_power_state target_dsp_state = {
705 .state = target_state,
706 .substate = target_state == SOF_DSP_PM_D0 ?
707 SOF_HDA_DSP_PM_D0I3 : 0,
711 if (target_state == SOF_DSP_PM_D0) {
712 /* Set DSP power state */
713 ret = hda_dsp_set_power_state(sdev, &target_dsp_state);
715 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
716 target_dsp_state.state,
717 target_dsp_state.substate);
721 /* enable L1SEN to make sure the system can enter S0Ix */
722 hda->l1_support_changed =
723 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
725 HDA_VS_INTEL_EM2_L1SEN,
726 HDA_VS_INTEL_EM2_L1SEN);
728 /* enable the system waking up via IPC IRQ */
729 enable_irq_wake(pci->irq);
734 /* stop hda controller and power dsp off */
735 ret = hda_suspend(sdev, false);
737 dev_err(bus->dev, "error: suspending dsp\n");
741 return hda_dsp_set_power_state(sdev, &target_dsp_state);
744 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev)
746 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
747 struct hdac_bus *bus = sof_to_bus(sdev);
748 struct snd_soc_pcm_runtime *rtd;
749 struct hdac_ext_stream *stream;
750 struct hdac_ext_link *link;
751 struct hdac_stream *s;
755 /* set internal flag for BE */
756 list_for_each_entry(s, &bus->stream_list, list) {
757 stream = stream_to_hdac_ext_stream(s);
760 * clear stream. This should already be taken care for running
761 * streams when the SUSPEND trigger is called. But paused
762 * streams do not get suspended, so this needs to be done
763 * explicitly during suspend.
765 if (stream->link_substream) {
766 rtd = snd_pcm_substream_chip(stream->link_substream);
767 name = rtd->codec_dai->component->name;
768 link = snd_hdac_ext_bus_get_link(bus, name);
772 stream->link_prepared = 0;
774 if (hdac_stream(stream)->direction ==
775 SNDRV_PCM_STREAM_CAPTURE)
778 stream_tag = hdac_stream(stream)->stream_tag;
779 snd_hdac_ext_link_clear_stream_id(link, stream_tag);