1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
6 // Copyright(c) 2018 Intel Corporation. All rights reserved.
8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
10 // Rander Wang <rander.wang@intel.com>
11 // Keyon Jie <yang.jie@linux.intel.com>
15 * Hardware interface for generic Intel audio DSP HDA IP
18 #include <linux/module.h>
19 #include <sound/hdaudio_ext.h>
20 #include <sound/hda_register.h>
21 #include "../sof-audio.h"
26 static bool hda_enable_trace_D0I3_S0;
27 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG)
28 module_param_named(enable_trace_D0I3_S0, hda_enable_trace_D0I3_S0, bool, 0444);
29 MODULE_PARM_DESC(enable_trace_D0I3_S0,
30 "SOF HDA enable trace when the DSP is in D0I3 in S0");
37 int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, unsigned int core_mask)
43 /* set reset bits for cores */
44 reset = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
45 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
49 /* poll with timeout to check if operation successful */
50 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
51 HDA_DSP_REG_ADSPCS, adspcs,
52 ((adspcs & reset) == reset),
53 HDA_DSP_REG_POLL_INTERVAL_US,
54 HDA_DSP_RESET_TIMEOUT_US);
57 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
62 /* has core entered reset ? */
63 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
65 if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) !=
66 HDA_DSP_ADSPCS_CRST_MASK(core_mask)) {
68 "error: reset enter failed: core_mask %x adspcs 0x%x\n",
76 int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, unsigned int core_mask)
82 /* clear reset bits for cores */
83 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
85 HDA_DSP_ADSPCS_CRST_MASK(core_mask),
88 /* poll with timeout to check if operation successful */
89 crst = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
90 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
91 HDA_DSP_REG_ADSPCS, adspcs,
93 HDA_DSP_REG_POLL_INTERVAL_US,
94 HDA_DSP_RESET_TIMEOUT_US);
98 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
103 /* has core left reset ? */
104 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
106 if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) != 0) {
108 "error: reset leave failed: core_mask %x adspcs 0x%x\n",
116 int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask)
119 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
121 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
122 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
124 /* set reset state */
125 return hda_dsp_core_reset_enter(sdev, core_mask);
128 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask)
132 /* leave reset state */
133 ret = hda_dsp_core_reset_leave(sdev, core_mask);
138 dev_dbg(sdev->dev, "unstall/run core: core_mask = %x\n", core_mask);
139 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
141 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
144 /* is core now running ? */
145 if (!hda_dsp_core_is_enabled(sdev, core_mask)) {
146 hda_dsp_core_stall_reset(sdev, core_mask);
147 dev_err(sdev->dev, "error: DSP start core failed: core_mask %x\n",
159 int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask)
166 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS,
167 HDA_DSP_ADSPCS_SPA_MASK(core_mask),
168 HDA_DSP_ADSPCS_SPA_MASK(core_mask));
170 /* poll with timeout to check if operation successful */
171 cpa = HDA_DSP_ADSPCS_CPA_MASK(core_mask);
172 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
173 HDA_DSP_REG_ADSPCS, adspcs,
174 (adspcs & cpa) == cpa,
175 HDA_DSP_REG_POLL_INTERVAL_US,
176 HDA_DSP_RESET_TIMEOUT_US);
179 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
184 /* did core power up ? */
185 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
187 if ((adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) !=
188 HDA_DSP_ADSPCS_CPA_MASK(core_mask)) {
190 "error: power up core failed core_mask %xadspcs 0x%x\n",
198 int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask)
204 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
206 HDA_DSP_ADSPCS_SPA_MASK(core_mask), 0);
208 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
209 HDA_DSP_REG_ADSPCS, adspcs,
210 !(adspcs & HDA_DSP_ADSPCS_SPA_MASK(core_mask)),
211 HDA_DSP_REG_POLL_INTERVAL_US,
212 HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC);
215 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
221 bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev,
222 unsigned int core_mask)
227 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS);
229 is_enable = ((val & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) &&
230 (val & HDA_DSP_ADSPCS_SPA_MASK(core_mask)) &&
231 !(val & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) &&
232 !(val & HDA_DSP_ADSPCS_CSTALL_MASK(core_mask)));
234 dev_dbg(sdev->dev, "DSP core(s) enabled? %d : core_mask %x\n",
235 is_enable, core_mask);
240 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask)
244 /* return if core is already enabled */
245 if (hda_dsp_core_is_enabled(sdev, core_mask))
249 ret = hda_dsp_core_power_up(sdev, core_mask);
251 dev_err(sdev->dev, "error: dsp core power up failed: core_mask %x\n",
256 return hda_dsp_core_run(sdev, core_mask);
259 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
260 unsigned int core_mask)
264 /* place core in reset prior to power down */
265 ret = hda_dsp_core_stall_reset(sdev, core_mask);
267 dev_err(sdev->dev, "error: dsp core reset failed: core_mask %x\n",
272 /* power down core */
273 ret = hda_dsp_core_power_down(sdev, core_mask);
275 dev_err(sdev->dev, "error: dsp core power down fail mask %x: %d\n",
280 /* make sure we are in OFF state */
281 if (hda_dsp_core_is_enabled(sdev, core_mask)) {
282 dev_err(sdev->dev, "error: dsp core disable fail mask %x: %d\n",
290 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev)
292 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
293 const struct sof_intel_dsp_desc *chip = hda->desc;
295 /* enable IPC DONE and BUSY interrupts */
296 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
297 HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY,
298 HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY);
300 /* enable IPC interrupt */
301 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
302 HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC);
305 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev)
307 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
308 const struct sof_intel_dsp_desc *chip = hda->desc;
310 /* disable IPC interrupt */
311 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
312 HDA_DSP_ADSPIC_IPC, 0);
314 /* disable IPC BUSY and DONE interrupt */
315 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
316 HDA_DSP_REG_HIPCCTL_BUSY | HDA_DSP_REG_HIPCCTL_DONE, 0);
319 static int hda_dsp_wait_d0i3c_done(struct snd_sof_dev *sdev)
321 struct hdac_bus *bus = sof_to_bus(sdev);
322 int retry = HDA_DSP_REG_POLL_RETRY_COUNT;
324 while (snd_hdac_chip_readb(bus, VS_D0I3C) & SOF_HDA_VS_D0I3C_CIP) {
327 usleep_range(10, 15);
333 static int hda_dsp_send_pm_gate_ipc(struct snd_sof_dev *sdev, u32 flags)
335 struct sof_ipc_pm_gate pm_gate;
336 struct sof_ipc_reply reply;
338 memset(&pm_gate, 0, sizeof(pm_gate));
340 /* configure pm_gate ipc message */
341 pm_gate.hdr.size = sizeof(pm_gate);
342 pm_gate.hdr.cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE;
343 pm_gate.flags = flags;
345 /* send pm_gate ipc to dsp */
346 return sof_ipc_tx_message_no_pm(sdev->ipc, pm_gate.hdr.cmd,
347 &pm_gate, sizeof(pm_gate), &reply,
351 static int hda_dsp_update_d0i3c_register(struct snd_sof_dev *sdev, u8 value)
353 struct hdac_bus *bus = sof_to_bus(sdev);
356 /* Write to D0I3C after Command-In-Progress bit is cleared */
357 ret = hda_dsp_wait_d0i3c_done(sdev);
359 dev_err(bus->dev, "CIP timeout before D0I3C update!\n");
363 /* Update D0I3C register */
364 snd_hdac_chip_updateb(bus, VS_D0I3C, SOF_HDA_VS_D0I3C_I3, value);
366 /* Wait for cmd in progress to be cleared before exiting the function */
367 ret = hda_dsp_wait_d0i3c_done(sdev);
369 dev_err(bus->dev, "CIP timeout after D0I3C update!\n");
373 dev_vdbg(bus->dev, "D0I3C updated, register = 0x%x\n",
374 snd_hdac_chip_readb(bus, VS_D0I3C));
379 static int hda_dsp_set_D0_state(struct snd_sof_dev *sdev,
380 const struct sof_dsp_power_state *target_state)
387 * Sanity check for illegal state transitions
388 * The only allowed transitions are:
393 switch (sdev->dsp_power_state.state) {
395 /* Follow the sequence below for D0 substate transitions */
398 /* Follow regular flow for D3 -> D0 transition */
401 dev_err(sdev->dev, "error: transition from %d to %d not allowed\n",
402 sdev->dsp_power_state.state, target_state->state);
406 /* Set flags and register value for D0 target substate */
407 if (target_state->substate == SOF_HDA_DSP_PM_D0I3) {
408 value = SOF_HDA_VS_D0I3C_I3;
411 * Trace DMA is disabled by default when the DSP enters D0I3.
412 * But it can be kept enabled when the DSP enters D0I3 while the
413 * system is in S0 for debug.
415 if (hda_enable_trace_D0I3_S0 &&
416 sdev->system_suspend_target != SOF_SUSPEND_NONE)
417 flags = HDA_PM_NO_DMA_TRACE;
419 /* prevent power gating in D0I0 */
423 /* update D0I3C register */
424 ret = hda_dsp_update_d0i3c_register(sdev, value);
429 * Notify the DSP of the state change.
430 * If this IPC fails, revert the D0I3C register update in order
431 * to prevent partial state change.
433 ret = hda_dsp_send_pm_gate_ipc(sdev, flags);
436 "error: PM_GATE ipc error %d\n", ret);
443 /* fallback to the previous register value */
444 value = value ? 0 : SOF_HDA_VS_D0I3C_I3;
447 * This can fail but return the IPC error to signal that
448 * the state change failed.
450 hda_dsp_update_d0i3c_register(sdev, value);
456 * All DSP power state transitions are initiated by the driver.
457 * If the requested state change fails, the error is simply returned.
458 * Further state transitions are attempted only when the set_power_save() op
459 * is called again either because of a new IPC sent to the DSP or
460 * during system suspend/resume.
462 int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
463 const struct sof_dsp_power_state *target_state)
468 * When the DSP is already in D0I3 and the target state is D0I3,
469 * it could be the case that the DSP is in D0I3 during S0
470 * and the system is suspending to S0Ix. Therefore,
471 * hda_dsp_set_D0_state() must be called to disable trace DMA
472 * by sending the PM_GATE IPC to the FW.
474 if (target_state->substate == SOF_HDA_DSP_PM_D0I3 &&
475 sdev->system_suspend_target == SOF_SUSPEND_S0IX)
479 * For all other cases, return without doing anything if
480 * the DSP is already in the target state.
482 if (target_state->state == sdev->dsp_power_state.state &&
483 target_state->substate == sdev->dsp_power_state.substate)
487 switch (target_state->state) {
489 ret = hda_dsp_set_D0_state(sdev, target_state);
492 /* The only allowed transition is: D0I0 -> D3 */
493 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0 &&
494 sdev->dsp_power_state.substate == SOF_HDA_DSP_PM_D0I0)
498 "error: transition from %d to %d not allowed\n",
499 sdev->dsp_power_state.state, target_state->state);
502 dev_err(sdev->dev, "error: target state unsupported %d\n",
503 target_state->state);
508 "failed to set requested target DSP state %d substate %d\n",
509 target_state->state, target_state->substate);
513 sdev->dsp_power_state = *target_state;
514 dev_dbg(sdev->dev, "New DSP state %d substate %d\n",
515 target_state->state, target_state->substate);
520 * Audio DSP states may transform as below:-
522 * Opportunistic D0I3 in S0
523 * Runtime +---------------------+ Delayed D0i3 work timeout
524 * suspend | +--------------------+
525 * +------------+ D0I0(active) | |
526 * | | <---------------+ |
527 * | +--------> | New IPC | |
528 * | |Runtime +--^--+---------^--+--+ (via mailbox) | |
529 * | |resume | | | | | |
531 * | | System| | | | | |
532 * | | resume| | S3/S0IX | | | |
533 * | | | | suspend | | S0IX | |
534 * | | | | | |suspend | |
537 * +-v---+-----------+--v-------+ | | +------+----v----+
538 * | | | +-----------> |
539 * | D3 (suspended) | | | D0I3 |
540 * | | +--------------+ |
541 * | | System resume | |
542 * +----------------------------+ +----------------+
544 * S0IX suspend: The DSP is in D0I3 if any D0I3-compatible streams
545 * ignored the suspend trigger. Otherwise the DSP
549 static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend)
551 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
552 const struct sof_intel_dsp_desc *chip = hda->desc;
553 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
554 struct hdac_bus *bus = sof_to_bus(sdev);
558 /* disable IPC interrupts */
559 hda_dsp_ipc_int_disable(sdev);
561 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
563 hda_codec_jack_wake_enable(sdev);
565 /* power down all hda link */
566 snd_hdac_ext_bus_link_power_down_all(bus);
570 ret = hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
573 "error: failed to power down core during suspend\n");
577 /* disable ppcap interrupt */
578 hda_dsp_ctrl_ppcap_enable(sdev, false);
579 hda_dsp_ctrl_ppcap_int_enable(sdev, false);
581 /* disable hda bus irq and streams */
582 hda_dsp_ctrl_stop_chip(sdev);
584 /* disable LP retention mode */
585 snd_sof_pci_update_bits(sdev, PCI_PGCTL,
586 PCI_PGCTL_LSRMD_MASK, PCI_PGCTL_LSRMD_MASK);
588 /* reset controller */
589 ret = hda_dsp_ctrl_link_reset(sdev, true);
592 "error: failed to reset controller during suspend\n");
599 static int hda_resume(struct snd_sof_dev *sdev, bool runtime_resume)
601 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
602 struct hdac_bus *bus = sof_to_bus(sdev);
603 struct hdac_ext_link *hlink = NULL;
608 * clear TCSEL to clear playback on some HD Audio
609 * codecs. PCI TCSEL is defined in the Intel manuals.
611 snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);
613 /* reset and start hda controller */
614 ret = hda_dsp_ctrl_init_chip(sdev, true);
617 "error: failed to start controller after resume\n");
621 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
622 /* check jack status */
624 hda_codec_jack_check(sdev);
626 /* turn off the links that were off before suspend */
627 list_for_each_entry(hlink, &bus->hlink_list, list) {
628 if (!hlink->ref_count)
629 snd_hdac_ext_bus_link_power_down(hlink);
632 /* check dma status and clean up CORB/RIRB buffers */
633 if (!bus->cmd_dma_state)
634 snd_hdac_bus_stop_cmd_io(bus);
637 /* enable ppcap interrupt */
638 hda_dsp_ctrl_ppcap_enable(sdev, true);
639 hda_dsp_ctrl_ppcap_int_enable(sdev, true);
644 int hda_dsp_resume(struct snd_sof_dev *sdev)
646 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
647 struct pci_dev *pci = to_pci_dev(sdev->dev);
648 const struct sof_dsp_power_state target_state = {
649 .state = SOF_DSP_PM_D0,
650 .substate = SOF_HDA_DSP_PM_D0I0,
654 /* resume from D0I3 */
655 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0) {
656 /* Set DSP power state */
657 ret = hda_dsp_set_power_state(sdev, &target_state);
659 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
660 target_state.state, target_state.substate);
664 /* restore L1SEN bit */
665 if (hda->l1_support_changed)
666 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
668 HDA_VS_INTEL_EM2_L1SEN, 0);
670 /* restore and disable the system wakeup */
671 pci_restore_state(pci);
672 disable_irq_wake(pci->irq);
676 /* init hda controller. DSP cores will be powered up during fw boot */
677 ret = hda_resume(sdev, false);
681 hda_dsp_set_power_state(sdev, &target_state);
685 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev)
687 const struct sof_dsp_power_state target_state = {
688 .state = SOF_DSP_PM_D0,
692 /* init hda controller. DSP cores will be powered up during fw boot */
693 ret = hda_resume(sdev, true);
697 return hda_dsp_set_power_state(sdev, &target_state);
700 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev)
702 struct hdac_bus *hbus = sof_to_bus(sdev);
704 if (hbus->codec_powered) {
705 dev_dbg(sdev->dev, "some codecs still powered (%08X), not idle\n",
706 (unsigned int)hbus->codec_powered);
713 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev)
715 const struct sof_dsp_power_state target_state = {
716 .state = SOF_DSP_PM_D3,
720 /* stop hda controller and power dsp off */
721 ret = hda_suspend(sdev, true);
725 return hda_dsp_set_power_state(sdev, &target_state);
728 int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
730 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
731 struct hdac_bus *bus = sof_to_bus(sdev);
732 struct pci_dev *pci = to_pci_dev(sdev->dev);
733 const struct sof_dsp_power_state target_dsp_state = {
734 .state = target_state,
735 .substate = target_state == SOF_DSP_PM_D0 ?
736 SOF_HDA_DSP_PM_D0I3 : 0,
740 /* cancel any attempt for DSP D0I3 */
741 cancel_delayed_work_sync(&hda->d0i3_work);
743 if (target_state == SOF_DSP_PM_D0) {
744 /* Set DSP power state */
745 ret = hda_dsp_set_power_state(sdev, &target_dsp_state);
747 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
748 target_dsp_state.state,
749 target_dsp_state.substate);
753 /* enable L1SEN to make sure the system can enter S0Ix */
754 hda->l1_support_changed =
755 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
757 HDA_VS_INTEL_EM2_L1SEN,
758 HDA_VS_INTEL_EM2_L1SEN);
760 /* enable the system waking up via IPC IRQ */
761 enable_irq_wake(pci->irq);
766 /* stop hda controller and power dsp off */
767 ret = hda_suspend(sdev, false);
769 dev_err(bus->dev, "error: suspending dsp\n");
773 return hda_dsp_set_power_state(sdev, &target_dsp_state);
776 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev)
778 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
779 struct hdac_bus *bus = sof_to_bus(sdev);
780 struct snd_soc_pcm_runtime *rtd;
781 struct hdac_ext_stream *stream;
782 struct hdac_ext_link *link;
783 struct hdac_stream *s;
787 /* set internal flag for BE */
788 list_for_each_entry(s, &bus->stream_list, list) {
789 stream = stream_to_hdac_ext_stream(s);
792 * clear stream. This should already be taken care for running
793 * streams when the SUSPEND trigger is called. But paused
794 * streams do not get suspended, so this needs to be done
795 * explicitly during suspend.
797 if (stream->link_substream) {
798 rtd = snd_pcm_substream_chip(stream->link_substream);
799 name = rtd->codec_dai->component->name;
800 link = snd_hdac_ext_bus_get_link(bus, name);
804 stream->link_prepared = 0;
806 if (hdac_stream(stream)->direction ==
807 SNDRV_PCM_STREAM_CAPTURE)
810 stream_tag = hdac_stream(stream)->stream_tag;
811 snd_hdac_ext_link_clear_stream_id(link, stream_tag);
818 void hda_dsp_d0i3_work(struct work_struct *work)
820 struct sof_intel_hda_dev *hdev = container_of(work,
821 struct sof_intel_hda_dev,
823 struct hdac_bus *bus = &hdev->hbus.core;
824 struct snd_sof_dev *sdev = dev_get_drvdata(bus->dev);
825 struct sof_dsp_power_state target_state;
828 target_state.state = SOF_DSP_PM_D0;
830 /* DSP can enter D0I3 iff only D0I3-compatible streams are active */
831 if (snd_sof_dsp_only_d0i3_compatible_stream_active(sdev))
832 target_state.substate = SOF_HDA_DSP_PM_D0I3;
834 target_state.substate = SOF_HDA_DSP_PM_D0I0;
837 if (target_state.substate == SOF_HDA_DSP_PM_D0I0)
840 /* This can fail but error cannot be propagated */
841 ret = hda_dsp_set_power_state(sdev, &target_state);
843 dev_err_ratelimited(sdev->dev,
844 "error: failed to set DSP state %d substate %d\n",
845 target_state.state, target_state.substate);