1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
6 // Copyright(c) 2018 Intel Corporation. All rights reserved.
8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
10 // Rander Wang <rander.wang@intel.com>
11 // Keyon Jie <yang.jie@linux.intel.com>
15 * Hardware interface for generic Intel audio DSP HDA IP
18 #include <linux/module.h>
19 #include <sound/hdaudio_ext.h>
20 #include <sound/hda_register.h>
21 #include "../sof-audio.h"
26 static bool hda_enable_trace_D0I3_S0;
27 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG)
28 module_param_named(enable_trace_D0I3_S0, hda_enable_trace_D0I3_S0, bool, 0444);
29 MODULE_PARM_DESC(enable_trace_D0I3_S0,
30 "SOF HDA enable trace when the DSP is in D0I3 in S0");
37 static int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, unsigned int core_mask)
43 /* set reset bits for cores */
44 reset = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
45 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
49 /* poll with timeout to check if operation successful */
50 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
51 HDA_DSP_REG_ADSPCS, adspcs,
52 ((adspcs & reset) == reset),
53 HDA_DSP_REG_POLL_INTERVAL_US,
54 HDA_DSP_RESET_TIMEOUT_US);
57 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
62 /* has core entered reset ? */
63 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
65 if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) !=
66 HDA_DSP_ADSPCS_CRST_MASK(core_mask)) {
68 "error: reset enter failed: core_mask %x adspcs 0x%x\n",
76 static int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, unsigned int core_mask)
82 /* clear reset bits for cores */
83 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
85 HDA_DSP_ADSPCS_CRST_MASK(core_mask),
88 /* poll with timeout to check if operation successful */
89 crst = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
90 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
91 HDA_DSP_REG_ADSPCS, adspcs,
93 HDA_DSP_REG_POLL_INTERVAL_US,
94 HDA_DSP_RESET_TIMEOUT_US);
98 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
103 /* has core left reset ? */
104 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
106 if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) != 0) {
108 "error: reset leave failed: core_mask %x adspcs 0x%x\n",
116 static int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask)
119 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
121 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
122 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
124 /* set reset state */
125 return hda_dsp_core_reset_enter(sdev, core_mask);
128 static bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, unsigned int core_mask)
133 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS);
135 #define MASK_IS_EQUAL(v, m, field) ({ \
140 is_enable = MASK_IS_EQUAL(val, core_mask, HDA_DSP_ADSPCS_CPA_MASK) &&
141 MASK_IS_EQUAL(val, core_mask, HDA_DSP_ADSPCS_SPA_MASK) &&
142 !(val & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) &&
143 !(val & HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
147 dev_dbg(sdev->dev, "DSP core(s) enabled? %d : core_mask %x\n",
148 is_enable, core_mask);
153 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask)
157 /* leave reset state */
158 ret = hda_dsp_core_reset_leave(sdev, core_mask);
163 dev_dbg(sdev->dev, "unstall/run core: core_mask = %x\n", core_mask);
164 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
166 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
169 /* is core now running ? */
170 if (!hda_dsp_core_is_enabled(sdev, core_mask)) {
171 hda_dsp_core_stall_reset(sdev, core_mask);
172 dev_err(sdev->dev, "error: DSP start core failed: core_mask %x\n",
184 static int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask)
191 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS,
192 HDA_DSP_ADSPCS_SPA_MASK(core_mask),
193 HDA_DSP_ADSPCS_SPA_MASK(core_mask));
195 /* poll with timeout to check if operation successful */
196 cpa = HDA_DSP_ADSPCS_CPA_MASK(core_mask);
197 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
198 HDA_DSP_REG_ADSPCS, adspcs,
199 (adspcs & cpa) == cpa,
200 HDA_DSP_REG_POLL_INTERVAL_US,
201 HDA_DSP_RESET_TIMEOUT_US);
204 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
209 /* did core power up ? */
210 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
212 if ((adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) !=
213 HDA_DSP_ADSPCS_CPA_MASK(core_mask)) {
215 "error: power up core failed core_mask %xadspcs 0x%x\n",
223 static int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask)
229 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
231 HDA_DSP_ADSPCS_SPA_MASK(core_mask), 0);
233 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
234 HDA_DSP_REG_ADSPCS, adspcs,
235 !(adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)),
236 HDA_DSP_REG_POLL_INTERVAL_US,
237 HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC);
240 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
246 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask)
248 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
249 const struct sof_intel_dsp_desc *chip = hda->desc;
252 /* restrict core_mask to host managed cores mask */
253 core_mask &= chip->host_managed_cores_mask;
255 /* return if core_mask is not valid or cores are already enabled */
256 if (!core_mask || hda_dsp_core_is_enabled(sdev, core_mask))
260 ret = hda_dsp_core_power_up(sdev, core_mask);
262 dev_err(sdev->dev, "error: dsp core power up failed: core_mask %x\n",
267 return hda_dsp_core_run(sdev, core_mask);
270 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
271 unsigned int core_mask)
273 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
274 const struct sof_intel_dsp_desc *chip = hda->desc;
277 /* restrict core_mask to host managed cores mask */
278 core_mask &= chip->host_managed_cores_mask;
280 /* return if core_mask is not valid */
284 /* place core in reset prior to power down */
285 ret = hda_dsp_core_stall_reset(sdev, core_mask);
287 dev_err(sdev->dev, "error: dsp core reset failed: core_mask %x\n",
292 /* power down core */
293 ret = hda_dsp_core_power_down(sdev, core_mask);
295 dev_err(sdev->dev, "error: dsp core power down fail mask %x: %d\n",
300 /* make sure we are in OFF state */
301 if (hda_dsp_core_is_enabled(sdev, core_mask)) {
302 dev_err(sdev->dev, "error: dsp core disable fail mask %x: %d\n",
310 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev)
312 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
313 const struct sof_intel_dsp_desc *chip = hda->desc;
315 /* enable IPC DONE and BUSY interrupts */
316 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
317 HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY,
318 HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY);
320 /* enable IPC interrupt */
321 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
322 HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC);
325 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev)
327 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
328 const struct sof_intel_dsp_desc *chip = hda->desc;
330 /* disable IPC interrupt */
331 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
332 HDA_DSP_ADSPIC_IPC, 0);
334 /* disable IPC BUSY and DONE interrupt */
335 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
336 HDA_DSP_REG_HIPCCTL_BUSY | HDA_DSP_REG_HIPCCTL_DONE, 0);
339 static int hda_dsp_wait_d0i3c_done(struct snd_sof_dev *sdev)
341 struct hdac_bus *bus = sof_to_bus(sdev);
342 int retry = HDA_DSP_REG_POLL_RETRY_COUNT;
344 while (snd_hdac_chip_readb(bus, VS_D0I3C) & SOF_HDA_VS_D0I3C_CIP) {
347 usleep_range(10, 15);
353 static int hda_dsp_send_pm_gate_ipc(struct snd_sof_dev *sdev, u32 flags)
355 struct sof_ipc_pm_gate pm_gate;
356 struct sof_ipc_reply reply;
358 memset(&pm_gate, 0, sizeof(pm_gate));
360 /* configure pm_gate ipc message */
361 pm_gate.hdr.size = sizeof(pm_gate);
362 pm_gate.hdr.cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE;
363 pm_gate.flags = flags;
365 /* send pm_gate ipc to dsp */
366 return sof_ipc_tx_message_no_pm(sdev->ipc, pm_gate.hdr.cmd,
367 &pm_gate, sizeof(pm_gate), &reply,
371 static int hda_dsp_update_d0i3c_register(struct snd_sof_dev *sdev, u8 value)
373 struct hdac_bus *bus = sof_to_bus(sdev);
376 /* Write to D0I3C after Command-In-Progress bit is cleared */
377 ret = hda_dsp_wait_d0i3c_done(sdev);
379 dev_err(bus->dev, "CIP timeout before D0I3C update!\n");
383 /* Update D0I3C register */
384 snd_hdac_chip_updateb(bus, VS_D0I3C, SOF_HDA_VS_D0I3C_I3, value);
386 /* Wait for cmd in progress to be cleared before exiting the function */
387 ret = hda_dsp_wait_d0i3c_done(sdev);
389 dev_err(bus->dev, "CIP timeout after D0I3C update!\n");
393 dev_vdbg(bus->dev, "D0I3C updated, register = 0x%x\n",
394 snd_hdac_chip_readb(bus, VS_D0I3C));
399 static int hda_dsp_set_D0_state(struct snd_sof_dev *sdev,
400 const struct sof_dsp_power_state *target_state)
407 * Sanity check for illegal state transitions
408 * The only allowed transitions are:
413 switch (sdev->dsp_power_state.state) {
415 /* Follow the sequence below for D0 substate transitions */
418 /* Follow regular flow for D3 -> D0 transition */
421 dev_err(sdev->dev, "error: transition from %d to %d not allowed\n",
422 sdev->dsp_power_state.state, target_state->state);
426 /* Set flags and register value for D0 target substate */
427 if (target_state->substate == SOF_HDA_DSP_PM_D0I3) {
428 value = SOF_HDA_VS_D0I3C_I3;
431 * Trace DMA need to be disabled when the DSP enters
432 * D0I3 for S0Ix suspend, but it can be kept enabled
433 * when the DSP enters D0I3 while the system is in S0
436 if (!sdev->dtrace_is_supported ||
437 !hda_enable_trace_D0I3_S0 ||
438 sdev->system_suspend_target != SOF_SUSPEND_NONE)
439 flags = HDA_PM_NO_DMA_TRACE;
441 /* prevent power gating in D0I0 */
445 /* update D0I3C register */
446 ret = hda_dsp_update_d0i3c_register(sdev, value);
451 * Notify the DSP of the state change.
452 * If this IPC fails, revert the D0I3C register update in order
453 * to prevent partial state change.
455 ret = hda_dsp_send_pm_gate_ipc(sdev, flags);
458 "error: PM_GATE ipc error %d\n", ret);
465 /* fallback to the previous register value */
466 value = value ? 0 : SOF_HDA_VS_D0I3C_I3;
469 * This can fail but return the IPC error to signal that
470 * the state change failed.
472 hda_dsp_update_d0i3c_register(sdev, value);
477 /* helper to log DSP state */
478 static void hda_dsp_state_log(struct snd_sof_dev *sdev)
480 switch (sdev->dsp_power_state.state) {
482 switch (sdev->dsp_power_state.substate) {
483 case SOF_HDA_DSP_PM_D0I0:
484 dev_dbg(sdev->dev, "Current DSP power state: D0I0\n");
486 case SOF_HDA_DSP_PM_D0I3:
487 dev_dbg(sdev->dev, "Current DSP power state: D0I3\n");
490 dev_dbg(sdev->dev, "Unknown DSP D0 substate: %d\n",
491 sdev->dsp_power_state.substate);
496 dev_dbg(sdev->dev, "Current DSP power state: D1\n");
499 dev_dbg(sdev->dev, "Current DSP power state: D2\n");
501 case SOF_DSP_PM_D3_HOT:
502 dev_dbg(sdev->dev, "Current DSP power state: D3_HOT\n");
505 dev_dbg(sdev->dev, "Current DSP power state: D3\n");
507 case SOF_DSP_PM_D3_COLD:
508 dev_dbg(sdev->dev, "Current DSP power state: D3_COLD\n");
511 dev_dbg(sdev->dev, "Unknown DSP power state: %d\n",
512 sdev->dsp_power_state.state);
518 * All DSP power state transitions are initiated by the driver.
519 * If the requested state change fails, the error is simply returned.
520 * Further state transitions are attempted only when the set_power_save() op
521 * is called again either because of a new IPC sent to the DSP or
522 * during system suspend/resume.
524 int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
525 const struct sof_dsp_power_state *target_state)
530 * When the DSP is already in D0I3 and the target state is D0I3,
531 * it could be the case that the DSP is in D0I3 during S0
532 * and the system is suspending to S0Ix. Therefore,
533 * hda_dsp_set_D0_state() must be called to disable trace DMA
534 * by sending the PM_GATE IPC to the FW.
536 if (target_state->substate == SOF_HDA_DSP_PM_D0I3 &&
537 sdev->system_suspend_target == SOF_SUSPEND_S0IX)
541 * For all other cases, return without doing anything if
542 * the DSP is already in the target state.
544 if (target_state->state == sdev->dsp_power_state.state &&
545 target_state->substate == sdev->dsp_power_state.substate)
549 switch (target_state->state) {
551 ret = hda_dsp_set_D0_state(sdev, target_state);
554 /* The only allowed transition is: D0I0 -> D3 */
555 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0 &&
556 sdev->dsp_power_state.substate == SOF_HDA_DSP_PM_D0I0)
560 "error: transition from %d to %d not allowed\n",
561 sdev->dsp_power_state.state, target_state->state);
564 dev_err(sdev->dev, "error: target state unsupported %d\n",
565 target_state->state);
570 "failed to set requested target DSP state %d substate %d\n",
571 target_state->state, target_state->substate);
575 sdev->dsp_power_state = *target_state;
576 hda_dsp_state_log(sdev);
581 * Audio DSP states may transform as below:-
583 * Opportunistic D0I3 in S0
584 * Runtime +---------------------+ Delayed D0i3 work timeout
585 * suspend | +--------------------+
586 * +------------+ D0I0(active) | |
587 * | | <---------------+ |
588 * | +--------> | New IPC | |
589 * | |Runtime +--^--+---------^--+--+ (via mailbox) | |
590 * | |resume | | | | | |
592 * | | System| | | | | |
593 * | | resume| | S3/S0IX | | | |
594 * | | | | suspend | | S0IX | |
595 * | | | | | |suspend | |
598 * +-v---+-----------+--v-------+ | | +------+----v----+
599 * | | | +-----------> |
600 * | D3 (suspended) | | | D0I3 |
601 * | | +--------------+ |
602 * | | System resume | |
603 * +----------------------------+ +----------------+
605 * S0IX suspend: The DSP is in D0I3 if any D0I3-compatible streams
606 * ignored the suspend trigger. Otherwise the DSP
610 static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend)
612 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
613 const struct sof_intel_dsp_desc *chip = hda->desc;
614 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
615 struct hdac_bus *bus = sof_to_bus(sdev);
619 hda_sdw_int_enable(sdev, false);
621 /* disable IPC interrupts */
622 hda_dsp_ipc_int_disable(sdev);
624 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
626 hda_codec_jack_wake_enable(sdev, true);
628 /* power down all hda link */
629 snd_hdac_ext_bus_link_power_down_all(bus);
633 ret = snd_sof_dsp_core_power_down(sdev, chip->host_managed_cores_mask);
636 "error: failed to power down core during suspend\n");
640 /* disable ppcap interrupt */
641 hda_dsp_ctrl_ppcap_enable(sdev, false);
642 hda_dsp_ctrl_ppcap_int_enable(sdev, false);
644 /* disable hda bus irq and streams */
645 hda_dsp_ctrl_stop_chip(sdev);
647 /* disable LP retention mode */
648 snd_sof_pci_update_bits(sdev, PCI_PGCTL,
649 PCI_PGCTL_LSRMD_MASK, PCI_PGCTL_LSRMD_MASK);
651 /* reset controller */
652 ret = hda_dsp_ctrl_link_reset(sdev, true);
655 "error: failed to reset controller during suspend\n");
659 /* display codec can powered off after link reset */
660 hda_codec_i915_display_power(sdev, false);
665 static int hda_resume(struct snd_sof_dev *sdev, bool runtime_resume)
667 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
668 struct hdac_bus *bus = sof_to_bus(sdev);
669 struct hdac_ext_link *hlink = NULL;
673 /* display codec must be powered before link reset */
674 hda_codec_i915_display_power(sdev, true);
677 * clear TCSEL to clear playback on some HD Audio
678 * codecs. PCI TCSEL is defined in the Intel manuals.
680 snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);
682 /* reset and start hda controller */
683 ret = hda_dsp_ctrl_init_chip(sdev, true);
686 "error: failed to start controller after resume\n");
690 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
691 /* check jack status */
692 if (runtime_resume) {
693 hda_codec_jack_wake_enable(sdev, false);
694 if (sdev->system_suspend_target == SOF_SUSPEND_NONE)
695 hda_codec_jack_check(sdev);
698 /* turn off the links that were off before suspend */
699 list_for_each_entry(hlink, &bus->hlink_list, list) {
700 if (!hlink->ref_count)
701 snd_hdac_ext_bus_link_power_down(hlink);
704 /* check dma status and clean up CORB/RIRB buffers */
705 if (!bus->cmd_dma_state)
706 snd_hdac_bus_stop_cmd_io(bus);
709 /* enable ppcap interrupt */
710 hda_dsp_ctrl_ppcap_enable(sdev, true);
711 hda_dsp_ctrl_ppcap_int_enable(sdev, true);
714 /* display codec can powered off after controller init */
715 hda_codec_i915_display_power(sdev, false);
720 int hda_dsp_resume(struct snd_sof_dev *sdev)
722 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
723 struct pci_dev *pci = to_pci_dev(sdev->dev);
724 const struct sof_dsp_power_state target_state = {
725 .state = SOF_DSP_PM_D0,
726 .substate = SOF_HDA_DSP_PM_D0I0,
728 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
729 struct hdac_bus *bus = sof_to_bus(sdev);
730 struct hdac_ext_link *hlink = NULL;
734 /* resume from D0I3 */
735 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0) {
736 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
737 /* power up links that were active before suspend */
738 list_for_each_entry(hlink, &bus->hlink_list, list) {
739 if (hlink->ref_count) {
740 ret = snd_hdac_ext_bus_link_power_up(hlink);
743 "error %d in %s: failed to power up links",
750 /* set up CORB/RIRB buffers if was on before suspend */
751 if (bus->cmd_dma_state)
752 snd_hdac_bus_init_cmd_io(bus);
755 /* Set DSP power state */
756 ret = snd_sof_dsp_set_power_state(sdev, &target_state);
758 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
759 target_state.state, target_state.substate);
763 /* restore L1SEN bit */
764 if (hda->l1_support_changed)
765 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
767 HDA_VS_INTEL_EM2_L1SEN, 0);
769 /* restore and disable the system wakeup */
770 pci_restore_state(pci);
771 disable_irq_wake(pci->irq);
775 /* init hda controller. DSP cores will be powered up during fw boot */
776 ret = hda_resume(sdev, false);
780 return snd_sof_dsp_set_power_state(sdev, &target_state);
783 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev)
785 const struct sof_dsp_power_state target_state = {
786 .state = SOF_DSP_PM_D0,
790 /* init hda controller. DSP cores will be powered up during fw boot */
791 ret = hda_resume(sdev, true);
795 return snd_sof_dsp_set_power_state(sdev, &target_state);
798 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev)
800 struct hdac_bus *hbus = sof_to_bus(sdev);
802 if (hbus->codec_powered) {
803 dev_dbg(sdev->dev, "some codecs still powered (%08X), not idle\n",
804 (unsigned int)hbus->codec_powered);
811 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev)
813 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
814 const struct sof_dsp_power_state target_state = {
815 .state = SOF_DSP_PM_D3,
819 /* cancel any attempt for DSP D0I3 */
820 cancel_delayed_work_sync(&hda->d0i3_work);
822 /* stop hda controller and power dsp off */
823 ret = hda_suspend(sdev, true);
827 return snd_sof_dsp_set_power_state(sdev, &target_state);
830 int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
832 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
833 struct hdac_bus *bus = sof_to_bus(sdev);
834 struct pci_dev *pci = to_pci_dev(sdev->dev);
835 const struct sof_dsp_power_state target_dsp_state = {
836 .state = target_state,
837 .substate = target_state == SOF_DSP_PM_D0 ?
838 SOF_HDA_DSP_PM_D0I3 : 0,
842 /* cancel any attempt for DSP D0I3 */
843 cancel_delayed_work_sync(&hda->d0i3_work);
845 if (target_state == SOF_DSP_PM_D0) {
846 /* Set DSP power state */
847 ret = snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
849 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
850 target_dsp_state.state,
851 target_dsp_state.substate);
855 /* enable L1SEN to make sure the system can enter S0Ix */
856 hda->l1_support_changed =
857 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
859 HDA_VS_INTEL_EM2_L1SEN,
860 HDA_VS_INTEL_EM2_L1SEN);
862 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
863 /* stop the CORB/RIRB DMA if it is On */
864 if (bus->cmd_dma_state)
865 snd_hdac_bus_stop_cmd_io(bus);
867 /* no link can be powered in s0ix state */
868 ret = snd_hdac_ext_bus_link_power_down_all(bus);
871 "error %d in %s: failed to power down links",
877 /* enable the system waking up via IPC IRQ */
878 enable_irq_wake(pci->irq);
883 /* stop hda controller and power dsp off */
884 ret = hda_suspend(sdev, false);
886 dev_err(bus->dev, "error: suspending dsp\n");
890 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
893 int hda_dsp_shutdown(struct snd_sof_dev *sdev)
895 sdev->system_suspend_target = SOF_SUSPEND_S3;
896 return snd_sof_suspend(sdev->dev);
899 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev)
901 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
902 struct hdac_bus *bus = sof_to_bus(sdev);
903 struct snd_soc_pcm_runtime *rtd;
904 struct hdac_ext_stream *stream;
905 struct hdac_ext_link *link;
906 struct hdac_stream *s;
910 /* set internal flag for BE */
911 list_for_each_entry(s, &bus->stream_list, list) {
912 stream = stream_to_hdac_ext_stream(s);
915 * clear stream. This should already be taken care for running
916 * streams when the SUSPEND trigger is called. But paused
917 * streams do not get suspended, so this needs to be done
918 * explicitly during suspend.
920 if (stream->link_substream) {
921 rtd = asoc_substream_to_rtd(stream->link_substream);
922 name = asoc_rtd_to_codec(rtd, 0)->component->name;
923 link = snd_hdac_ext_bus_get_link(bus, name);
927 stream->link_prepared = 0;
929 if (hdac_stream(stream)->direction ==
930 SNDRV_PCM_STREAM_CAPTURE)
933 stream_tag = hdac_stream(stream)->stream_tag;
934 snd_hdac_ext_link_clear_stream_id(link, stream_tag);
941 void hda_dsp_d0i3_work(struct work_struct *work)
943 struct sof_intel_hda_dev *hdev = container_of(work,
944 struct sof_intel_hda_dev,
946 struct hdac_bus *bus = &hdev->hbus.core;
947 struct snd_sof_dev *sdev = dev_get_drvdata(bus->dev);
948 struct sof_dsp_power_state target_state = {
949 .state = SOF_DSP_PM_D0,
950 .substate = SOF_HDA_DSP_PM_D0I3,
954 /* DSP can enter D0I3 iff only D0I3-compatible streams are active */
955 if (!snd_sof_dsp_only_d0i3_compatible_stream_active(sdev))
959 /* This can fail but error cannot be propagated */
960 ret = snd_sof_dsp_set_power_state(sdev, &target_state);
962 dev_err_ratelimited(sdev->dev,
963 "error: failed to set DSP state %d substate %d\n",
964 target_state.state, target_state.substate);