1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
6 // Copyright(c) 2018 Intel Corporation. All rights reserved.
8 // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
12 * Hardware interface for audio DSP on Baytrail, Braswell and Cherrytrail.
15 #include <linux/module.h>
16 #include <sound/sof.h>
17 #include <sound/sof/xtensa.h>
20 #include "../sof-audio.h"
21 #include "../../intel/common/soc-intel-quirks.h"
24 #define IRAM_OFFSET 0x0C0000
25 #define IRAM_SIZE (80 * 1024)
26 #define DRAM_OFFSET 0x100000
27 #define DRAM_SIZE (160 * 1024)
28 #define SHIM_OFFSET 0x140000
29 #define SHIM_SIZE_BYT 0x100
30 #define SHIM_SIZE_CHT 0x118
31 #define MBOX_OFFSET 0x144000
32 #define MBOX_SIZE 0x1000
33 #define EXCEPT_OFFSET 0x800
34 #define EXCEPT_MAX_HDR_SIZE 0x400
37 #define DMAC0_OFFSET 0x098000
38 #define DMAC1_OFFSET 0x09c000
39 #define DMAC2_OFFSET 0x094000
40 #define DMAC_SIZE 0x420
41 #define SSP0_OFFSET 0x0a0000
42 #define SSP1_OFFSET 0x0a1000
43 #define SSP2_OFFSET 0x0a2000
44 #define SSP3_OFFSET 0x0a4000
45 #define SSP4_OFFSET 0x0a5000
46 #define SSP5_OFFSET 0x0a6000
47 #define SSP_SIZE 0x100
49 #define BYT_STACK_DUMP_SIZE 32
51 #define BYT_PCI_BAR_SIZE 0x200000
53 #define BYT_PANIC_OFFSET(x) (((x) & GENMASK_ULL(47, 32)) >> 32)
59 #define MBOX_DUMP_SIZE 0x30
66 static const struct snd_sof_debugfs_map byt_debugfs[] = {
67 {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
68 SOF_DEBUGFS_ACCESS_ALWAYS},
69 {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
70 SOF_DEBUGFS_ACCESS_ALWAYS},
71 {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE,
72 SOF_DEBUGFS_ACCESS_ALWAYS},
73 {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE,
74 SOF_DEBUGFS_ACCESS_ALWAYS},
75 {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE,
76 SOF_DEBUGFS_ACCESS_ALWAYS},
77 {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
78 SOF_DEBUGFS_ACCESS_D0_ONLY},
79 {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
80 SOF_DEBUGFS_ACCESS_D0_ONLY},
81 {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT,
82 SOF_DEBUGFS_ACCESS_ALWAYS},
85 static const struct snd_sof_debugfs_map cht_debugfs[] = {
86 {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
87 SOF_DEBUGFS_ACCESS_ALWAYS},
88 {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
89 SOF_DEBUGFS_ACCESS_ALWAYS},
90 {"dmac2", BYT_DSP_BAR, DMAC2_OFFSET, DMAC_SIZE,
91 SOF_DEBUGFS_ACCESS_ALWAYS},
92 {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE,
93 SOF_DEBUGFS_ACCESS_ALWAYS},
94 {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE,
95 SOF_DEBUGFS_ACCESS_ALWAYS},
96 {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE,
97 SOF_DEBUGFS_ACCESS_ALWAYS},
98 {"ssp3", BYT_DSP_BAR, SSP3_OFFSET, SSP_SIZE,
99 SOF_DEBUGFS_ACCESS_ALWAYS},
100 {"ssp4", BYT_DSP_BAR, SSP4_OFFSET, SSP_SIZE,
101 SOF_DEBUGFS_ACCESS_ALWAYS},
102 {"ssp5", BYT_DSP_BAR, SSP5_OFFSET, SSP_SIZE,
103 SOF_DEBUGFS_ACCESS_ALWAYS},
104 {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
105 SOF_DEBUGFS_ACCESS_D0_ONLY},
106 {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
107 SOF_DEBUGFS_ACCESS_D0_ONLY},
108 {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE_CHT,
109 SOF_DEBUGFS_ACCESS_ALWAYS},
112 static void byt_host_done(struct snd_sof_dev *sdev);
113 static void byt_dsp_done(struct snd_sof_dev *sdev);
114 static void byt_get_reply(struct snd_sof_dev *sdev);
120 static void byt_get_registers(struct snd_sof_dev *sdev,
121 struct sof_ipc_dsp_oops_xtensa *xoops,
122 struct sof_ipc_panic_info *panic_info,
123 u32 *stack, size_t stack_words)
125 u32 offset = sdev->dsp_oops_offset;
127 /* first read regsisters */
128 sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));
130 /* note: variable AR register array is not read */
132 /* then get panic info */
133 if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) {
134 dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n",
135 xoops->arch_hdr.totalsize);
138 offset += xoops->arch_hdr.totalsize;
139 sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info));
141 /* then get the stack */
142 offset += sizeof(*panic_info);
143 sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32));
146 static void byt_dump(struct snd_sof_dev *sdev, u32 flags)
148 struct sof_ipc_dsp_oops_xtensa xoops;
149 struct sof_ipc_panic_info panic_info;
150 u32 stack[BYT_STACK_DUMP_SIZE];
151 u64 status, panic, imrd, imrx;
153 /* now try generic SOF status messages */
154 status = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD);
155 panic = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX);
156 byt_get_registers(sdev, &xoops, &panic_info, stack,
157 BYT_STACK_DUMP_SIZE);
158 snd_sof_get_status(sdev, status, panic, &xoops, &panic_info, stack,
159 BYT_STACK_DUMP_SIZE);
161 /* provide some context for firmware debug */
162 imrx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRX);
163 imrd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRD);
165 "error: ipc host -> DSP: pending %s complete %s raw 0x%llx\n",
166 (panic & SHIM_IPCX_BUSY) ? "yes" : "no",
167 (panic & SHIM_IPCX_DONE) ? "yes" : "no", panic);
169 "error: mask host: pending %s complete %s raw 0x%llx\n",
170 (imrx & SHIM_IMRX_BUSY) ? "yes" : "no",
171 (imrx & SHIM_IMRX_DONE) ? "yes" : "no", imrx);
173 "error: ipc DSP -> host: pending %s complete %s raw 0x%llx\n",
174 (status & SHIM_IPCD_BUSY) ? "yes" : "no",
175 (status & SHIM_IPCD_DONE) ? "yes" : "no", status);
177 "error: mask DSP: pending %s complete %s raw 0x%llx\n",
178 (imrd & SHIM_IMRD_BUSY) ? "yes" : "no",
179 (imrd & SHIM_IMRD_DONE) ? "yes" : "no", imrd);
184 * IPC Doorbell IRQ handler and thread.
187 static irqreturn_t byt_irq_handler(int irq, void *context)
189 struct snd_sof_dev *sdev = context;
193 /* Interrupt arrived, check src */
194 isr = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_ISRX);
195 if (isr & (SHIM_ISRX_DONE | SHIM_ISRX_BUSY))
196 ret = IRQ_WAKE_THREAD;
201 static irqreturn_t byt_irq_thread(int irq, void *context)
203 struct snd_sof_dev *sdev = context;
207 imrx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRX);
208 ipcx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX);
210 /* reply message from DSP */
211 if (ipcx & SHIM_BYT_IPCX_DONE &&
212 !(imrx & SHIM_IMRX_DONE)) {
213 /* Mask Done interrupt before first */
214 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR,
219 spin_lock_irq(&sdev->ipc_lock);
222 * handle immediate reply from DSP core. If the msg is
223 * found, set done bit in cmd_done which is called at the
224 * end of message processing function, else set it here
225 * because the done bit can't be set in cmd_done function
226 * which is triggered by msg
229 snd_sof_ipc_reply(sdev, ipcx);
233 spin_unlock_irq(&sdev->ipc_lock);
236 /* new message from DSP */
237 ipcd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD);
238 if (ipcd & SHIM_BYT_IPCD_BUSY &&
239 !(imrx & SHIM_IMRX_BUSY)) {
240 /* Mask Busy interrupt before return */
241 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR,
246 /* Handle messages from DSP Core */
247 if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
248 snd_sof_dsp_panic(sdev, BYT_PANIC_OFFSET(ipcd) +
251 snd_sof_ipc_msgs_rx(sdev);
260 static int byt_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
262 /* send the message */
263 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
265 snd_sof_dsp_write64(sdev, BYT_DSP_BAR, SHIM_IPCX, SHIM_BYT_IPCX_BUSY);
270 static void byt_get_reply(struct snd_sof_dev *sdev)
272 struct snd_sof_ipc_msg *msg = sdev->msg;
273 struct sof_ipc_reply reply;
277 * Sometimes, there is unexpected reply ipc arriving. The reply
278 * ipc belongs to none of the ipcs sent from driver.
279 * In this case, the driver must ignore the ipc.
282 dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n");
287 sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply));
289 if (reply.error < 0) {
290 memcpy(msg->reply_data, &reply, sizeof(reply));
293 /* reply correct size ? */
294 if (reply.hdr.size != msg->reply_size) {
295 dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n",
296 msg->reply_size, reply.hdr.size);
300 /* read the message */
301 if (msg->reply_size > 0)
302 sof_mailbox_read(sdev, sdev->host_box.offset,
303 msg->reply_data, msg->reply_size);
306 msg->reply_error = ret;
309 static int byt_get_mailbox_offset(struct snd_sof_dev *sdev)
314 static int byt_get_window_offset(struct snd_sof_dev *sdev, u32 id)
319 static void byt_host_done(struct snd_sof_dev *sdev)
321 /* clear BUSY bit and set DONE bit - accept new messages */
322 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCD,
327 /* unmask busy interrupt */
328 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX,
332 static void byt_dsp_done(struct snd_sof_dev *sdev)
334 /* clear DONE bit - tell DSP we have completed */
335 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCX,
336 SHIM_BYT_IPCX_DONE, 0);
338 /* unmask Done interrupt */
339 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX,
347 static int byt_run(struct snd_sof_dev *sdev)
351 /* release stall and wait to unstall */
352 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR,
353 SHIM_BYT_CSR_STALL, 0x0);
355 if (!(snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_CSR) &
356 SHIM_BYT_CSR_PWAITMODE))
361 dev_err(sdev->dev, "error: unable to run DSP firmware\n");
362 byt_dump(sdev, SOF_DBG_REGS | SOF_DBG_MBOX);
366 /* return init core mask */
370 static int byt_reset(struct snd_sof_dev *sdev)
372 /* put DSP into reset, set reset vector and stall */
373 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR,
374 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL |
376 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL |
379 usleep_range(10, 15);
381 /* take DSP out of reset and keep stalled for FW loading */
382 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR,
383 SHIM_BYT_CSR_RST, 0);
388 static const char *fixup_tplg_name(struct snd_sof_dev *sdev,
389 const char *sof_tplg_filename,
392 const char *tplg_filename = NULL;
396 filename = devm_kstrdup(sdev->dev, sof_tplg_filename, GFP_KERNEL);
400 /* this assumes a .tplg extension */
401 split_ext = strsep(&filename, ".");
403 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL,
409 return tplg_filename;
412 static void byt_machine_select(struct snd_sof_dev *sdev)
414 struct snd_sof_pdata *sof_pdata = sdev->pdata;
415 const struct sof_dev_desc *desc = sof_pdata->desc;
416 struct snd_soc_acpi_mach *mach;
417 struct platform_device *pdev;
418 const char *tplg_filename;
420 mach = snd_soc_acpi_find_machine(desc->machines);
422 dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n");
426 pdev = to_platform_device(sdev->dev);
427 if (soc_intel_is_byt_cr(pdev)) {
429 "BYT-CR detected, SSP0 used instead of SSP2\n");
431 tplg_filename = fixup_tplg_name(sdev,
432 mach->sof_tplg_filename,
435 tplg_filename = mach->sof_tplg_filename;
438 if (!tplg_filename) {
440 "error: no topology filename\n");
444 sof_pdata->tplg_filename = tplg_filename;
445 mach->mach_params.acpi_ipc_irq_index = desc->irqindex_host_ipc;
446 sof_pdata->machine = mach;
449 static void byt_set_mach_params(const struct snd_soc_acpi_mach *mach,
452 struct snd_soc_acpi_mach_params *mach_params;
454 mach_params = (struct snd_soc_acpi_mach_params *)&mach->mach_params;
455 mach_params->platform = dev_name(dev);
459 static struct snd_soc_dai_driver byt_dai[] = {
484 #if IS_ENABLED(CONFIG_SND_SOC_SOF_MERRIFIELD)
486 static int tangier_pci_probe(struct snd_sof_dev *sdev)
488 struct snd_sof_pdata *pdata = sdev->pdata;
489 const struct sof_dev_desc *desc = pdata->desc;
490 struct pci_dev *pci = to_pci_dev(sdev->dev);
494 /* DSP DMA can only access low 31 bits of host memory */
495 ret = dma_coerce_mask_and_coherent(&pci->dev, DMA_BIT_MASK(31));
497 dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
502 base = pci_resource_start(pci, desc->resindex_lpe_base) - IRAM_OFFSET;
503 size = BYT_PCI_BAR_SIZE;
505 dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
506 sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size);
507 if (!sdev->bar[BYT_DSP_BAR]) {
508 dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n",
512 dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]);
514 /* IMR base - optional */
515 if (desc->resindex_imr_base == -1)
518 base = pci_resource_start(pci, desc->resindex_imr_base);
519 size = pci_resource_len(pci, desc->resindex_imr_base);
521 /* some BIOSes don't map IMR */
522 if (base == 0x55aa55aa || base == 0x0) {
523 dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n");
527 dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size);
528 sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size);
529 if (!sdev->bar[BYT_IMR_BAR]) {
530 dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n",
534 dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]);
537 /* register our IRQ */
538 sdev->ipc_irq = pci->irq;
539 dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
540 ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
541 byt_irq_handler, byt_irq_thread,
542 0, "AudioDSP", sdev);
544 dev_err(sdev->dev, "error: failed to register IRQ %d\n",
549 /* enable Interrupt from both sides */
550 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x0);
551 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x0);
553 /* set default mailbox offset for FW ready message */
554 sdev->dsp_box.offset = MBOX_OFFSET;
559 const struct snd_sof_dsp_ops sof_tng_ops = {
561 .probe = tangier_pci_probe,
563 /* DSP core boot / reset */
568 .write = sof_io_write,
570 .write64 = sof_io_write64,
571 .read64 = sof_io_read64,
574 .block_read = sof_block_read,
575 .block_write = sof_block_write,
578 .irq_handler = byt_irq_handler,
579 .irq_thread = byt_irq_thread,
582 .send_msg = byt_send_msg,
583 .fw_ready = sof_fw_ready,
584 .get_mailbox_offset = byt_get_mailbox_offset,
585 .get_window_offset = byt_get_window_offset,
587 .ipc_msg_data = intel_ipc_msg_data,
588 .ipc_pcm_params = intel_ipc_pcm_params,
591 .machine_select = byt_machine_select,
592 .machine_register = sof_machine_register,
593 .machine_unregister = sof_machine_unregister,
594 .set_mach_params = byt_set_mach_params,
597 .debug_map = byt_debugfs,
598 .debug_map_count = ARRAY_SIZE(byt_debugfs),
599 .dbg_dump = byt_dump,
601 /* stream callbacks */
602 .pcm_open = intel_pcm_open,
603 .pcm_close = intel_pcm_close,
606 .load_module = snd_sof_parse_module_memcpy,
608 /*Firmware loading */
609 .load_firmware = snd_sof_load_firmware_memcpy,
613 .num_drv = 3, /* we have only 3 SSPs on byt*/
615 /* ALSA HW info flags */
616 .hw_info = SNDRV_PCM_INFO_MMAP |
617 SNDRV_PCM_INFO_MMAP_VALID |
618 SNDRV_PCM_INFO_INTERLEAVED |
619 SNDRV_PCM_INFO_PAUSE |
620 SNDRV_PCM_INFO_BATCH,
622 .arch_ops = &sof_xtensa_arch_ops,
624 EXPORT_SYMBOL_NS(sof_tng_ops, SND_SOC_SOF_MERRIFIELD);
626 const struct sof_intel_dsp_desc tng_chip_info = {
630 EXPORT_SYMBOL_NS(tng_chip_info, SND_SOC_SOF_MERRIFIELD);
632 #endif /* CONFIG_SND_SOC_SOF_MERRIFIELD */
634 #if IS_ENABLED(CONFIG_SND_SOC_SOF_BAYTRAIL)
636 static int byt_acpi_probe(struct snd_sof_dev *sdev)
638 struct snd_sof_pdata *pdata = sdev->pdata;
639 const struct sof_dev_desc *desc = pdata->desc;
640 struct platform_device *pdev =
641 container_of(sdev->dev, struct platform_device, dev);
642 struct resource *mmio;
646 /* DSP DMA can only access low 31 bits of host memory */
647 ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31));
649 dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
654 mmio = platform_get_resource(pdev, IORESOURCE_MEM,
655 desc->resindex_lpe_base);
658 size = resource_size(mmio);
660 dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n",
661 desc->resindex_lpe_base);
665 dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
666 sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size);
667 if (!sdev->bar[BYT_DSP_BAR]) {
668 dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n",
672 dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]);
674 /* TODO: add offsets */
675 sdev->mmio_bar = BYT_DSP_BAR;
676 sdev->mailbox_bar = BYT_DSP_BAR;
678 /* IMR base - optional */
679 if (desc->resindex_imr_base == -1)
682 mmio = platform_get_resource(pdev, IORESOURCE_MEM,
683 desc->resindex_imr_base);
686 size = resource_size(mmio);
688 dev_err(sdev->dev, "error: failed to get IMR base at idx %d\n",
689 desc->resindex_imr_base);
693 /* some BIOSes don't map IMR */
694 if (base == 0x55aa55aa || base == 0x0) {
695 dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n");
699 dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size);
700 sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size);
701 if (!sdev->bar[BYT_IMR_BAR]) {
702 dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n",
706 dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]);
709 /* register our IRQ */
710 sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc);
711 if (sdev->ipc_irq < 0)
712 return sdev->ipc_irq;
714 dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
715 ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
716 byt_irq_handler, byt_irq_thread,
717 IRQF_SHARED, "AudioDSP", sdev);
719 dev_err(sdev->dev, "error: failed to register IRQ %d\n",
724 /* enable Interrupt from both sides */
725 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x0);
726 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x0);
728 /* set default mailbox offset for FW ready message */
729 sdev->dsp_box.offset = MBOX_OFFSET;
735 const struct snd_sof_dsp_ops sof_byt_ops = {
737 .probe = byt_acpi_probe,
739 /* DSP core boot / reset */
744 .write = sof_io_write,
746 .write64 = sof_io_write64,
747 .read64 = sof_io_read64,
750 .block_read = sof_block_read,
751 .block_write = sof_block_write,
754 .irq_handler = byt_irq_handler,
755 .irq_thread = byt_irq_thread,
758 .send_msg = byt_send_msg,
759 .fw_ready = sof_fw_ready,
760 .get_mailbox_offset = byt_get_mailbox_offset,
761 .get_window_offset = byt_get_window_offset,
763 .ipc_msg_data = intel_ipc_msg_data,
764 .ipc_pcm_params = intel_ipc_pcm_params,
767 .machine_select = byt_machine_select,
768 .machine_register = sof_machine_register,
769 .machine_unregister = sof_machine_unregister,
770 .set_mach_params = byt_set_mach_params,
773 .debug_map = byt_debugfs,
774 .debug_map_count = ARRAY_SIZE(byt_debugfs),
775 .dbg_dump = byt_dump,
777 /* stream callbacks */
778 .pcm_open = intel_pcm_open,
779 .pcm_close = intel_pcm_close,
782 .load_module = snd_sof_parse_module_memcpy,
784 /*Firmware loading */
785 .load_firmware = snd_sof_load_firmware_memcpy,
789 .num_drv = 3, /* we have only 3 SSPs on byt*/
791 /* ALSA HW info flags */
792 .hw_info = SNDRV_PCM_INFO_MMAP |
793 SNDRV_PCM_INFO_MMAP_VALID |
794 SNDRV_PCM_INFO_INTERLEAVED |
795 SNDRV_PCM_INFO_PAUSE |
796 SNDRV_PCM_INFO_BATCH,
798 .arch_ops = &sof_xtensa_arch_ops,
800 EXPORT_SYMBOL_NS(sof_byt_ops, SND_SOC_SOF_BAYTRAIL);
802 const struct sof_intel_dsp_desc byt_chip_info = {
806 EXPORT_SYMBOL_NS(byt_chip_info, SND_SOC_SOF_BAYTRAIL);
808 /* cherrytrail and braswell ops */
809 const struct snd_sof_dsp_ops sof_cht_ops = {
811 .probe = byt_acpi_probe,
813 /* DSP core boot / reset */
818 .write = sof_io_write,
820 .write64 = sof_io_write64,
821 .read64 = sof_io_read64,
824 .block_read = sof_block_read,
825 .block_write = sof_block_write,
828 .irq_handler = byt_irq_handler,
829 .irq_thread = byt_irq_thread,
832 .send_msg = byt_send_msg,
833 .fw_ready = sof_fw_ready,
834 .get_mailbox_offset = byt_get_mailbox_offset,
835 .get_window_offset = byt_get_window_offset,
837 .ipc_msg_data = intel_ipc_msg_data,
838 .ipc_pcm_params = intel_ipc_pcm_params,
841 .machine_select = byt_machine_select,
842 .machine_register = sof_machine_register,
843 .machine_unregister = sof_machine_unregister,
844 .set_mach_params = byt_set_mach_params,
847 .debug_map = cht_debugfs,
848 .debug_map_count = ARRAY_SIZE(cht_debugfs),
849 .dbg_dump = byt_dump,
851 /* stream callbacks */
852 .pcm_open = intel_pcm_open,
853 .pcm_close = intel_pcm_close,
856 .load_module = snd_sof_parse_module_memcpy,
858 /*Firmware loading */
859 .load_firmware = snd_sof_load_firmware_memcpy,
863 /* all 6 SSPs may be available for cherrytrail */
864 .num_drv = ARRAY_SIZE(byt_dai),
866 /* ALSA HW info flags */
867 .hw_info = SNDRV_PCM_INFO_MMAP |
868 SNDRV_PCM_INFO_MMAP_VALID |
869 SNDRV_PCM_INFO_INTERLEAVED |
870 SNDRV_PCM_INFO_PAUSE |
871 SNDRV_PCM_INFO_BATCH,
873 .arch_ops = &sof_xtensa_arch_ops,
875 EXPORT_SYMBOL_NS(sof_cht_ops, SND_SOC_SOF_BAYTRAIL);
877 const struct sof_intel_dsp_desc cht_chip_info = {
881 EXPORT_SYMBOL_NS(cht_chip_info, SND_SOC_SOF_BAYTRAIL);
883 #endif /* CONFIG_SND_SOC_SOF_BAYTRAIL */
885 MODULE_LICENSE("Dual BSD/GPL");
886 MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC);
887 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);