sound/soc/sof/intel/byt.c

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
   2 //
   3 // This file is provided under a dual BSD/GPLv2 license.  When using or
   4 // redistributing this file, you may do so under either license.
   5 //
   6 // Copyright(c) 2018 Intel Corporation. All rights reserved.
   7 //
   8 // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
   9 //
  10
  11 /*
  12  * Hardware interface for audio DSP on Baytrail, Braswell and Cherrytrail.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <sound/sof.h>
  17 #include <sound/sof/xtensa.h>
  18 #include <sound/soc-acpi.h>
  19 #include <sound/soc-acpi-intel-match.h>
  20 #include <sound/intel-dsp-config.h>
  21 #include "../ops.h"
  22 #include "atom.h"
  23 #include "shim.h"
  24 #include "../sof-acpi-dev.h"
  25 #include "../sof-audio.h"
  26 #include "../../intel/common/soc-intel-quirks.h"
  27
  28 static const struct snd_sof_debugfs_map byt_debugfs[] = {
  29         {"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
  30          SOF_DEBUGFS_ACCESS_ALWAYS},
  31         {"dmac1", DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
  32          SOF_DEBUGFS_ACCESS_ALWAYS},
  33         {"ssp0", DSP_BAR, SSP0_OFFSET, SSP_SIZE,
  34          SOF_DEBUGFS_ACCESS_ALWAYS},
  35         {"ssp1", DSP_BAR, SSP1_OFFSET, SSP_SIZE,
  36          SOF_DEBUGFS_ACCESS_ALWAYS},
  37         {"ssp2", DSP_BAR, SSP2_OFFSET, SSP_SIZE,
  38          SOF_DEBUGFS_ACCESS_ALWAYS},
  39         {"iram", DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
  40          SOF_DEBUGFS_ACCESS_D0_ONLY},
  41         {"dram", DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
  42          SOF_DEBUGFS_ACCESS_D0_ONLY},
  43         {"shim", DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT,
  44          SOF_DEBUGFS_ACCESS_ALWAYS},
  45 };
  46
  47 static const struct snd_sof_debugfs_map cht_debugfs[] = {
  48         {"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
  49          SOF_DEBUGFS_ACCESS_ALWAYS},
  50         {"dmac1", DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
  51          SOF_DEBUGFS_ACCESS_ALWAYS},
  52         {"dmac2", DSP_BAR, DMAC2_OFFSET, DMAC_SIZE,
  53          SOF_DEBUGFS_ACCESS_ALWAYS},
  54         {"ssp0", DSP_BAR, SSP0_OFFSET, SSP_SIZE,
  55          SOF_DEBUGFS_ACCESS_ALWAYS},
  56         {"ssp1", DSP_BAR, SSP1_OFFSET, SSP_SIZE,
  57          SOF_DEBUGFS_ACCESS_ALWAYS},
  58         {"ssp2", DSP_BAR, SSP2_OFFSET, SSP_SIZE,
  59          SOF_DEBUGFS_ACCESS_ALWAYS},
  60         {"ssp3", DSP_BAR, SSP3_OFFSET, SSP_SIZE,
  61          SOF_DEBUGFS_ACCESS_ALWAYS},
  62         {"ssp4", DSP_BAR, SSP4_OFFSET, SSP_SIZE,
  63          SOF_DEBUGFS_ACCESS_ALWAYS},
  64         {"ssp5", DSP_BAR, SSP5_OFFSET, SSP_SIZE,
  65          SOF_DEBUGFS_ACCESS_ALWAYS},
  66         {"iram", DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
  67          SOF_DEBUGFS_ACCESS_D0_ONLY},
  68         {"dram", DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
  69          SOF_DEBUGFS_ACCESS_D0_ONLY},
  70         {"shim", DSP_BAR, SHIM_OFFSET, SHIM_SIZE_CHT,
  71          SOF_DEBUGFS_ACCESS_ALWAYS},
  72 };
  73
  74 static void byt_reset_dsp_disable_int(struct snd_sof_dev *sdev)
  75 {
  76         /* Disable Interrupt from both sides */
  77         snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX, 0x3, 0x3);
  78         snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRD, 0x3, 0x3);
  79
  80         /* Put DSP into reset, set reset vector */
  81         snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_CSR,
  82                                   SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL,
  83                                   SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL);
  84 }
  85
  86 static int byt_suspend(struct snd_sof_dev *sdev, u32 target_state)
  87 {
  88         byt_reset_dsp_disable_int(sdev);
  89
  90         return 0;
  91 }
  92
  93 static int byt_resume(struct snd_sof_dev *sdev)
  94 {
  95         /* enable BUSY and disable DONE Interrupt by default */
  96         snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX,
  97                                   SHIM_IMRX_BUSY | SHIM_IMRX_DONE,
  98                                   SHIM_IMRX_DONE);
  99
 100         return 0;
 101 }
 102
 103 static int byt_remove(struct snd_sof_dev *sdev)
 104 {
 105         byt_reset_dsp_disable_int(sdev);
 106
 107         return 0;
 108 }
 109
 110 static int byt_acpi_probe(struct snd_sof_dev *sdev)
 111 {
 112         struct snd_sof_pdata *pdata = sdev->pdata;
 113         const struct sof_dev_desc *desc = pdata->desc;
 114         struct platform_device *pdev =
 115                 container_of(sdev->dev, struct platform_device, dev);
 116         struct resource *mmio;
 117         u32 base, size;
 118         int ret;
 119
 120         /* DSP DMA can only access low 31 bits of host memory */
 121         ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31));
 122         if (ret < 0) {
 123                 dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
 124                 return ret;
 125         }
 126
 127         /* LPE base */
 128         mmio = platform_get_resource(pdev, IORESOURCE_MEM,
 129                                      desc->resindex_lpe_base);
 130         if (mmio) {
 131                 base = mmio->start;
 132                 size = resource_size(mmio);
 133         } else {
 134                 dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n",
 135                         desc->resindex_lpe_base);
 136                 return -EINVAL;
 137         }
 138
 139         dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
 140         sdev->bar[DSP_BAR] = devm_ioremap(sdev->dev, base, size);
 141         if (!sdev->bar[DSP_BAR]) {
 142                 dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n",
 143                         base, size);
 144                 return -ENODEV;
 145         }
 146         dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[DSP_BAR]);
 147
 148         /* TODO: add offsets */
 149         sdev->mmio_bar = DSP_BAR;
 150         sdev->mailbox_bar = DSP_BAR;
 151
 152         /* IMR base - optional */
 153         if (desc->resindex_imr_base == -1)
 154                 goto irq;
 155
 156         mmio = platform_get_resource(pdev, IORESOURCE_MEM,
 157                                      desc->resindex_imr_base);
 158         if (mmio) {
 159                 base = mmio->start;
 160                 size = resource_size(mmio);
 161         } else {
 162                 dev_err(sdev->dev, "error: failed to get IMR base at idx %d\n",
 163                         desc->resindex_imr_base);
 164                 return -ENODEV;
 165         }
 166
 167         /* some BIOSes don't map IMR */
 168         if (base == 0x55aa55aa || base == 0x0) {
 169                 dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n");
 170                 goto irq;
 171         }
 172
 173         dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size);
 174         sdev->bar[IMR_BAR] = devm_ioremap(sdev->dev, base, size);
 175         if (!sdev->bar[IMR_BAR]) {
 176                 dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n",
 177                         base, size);
 178                 return -ENODEV;
 179         }
 180         dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[IMR_BAR]);
 181
 182 irq:
 183         /* register our IRQ */
 184         sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc);
 185         if (sdev->ipc_irq < 0)
 186                 return sdev->ipc_irq;
 187
 188         dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
 189         ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
 190                                         atom_irq_handler, atom_irq_thread,
 191                                         IRQF_SHARED, "AudioDSP", sdev);
 192         if (ret < 0) {
 193                 dev_err(sdev->dev, "error: failed to register IRQ %d\n",
 194                         sdev->ipc_irq);
 195                 return ret;
 196         }
 197
 198         /* enable BUSY and disable DONE Interrupt by default */
 199         snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX,
 200                                   SHIM_IMRX_BUSY | SHIM_IMRX_DONE,
 201                                   SHIM_IMRX_DONE);
 202
 203         /* set default mailbox offset for FW ready message */
 204         sdev->dsp_box.offset = MBOX_OFFSET;
 205
 206         return ret;
 207 }
 208
 209 /* baytrail ops */
 210 static const struct snd_sof_dsp_ops sof_byt_ops = {
 211         /* device init */
 212         .probe          = byt_acpi_probe,
 213         .remove         = byt_remove,
 214
 215         /* DSP core boot / reset */
 216         .run            = atom_run,
 217         .reset          = atom_reset,
 218
 219         /* Register IO */
 220         .write          = sof_io_write,
 221         .read           = sof_io_read,
 222         .write64        = sof_io_write64,
 223         .read64         = sof_io_read64,
 224
 225         /* Block IO */
 226         .block_read     = sof_block_read,
 227         .block_write    = sof_block_write,
 228
 229         /* doorbell */
 230         .irq_handler    = atom_irq_handler,
 231         .irq_thread     = atom_irq_thread,
 232
 233         /* ipc */
 234         .send_msg       = atom_send_msg,
 235         .fw_ready       = sof_fw_ready,
 236         .get_mailbox_offset = atom_get_mailbox_offset,
 237         .get_window_offset = atom_get_window_offset,
 238
 239         .ipc_msg_data   = intel_ipc_msg_data,
 240         .ipc_pcm_params = intel_ipc_pcm_params,
 241
 242         /* machine driver */
 243         .machine_select = atom_machine_select,
 244         .machine_register = sof_machine_register,
 245         .machine_unregister = sof_machine_unregister,
 246         .set_mach_params = atom_set_mach_params,
 247
 248         /* debug */
 249         .debug_map      = byt_debugfs,
 250         .debug_map_count        = ARRAY_SIZE(byt_debugfs),
 251         .dbg_dump       = atom_dump,
 252
 253         /* stream callbacks */
 254         .pcm_open       = intel_pcm_open,
 255         .pcm_close      = intel_pcm_close,
 256
 257         /* module loading */
 258         .load_module    = snd_sof_parse_module_memcpy,
 259
 260         /*Firmware loading */
 261         .load_firmware  = snd_sof_load_firmware_memcpy,
 262
 263         /* PM */
 264         .suspend = byt_suspend,
 265         .resume = byt_resume,
 266
 267         /* DAI drivers */
 268         .drv = atom_dai,
 269         .num_drv = 3, /* we have only 3 SSPs on byt*/
 270
 271         /* ALSA HW info flags */
 272         .hw_info =      SNDRV_PCM_INFO_MMAP |
 273                         SNDRV_PCM_INFO_MMAP_VALID |
 274                         SNDRV_PCM_INFO_INTERLEAVED |
 275                         SNDRV_PCM_INFO_PAUSE |
 276                         SNDRV_PCM_INFO_BATCH,
 277
 278         .arch_ops = &sof_xtensa_arch_ops,
 279 };
 280
 281 static const struct sof_intel_dsp_desc byt_chip_info = {
 282         .cores_num = 1,
 283         .host_managed_cores_mask = 1,
 284 };
 285
 286 /* cherrytrail and braswell ops */
 287 static const struct snd_sof_dsp_ops sof_cht_ops = {
 288         /* device init */
 289         .probe          = byt_acpi_probe,
 290         .remove         = byt_remove,
 291
 292         /* DSP core boot / reset */
 293         .run            = atom_run,
 294         .reset          = atom_reset,
 295
 296         /* Register IO */
 297         .write          = sof_io_write,
 298         .read           = sof_io_read,
 299         .write64        = sof_io_write64,
 300         .read64         = sof_io_read64,
 301
 302         /* Block IO */
 303         .block_read     = sof_block_read,
 304         .block_write    = sof_block_write,
 305
 306         /* doorbell */
 307         .irq_handler    = atom_irq_handler,
 308         .irq_thread     = atom_irq_thread,
 309
 310         /* ipc */
 311         .send_msg       = atom_send_msg,
 312         .fw_ready       = sof_fw_ready,
 313         .get_mailbox_offset = atom_get_mailbox_offset,
 314         .get_window_offset = atom_get_window_offset,
 315
 316         .ipc_msg_data   = intel_ipc_msg_data,
 317         .ipc_pcm_params = intel_ipc_pcm_params,
 318
 319         /* machine driver */
 320         .machine_select = atom_machine_select,
 321         .machine_register = sof_machine_register,
 322         .machine_unregister = sof_machine_unregister,
 323         .set_mach_params = atom_set_mach_params,
 324
 325         /* debug */
 326         .debug_map      = cht_debugfs,
 327         .debug_map_count        = ARRAY_SIZE(cht_debugfs),
 328         .dbg_dump       = atom_dump,
 329
 330         /* stream callbacks */
 331         .pcm_open       = intel_pcm_open,
 332         .pcm_close      = intel_pcm_close,
 333
 334         /* module loading */
 335         .load_module    = snd_sof_parse_module_memcpy,
 336
 337         /*Firmware loading */
 338         .load_firmware  = snd_sof_load_firmware_memcpy,
 339
 340         /* PM */
 341         .suspend = byt_suspend,
 342         .resume = byt_resume,
 343
 344         /* DAI drivers */
 345         .drv = atom_dai,
 346         /* all 6 SSPs may be available for cherrytrail */
 347         .num_drv = 6,
 348
 349         /* ALSA HW info flags */
 350         .hw_info =      SNDRV_PCM_INFO_MMAP |
 351                         SNDRV_PCM_INFO_MMAP_VALID |
 352                         SNDRV_PCM_INFO_INTERLEAVED |
 353                         SNDRV_PCM_INFO_PAUSE |
 354                         SNDRV_PCM_INFO_BATCH,
 355
 356         .arch_ops = &sof_xtensa_arch_ops,
 357 };
 358
 359 static const struct sof_intel_dsp_desc cht_chip_info = {
 360         .cores_num = 1,
 361         .host_managed_cores_mask = 1,
 362 };
 363
 364 /* BYTCR uses different IRQ index */
 365 static const struct sof_dev_desc sof_acpi_baytrailcr_desc = {
 366         .machines = snd_soc_acpi_intel_baytrail_machines,
 367         .resindex_lpe_base = 0,
 368         .resindex_pcicfg_base = 1,
 369         .resindex_imr_base = 2,
 370         .irqindex_host_ipc = 0,
 371         .chip_info = &byt_chip_info,
 372         .default_fw_path = "intel/sof",
 373         .default_tplg_path = "intel/sof-tplg",
 374         .default_fw_filename = "sof-byt.ri",
 375         .nocodec_tplg_filename = "sof-byt-nocodec.tplg",
 376         .ops = &sof_byt_ops,
 377 };
 378
 379 static const struct sof_dev_desc sof_acpi_baytrail_desc = {
 380         .machines = snd_soc_acpi_intel_baytrail_machines,
 381         .resindex_lpe_base = 0,
 382         .resindex_pcicfg_base = 1,
 383         .resindex_imr_base = 2,
 384         .irqindex_host_ipc = 5,
 385         .chip_info = &byt_chip_info,
 386         .default_fw_path = "intel/sof",
 387         .default_tplg_path = "intel/sof-tplg",
 388         .default_fw_filename = "sof-byt.ri",
 389         .nocodec_tplg_filename = "sof-byt-nocodec.tplg",
 390         .ops = &sof_byt_ops,
 391 };
 392
 393 static const struct sof_dev_desc sof_acpi_cherrytrail_desc = {
 394         .machines = snd_soc_acpi_intel_cherrytrail_machines,
 395         .resindex_lpe_base = 0,
 396         .resindex_pcicfg_base = 1,
 397         .resindex_imr_base = 2,
 398         .irqindex_host_ipc = 5,
 399         .chip_info = &cht_chip_info,
 400         .default_fw_path = "intel/sof",
 401         .default_tplg_path = "intel/sof-tplg",
 402         .default_fw_filename = "sof-cht.ri",
 403         .nocodec_tplg_filename = "sof-cht-nocodec.tplg",
 404         .ops = &sof_cht_ops,
 405 };
 406
 407 static const struct acpi_device_id sof_baytrail_match[] = {
 408         { "80860F28", (unsigned long)&sof_acpi_baytrail_desc },
 409         { "808622A8", (unsigned long)&sof_acpi_cherrytrail_desc },
 410         { }
 411 };
 412 MODULE_DEVICE_TABLE(acpi, sof_baytrail_match);
 413
 414 static int sof_baytrail_probe(struct platform_device *pdev)
 415 {
 416         struct device *dev = &pdev->dev;
 417         const struct sof_dev_desc *desc;
 418         const struct acpi_device_id *id;
 419         int ret;
 420
 421         id = acpi_match_device(dev->driver->acpi_match_table, dev);
 422         if (!id)
 423                 return -ENODEV;
 424
 425         ret = snd_intel_acpi_dsp_driver_probe(dev, id->id);
 426         if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_SOF) {
 427                 dev_dbg(dev, "SOF ACPI driver not selected, aborting probe\n");
 428                 return -ENODEV;
 429         }
 430
 431         desc = device_get_match_data(&pdev->dev);
 432         if (!desc)
 433                 return -ENODEV;
 434
 435         if (desc == &sof_acpi_baytrail_desc && soc_intel_is_byt_cr(pdev))
 436                 desc = &sof_acpi_baytrailcr_desc;
 437
 438         return sof_acpi_probe(pdev, desc);
 439 }
 440
 441 /* acpi_driver definition */
 442 static struct platform_driver snd_sof_acpi_intel_byt_driver = {
 443         .probe = sof_baytrail_probe,
 444         .remove = sof_acpi_remove,
 445         .driver = {
 446                 .name = "sof-audio-acpi-intel-byt",
 447                 .pm = &sof_acpi_pm,
 448                 .acpi_match_table = sof_baytrail_match,
 449         },
 450 };
 451 module_platform_driver(snd_sof_acpi_intel_byt_driver);
 452
 453 MODULE_LICENSE("Dual BSD/GPL");
 454 MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC);
 455 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
 456 MODULE_IMPORT_NS(SND_SOC_SOF_ACPI_DEV);
 457 MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_ATOM_HIFI_EP);