sound/soc/sof/intel/bdw.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
   2 //
   3 // This file is provided under a dual BSD/GPLv2 license.  When using or
   4 // redistributing this file, you may do so under either license.
   5 //
   6 // Copyright(c) 2018 Intel Corporation. All rights reserved.
   7 //
   8 // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
   9 //
  10
  11 /*
  12  * Hardware interface for audio DSP on Broadwell
  13  */
  14
  15 #include <linux/module.h>
  16 #include <sound/sof.h>
  17 #include <sound/sof/xtensa.h>
  18 #include "../ops.h"
  19 #include "shim.h"
  20
  21 /* BARs */
  22 #define BDW_DSP_BAR 0
  23 #define BDW_PCI_BAR 1
  24
  25 /*
  26  * Debug
  27  */
  28
  29 /* DSP memories for BDW */
  30 #define IRAM_OFFSET     0xA0000
  31 #define BDW_IRAM_SIZE       (10 * 32 * 1024)
  32 #define DRAM_OFFSET     0x00000
  33 #define BDW_DRAM_SIZE       (20 * 32 * 1024)
  34 #define SHIM_OFFSET     0xFB000
  35 #define SHIM_SIZE       0x100
  36 #define MBOX_OFFSET     0x9E000
  37 #define MBOX_SIZE       0x1000
  38 #define MBOX_DUMP_SIZE 0x30
  39 #define EXCEPT_OFFSET   0x800
  40
  41 /* DSP peripherals */
  42 #define DMAC0_OFFSET    0xFE000
  43 #define DMAC1_OFFSET    0xFF000
  44 #define DMAC_SIZE       0x420
  45 #define SSP0_OFFSET     0xFC000
  46 #define SSP1_OFFSET     0xFD000
  47 #define SSP_SIZE        0x100
  48
  49 #define BDW_STACK_DUMP_SIZE     32
  50
  51 #define BDW_PANIC_OFFSET(x)     ((x) & 0xFFFF)
  52
  53 static const struct snd_sof_debugfs_map bdw_debugfs[] = {
  54         {"dmac0", BDW_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
  55          SOF_DEBUGFS_ACCESS_ALWAYS},
  56         {"dmac1", BDW_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
  57          SOF_DEBUGFS_ACCESS_ALWAYS},
  58         {"ssp0", BDW_DSP_BAR, SSP0_OFFSET, SSP_SIZE,
  59          SOF_DEBUGFS_ACCESS_ALWAYS},
  60         {"ssp1", BDW_DSP_BAR, SSP1_OFFSET, SSP_SIZE,
  61          SOF_DEBUGFS_ACCESS_ALWAYS},
  62         {"iram", BDW_DSP_BAR, IRAM_OFFSET, BDW_IRAM_SIZE,
  63          SOF_DEBUGFS_ACCESS_D0_ONLY},
  64         {"dram", BDW_DSP_BAR, DRAM_OFFSET, BDW_DRAM_SIZE,
  65          SOF_DEBUGFS_ACCESS_D0_ONLY},
  66         {"shim", BDW_DSP_BAR, SHIM_OFFSET, SHIM_SIZE,
  67          SOF_DEBUGFS_ACCESS_ALWAYS},
  68 };
  69
  70 static void bdw_host_done(struct snd_sof_dev *sdev);
  71 static void bdw_dsp_done(struct snd_sof_dev *sdev);
  72 static void bdw_get_reply(struct snd_sof_dev *sdev);
  73
  74 /*
  75  * DSP Control.
  76  */
  77
  78 static int bdw_run(struct snd_sof_dev *sdev)
  79 {
  80         /* set opportunistic mode on engine 0,1 for all channels */
  81         snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_HMDC,
  82                                 SHIM_HMDC_HDDA_E0_ALLCH |
  83                                 SHIM_HMDC_HDDA_E1_ALLCH, 0);
  84
  85         /* set DSP to RUN */
  86         snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
  87                                          SHIM_CSR_STALL, 0x0);
  88
  89         /* return init core mask */
  90         return 1;
  91 }
  92
  93 static int bdw_reset(struct snd_sof_dev *sdev)
  94 {
  95         /* put DSP into reset and stall */
  96         snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
  97                                          SHIM_CSR_RST | SHIM_CSR_STALL,
  98                                          SHIM_CSR_RST | SHIM_CSR_STALL);
  99
 100         /* keep in reset for 10ms */
 101         mdelay(10);
 102
 103         /* take DSP out of reset and keep stalled for FW loading */
 104         snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
 105                                          SHIM_CSR_RST | SHIM_CSR_STALL,
 106                                          SHIM_CSR_STALL);
 107
 108         return 0;
 109 }
 110
 111 static int bdw_set_dsp_D0(struct snd_sof_dev *sdev)
 112 {
 113         int tries = 10;
 114         u32 reg;
 115
 116         /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
 117         snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2,
 118                                          PCI_VDRTCL2_DCLCGE |
 119                                          PCI_VDRTCL2_DTCGE, 0);
 120
 121         /* Disable D3PG (VDRTCTL0.D3PGD = 1) */
 122         snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL0,
 123                                          PCI_VDRTCL0_D3PGD, PCI_VDRTCL0_D3PGD);
 124
 125         /* Set D0 state */
 126         snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_PMCS,
 127                                          PCI_PMCS_PS_MASK, 0);
 128
 129         /* check that ADSP shim is enabled */
 130         while (tries--) {
 131                 reg = readl(sdev->bar[BDW_PCI_BAR] + PCI_PMCS)
 132                         & PCI_PMCS_PS_MASK;
 133                 if (reg == 0)
 134                         goto finish;
 135
 136                 msleep(20);
 137         }
 138
 139         return -ENODEV;
 140
 141 finish:
 142         /*
 143          * select SSP1 19.2MHz base clock, SSP clock 0,
 144          * turn off Low Power Clock
 145          */
 146         snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
 147                                          SHIM_CSR_S1IOCS | SHIM_CSR_SBCS1 |
 148                                          SHIM_CSR_LPCS, 0x0);
 149
 150         /* stall DSP core, set clk to 192/96Mhz */
 151         snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,
 152                                          SHIM_CSR, SHIM_CSR_STALL |
 153                                          SHIM_CSR_DCS_MASK,
 154                                          SHIM_CSR_STALL |
 155                                          SHIM_CSR_DCS(4));
 156
 157         /* Set 24MHz MCLK, prevent local clock gating, enable SSP0 clock */
 158         snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CLKCTL,
 159                                          SHIM_CLKCTL_MASK |
 160                                          SHIM_CLKCTL_DCPLCG |
 161                                          SHIM_CLKCTL_SCOE0,
 162                                          SHIM_CLKCTL_MASK |
 163                                          SHIM_CLKCTL_DCPLCG |
 164                                          SHIM_CLKCTL_SCOE0);
 165
 166         /* Stall and reset core, set CSR */
 167         bdw_reset(sdev);
 168
 169         /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
 170         snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2,
 171                                          PCI_VDRTCL2_DCLCGE |
 172                                          PCI_VDRTCL2_DTCGE,
 173                                          PCI_VDRTCL2_DCLCGE |
 174                                          PCI_VDRTCL2_DTCGE);
 175
 176         usleep_range(50, 55);
 177
 178         /* switch on audio PLL */
 179         snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2,
 180                                          PCI_VDRTCL2_APLLSE_MASK, 0);
 181
 182         /*
 183          * set default power gating control, enable power gating control for
 184          * all blocks. that is, can't be accessed, please enable each block
 185          * before accessing.
 186          */
 187         snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL0,
 188                                          0xfffffffC, 0x0);
 189
 190         /* disable DMA finish function for SSP0 & SSP1 */
 191         snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,  SHIM_CSR2,
 192                                          SHIM_CSR2_SDFD_SSP1,
 193                                          SHIM_CSR2_SDFD_SSP1);
 194
 195         /* set on-demond mode on engine 0,1 for all channels */
 196         snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_HMDC,
 197                                 SHIM_HMDC_HDDA_E0_ALLCH |
 198                                 SHIM_HMDC_HDDA_E1_ALLCH,
 199                                 SHIM_HMDC_HDDA_E0_ALLCH |
 200                                 SHIM_HMDC_HDDA_E1_ALLCH);
 201
 202         /* Enable Interrupt from both sides */
 203         snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_IMRX,
 204                                 (SHIM_IMRX_BUSY | SHIM_IMRX_DONE), 0x0);
 205         snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_IMRD,
 206                                 (SHIM_IMRD_DONE | SHIM_IMRD_BUSY |
 207                                 SHIM_IMRD_SSP0 | SHIM_IMRD_DMAC), 0x0);
 208
 209         /* clear IPC registers */
 210         snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, 0x0);
 211         snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCD, 0x0);
 212         snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0x80, 0x6);
 213         snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0xe0, 0x300a);
 214
 215         return 0;
 216 }
 217
 218 static void bdw_get_registers(struct snd_sof_dev *sdev,
 219                               struct sof_ipc_dsp_oops_xtensa *xoops,
 220                               struct sof_ipc_panic_info *panic_info,
 221                               u32 *stack, size_t stack_words)
 222 {
 223         u32 offset = sdev->dsp_oops_offset;
 224
 225         /* first read registers */
 226         sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));
 227
 228         /* note: variable AR register array is not read */
 229
 230         /* then get panic info */
 231         offset += xoops->arch_hdr.totalsize;
 232         sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info));
 233
 234         /* then get the stack */
 235         offset += sizeof(*panic_info);
 236         sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32));
 237 }
 238
 239 static void bdw_dump(struct snd_sof_dev *sdev, u32 flags)
 240 {
 241         struct sof_ipc_dsp_oops_xtensa xoops;
 242         struct sof_ipc_panic_info panic_info;
 243         u32 stack[BDW_STACK_DUMP_SIZE];
 244         u32 status, panic;
 245
 246         /* now try generic SOF status messages */
 247         status = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCD);
 248         panic = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCX);
 249         bdw_get_registers(sdev, &xoops, &panic_info, stack,
 250                           BDW_STACK_DUMP_SIZE);
 251         snd_sof_get_status(sdev, status, panic, &xoops, &panic_info, stack,
 252                            BDW_STACK_DUMP_SIZE);
 253 }
 254
 255 /*
 256  * IPC Doorbell IRQ handler and thread.
 257  */
 258
 259 static irqreturn_t bdw_irq_handler(int irq, void *context)
 260 {
 261         struct snd_sof_dev *sdev = context;
 262         u32 isr;
 263         int ret = IRQ_NONE;
 264
 265         /* Interrupt arrived, check src */
 266         isr = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_ISRX);
 267         if (isr & (SHIM_ISRX_DONE | SHIM_ISRX_BUSY))
 268                 ret = IRQ_WAKE_THREAD;
 269
 270         return ret;
 271 }
 272
 273 static irqreturn_t bdw_irq_thread(int irq, void *context)
 274 {
 275         struct snd_sof_dev *sdev = context;
 276         u32 ipcx, ipcd, imrx;
 277
 278         imrx = snd_sof_dsp_read64(sdev, BDW_DSP_BAR, SHIM_IMRX);
 279         ipcx = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCX);
 280
 281         /* reply message from DSP */
 282         if (ipcx & SHIM_IPCX_DONE &&
 283             !(imrx & SHIM_IMRX_DONE)) {
 284                 /* Mask Done interrupt before return */
 285                 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,
 286                                                  SHIM_IMRX, SHIM_IMRX_DONE,
 287                                                  SHIM_IMRX_DONE);
 288
 289                 spin_lock_irq(&sdev->ipc_lock);
 290
 291                 /*
 292                  * handle immediate reply from DSP core. If the msg is
 293                  * found, set done bit in cmd_done which is called at the
 294                  * end of message processing function, else set it here
 295                  * because the done bit can't be set in cmd_done function
 296                  * which is triggered by msg
 297                  */
 298                 bdw_get_reply(sdev);
 299                 snd_sof_ipc_reply(sdev, ipcx);
 300
 301                 bdw_dsp_done(sdev);
 302
 303                 spin_unlock_irq(&sdev->ipc_lock);
 304         }
 305
 306         ipcd = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCD);
 307
 308         /* new message from DSP */
 309         if (ipcd & SHIM_IPCD_BUSY &&
 310             !(imrx & SHIM_IMRX_BUSY)) {
 311                 /* Mask Busy interrupt before return */
 312                 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,
 313                                                  SHIM_IMRX, SHIM_IMRX_BUSY,
 314                                                  SHIM_IMRX_BUSY);
 315
 316                 /* Handle messages from DSP Core */
 317                 if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
 318                         snd_sof_dsp_panic(sdev, BDW_PANIC_OFFSET(ipcx) +
 319                                           MBOX_OFFSET);
 320                 } else {
 321                         snd_sof_ipc_msgs_rx(sdev);
 322                 }
 323
 324                 bdw_host_done(sdev);
 325         }
 326
 327         return IRQ_HANDLED;
 328 }
 329
 330 /*
 331  * IPC Mailbox IO
 332  */
 333
 334 static int bdw_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
 335 {
 336         /* send the message */
 337         sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
 338                           msg->msg_size);
 339         snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, SHIM_IPCX_BUSY);
 340
 341         return 0;
 342 }
 343
 344 static void bdw_get_reply(struct snd_sof_dev *sdev)
 345 {
 346         struct snd_sof_ipc_msg *msg = sdev->msg;
 347         struct sof_ipc_reply reply;
 348         int ret = 0;
 349
 350         /*
 351          * Sometimes, there is unexpected reply ipc arriving. The reply
 352          * ipc belongs to none of the ipcs sent from driver.
 353          * In this case, the driver must ignore the ipc.
 354          */
 355         if (!msg) {
 356                 dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n");
 357                 return;
 358         }
 359
 360         /* get reply */
 361         sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply));
 362
 363         if (reply.error < 0) {
 364                 memcpy(msg->reply_data, &reply, sizeof(reply));
 365                 ret = reply.error;
 366         } else {
 367                 /* reply correct size ? */
 368                 if (reply.hdr.size != msg->reply_size) {
 369                         dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n",
 370                                 msg->reply_size, reply.hdr.size);
 371                         ret = -EINVAL;
 372                 }
 373
 374                 /* read the message */
 375                 if (msg->reply_size > 0)
 376                         sof_mailbox_read(sdev, sdev->host_box.offset,
 377                                          msg->reply_data, msg->reply_size);
 378         }
 379
 380         msg->reply_error = ret;
 381 }
 382
 383 static int bdw_get_mailbox_offset(struct snd_sof_dev *sdev)
 384 {
 385         return MBOX_OFFSET;
 386 }
 387
 388 static int bdw_get_window_offset(struct snd_sof_dev *sdev, u32 id)
 389 {
 390         return MBOX_OFFSET;
 391 }
 392
 393 static void bdw_host_done(struct snd_sof_dev *sdev)
 394 {
 395         /* clear BUSY bit and set DONE bit - accept new messages */
 396         snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCD,
 397                                          SHIM_IPCD_BUSY | SHIM_IPCD_DONE,
 398                                          SHIM_IPCD_DONE);
 399
 400         /* unmask busy interrupt */
 401         snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX,
 402                                          SHIM_IMRX_BUSY, 0);
 403 }
 404
 405 static void bdw_dsp_done(struct snd_sof_dev *sdev)
 406 {
 407         /* clear DONE bit - tell DSP we have completed */
 408         snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCX,
 409                                          SHIM_IPCX_DONE, 0);
 410
 411         /* unmask Done interrupt */
 412         snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX,
 413                                          SHIM_IMRX_DONE, 0);
 414 }
 415
 416 /*
 417  * Probe and remove.
 418  */
 419 static int bdw_probe(struct snd_sof_dev *sdev)
 420 {
 421         struct snd_sof_pdata *pdata = sdev->pdata;
 422         const struct sof_dev_desc *desc = pdata->desc;
 423         struct platform_device *pdev =
 424                 container_of(sdev->dev, struct platform_device, dev);
 425         struct resource *mmio;
 426         u32 base, size;
 427         int ret;
 428
 429         /* LPE base */
 430         mmio = platform_get_resource(pdev, IORESOURCE_MEM,
 431                                      desc->resindex_lpe_base);
 432         if (mmio) {
 433                 base = mmio->start;
 434                 size = resource_size(mmio);
 435         } else {
 436                 dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n",
 437                         desc->resindex_lpe_base);
 438                 return -EINVAL;
 439         }
 440
 441         dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
 442         sdev->bar[BDW_DSP_BAR] = devm_ioremap(sdev->dev, base, size);
 443         if (!sdev->bar[BDW_DSP_BAR]) {
 444                 dev_err(sdev->dev,
 445                         "error: failed to ioremap LPE base 0x%x size 0x%x\n",
 446                         base, size);
 447                 return -ENODEV;
 448         }
 449         dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BDW_DSP_BAR]);
 450
 451         /* TODO: add offsets */
 452         sdev->mmio_bar = BDW_DSP_BAR;
 453         sdev->mailbox_bar = BDW_DSP_BAR;
 454
 455         /* PCI base */
 456         mmio = platform_get_resource(pdev, IORESOURCE_MEM,
 457                                      desc->resindex_pcicfg_base);
 458         if (mmio) {
 459                 base = mmio->start;
 460                 size = resource_size(mmio);
 461         } else {
 462                 dev_err(sdev->dev, "error: failed to get PCI base at idx %d\n",
 463                         desc->resindex_pcicfg_base);
 464                 return -ENODEV;
 465         }
 466
 467         dev_dbg(sdev->dev, "PCI base at 0x%x size 0x%x", base, size);
 468         sdev->bar[BDW_PCI_BAR] = devm_ioremap(sdev->dev, base, size);
 469         if (!sdev->bar[BDW_PCI_BAR]) {
 470                 dev_err(sdev->dev,
 471                         "error: failed to ioremap PCI base 0x%x size 0x%x\n",
 472                         base, size);
 473                 return -ENODEV;
 474         }
 475         dev_dbg(sdev->dev, "PCI VADDR %p\n", sdev->bar[BDW_PCI_BAR]);
 476
 477         /* register our IRQ */
 478         sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc);
 479         if (sdev->ipc_irq < 0)
 480                 return sdev->ipc_irq;
 481
 482         dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
 483         ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
 484                                         bdw_irq_handler, bdw_irq_thread,
 485                                         IRQF_SHARED, "AudioDSP", sdev);
 486         if (ret < 0) {
 487                 dev_err(sdev->dev, "error: failed to register IRQ %d\n",
 488                         sdev->ipc_irq);
 489                 return ret;
 490         }
 491
 492         /* enable the DSP SHIM */
 493         ret = bdw_set_dsp_D0(sdev);
 494         if (ret < 0) {
 495                 dev_err(sdev->dev, "error: failed to set DSP D0\n");
 496                 return ret;
 497         }
 498
 499         /* DSP DMA can only access low 31 bits of host memory */
 500         ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31));
 501         if (ret < 0) {
 502                 dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
 503                 return ret;
 504         }
 505
 506         /* set default mailbox */
 507         snd_sof_dsp_mailbox_init(sdev, MBOX_OFFSET, MBOX_SIZE, 0, 0);
 508
 509         return ret;
 510 }
 511
 512 /* Broadwell DAIs */
 513 static struct snd_soc_dai_driver bdw_dai[] = {
 514 {
 515         .name = "ssp0-port",
 516 },
 517 {
 518         .name = "ssp1-port",
 519 },
 520 };
 521
 522 /* broadwell ops */
 523 const struct snd_sof_dsp_ops sof_bdw_ops = {
 524         /*Device init */
 525         .probe          = bdw_probe,
 526
 527         /* DSP Core Control */
 528         .run            = bdw_run,
 529         .reset          = bdw_reset,
 530
 531         /* Register IO */
 532         .write          = sof_io_write,
 533         .read           = sof_io_read,
 534         .write64        = sof_io_write64,
 535         .read64         = sof_io_read64,
 536
 537         /* Block IO */
 538         .block_read     = sof_block_read,
 539         .block_write    = sof_block_write,
 540
 541         /* ipc */
 542         .send_msg       = bdw_send_msg,
 543         .fw_ready       = sof_fw_ready,
 544         .get_mailbox_offset = bdw_get_mailbox_offset,
 545         .get_window_offset = bdw_get_window_offset,
 546
 547         .ipc_msg_data   = intel_ipc_msg_data,
 548         .ipc_pcm_params = intel_ipc_pcm_params,
 549
 550         /* debug */
 551         .debug_map  = bdw_debugfs,
 552         .debug_map_count    = ARRAY_SIZE(bdw_debugfs),
 553         .dbg_dump   = bdw_dump,
 554
 555         /* stream callbacks */
 556         .pcm_open       = intel_pcm_open,
 557         .pcm_close      = intel_pcm_close,
 558
 559         /* Module loading */
 560         .load_module    = snd_sof_parse_module_memcpy,
 561
 562         /*Firmware loading */
 563         .load_firmware  = snd_sof_load_firmware_memcpy,
 564
 565         /* DAI drivers */
 566         .drv = bdw_dai,
 567         .num_drv = ARRAY_SIZE(bdw_dai)
 568 };
 569 EXPORT_SYMBOL(sof_bdw_ops);
 570
 571 const struct sof_intel_dsp_desc bdw_chip_info = {
 572         .cores_num = 1,
 573         .cores_mask = 1,
 574 };
 575 EXPORT_SYMBOL(bdw_chip_info);
 576
 577 MODULE_LICENSE("Dual BSD/GPL");