sound/soc/sh/rcar/adg.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Helper routines for R-Car sound ADG.
   4 //
   5 //  Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6
   7 #include <linux/clk-provider.h>
   8 #include "rsnd.h"
   9
  10 #define CLKA    0
  11 #define CLKB    1
  12 #define CLKC    2
  13 #define CLKI    3
  14 #define CLKMAX  4
  15
  16 #define CLKOUT  0
  17 #define CLKOUT1 1
  18 #define CLKOUT2 2
  19 #define CLKOUT3 3
  20 #define CLKOUTMAX 4
  21
  22 #define BRRx_MASK(x) (0x3FF & x)
  23
  24 static struct rsnd_mod_ops adg_ops = {
  25         .name = "adg",
  26 };
  27
  28 struct rsnd_adg {
  29         struct clk *clk[CLKMAX];
  30         struct clk *clkout[CLKOUTMAX];
  31         struct clk_onecell_data onecell;
  32         struct rsnd_mod mod;
  33         u32 flags;
  34         u32 ckr;
  35         u32 rbga;
  36         u32 rbgb;
  37
  38         int rbga_rate_for_441khz; /* RBGA */
  39         int rbgb_rate_for_48khz;  /* RBGB */
  40 };
  41
  42 #define LRCLK_ASYNC     (1 << 0)
  43 #define AUDIO_OUT_48    (1 << 1)
  44
  45 #define for_each_rsnd_clk(pos, adg, i)          \
  46         for (i = 0;                             \
  47              (i < CLKMAX) &&                    \
  48              ((pos) = adg->clk[i]);             \
  49              i++)
  50 #define for_each_rsnd_clkout(pos, adg, i)       \
  51         for (i = 0;                             \
  52              (i < CLKOUTMAX) &&                 \
  53              ((pos) = adg->clkout[i]);  \
  54              i++)
  55 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
  56
  57 static const char * const clk_name[] = {
  58         [CLKA]  = "clk_a",
  59         [CLKB]  = "clk_b",
  60         [CLKC]  = "clk_c",
  61         [CLKI]  = "clk_i",
  62 };
  63
  64 static u32 rsnd_adg_calculate_rbgx(unsigned long div)
  65 {
  66         int i, ratio;
  67
  68         if (!div)
  69                 return 0;
  70
  71         for (i = 3; i >= 0; i--) {
  72                 ratio = 2 << (i * 2);
  73                 if (0 == (div % ratio))
  74                         return (u32)((i << 8) | ((div / ratio) - 1));
  75         }
  76
  77         return ~0;
  78 }
  79
  80 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
  81 {
  82         struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io);
  83         int id = rsnd_mod_id(ssi_mod);
  84         int ws = id;
  85
  86         if (rsnd_ssi_is_pin_sharing(io)) {
  87                 switch (id) {
  88                 case 1:
  89                 case 2:
  90                         ws = 0;
  91                         break;
  92                 case 4:
  93                         ws = 3;
  94                         break;
  95                 case 8:
  96                         ws = 7;
  97                         break;
  98                 }
  99         }
 100
 101         return (0x6 + ws) << 8;
 102 }
 103
 104 static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
 105                                        struct rsnd_dai_stream *io,
 106                                        unsigned int target_rate,
 107                                        unsigned int *target_val,
 108                                        unsigned int *target_en)
 109 {
 110         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 111         struct device *dev = rsnd_priv_to_dev(priv);
 112         int idx, sel, div, step;
 113         unsigned int val, en;
 114         unsigned int min, diff;
 115         unsigned int sel_rate[] = {
 116                 clk_get_rate(adg->clk[CLKA]),   /* 0000: CLKA */
 117                 clk_get_rate(adg->clk[CLKB]),   /* 0001: CLKB */
 118                 clk_get_rate(adg->clk[CLKC]),   /* 0010: CLKC */
 119                 adg->rbga_rate_for_441khz,      /* 0011: RBGA */
 120                 adg->rbgb_rate_for_48khz,       /* 0100: RBGB */
 121         };
 122
 123         min = ~0;
 124         val = 0;
 125         en = 0;
 126         for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
 127                 idx = 0;
 128                 step = 2;
 129
 130                 if (!sel_rate[sel])
 131                         continue;
 132
 133                 for (div = 2; div <= 98304; div += step) {
 134                         diff = abs(target_rate - sel_rate[sel] / div);
 135                         if (min > diff) {
 136                                 val = (sel << 8) | idx;
 137                                 min = diff;
 138                                 en = 1 << (sel + 1); /* fixme */
 139                         }
 140
 141                         /*
 142                          * step of 0_0000 / 0_0001 / 0_1101
 143                          * are out of order
 144                          */
 145                         if ((idx > 2) && (idx % 2))
 146                                 step *= 2;
 147                         if (idx == 0x1c) {
 148                                 div += step;
 149                                 step *= 2;
 150                         }
 151                         idx++;
 152                 }
 153         }
 154
 155         if (min == ~0) {
 156                 dev_err(dev, "no Input clock\n");
 157                 return;
 158         }
 159
 160         *target_val = val;
 161         if (target_en)
 162                 *target_en = en;
 163 }
 164
 165 static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
 166                                        struct rsnd_dai_stream *io,
 167                                        unsigned int in_rate,
 168                                        unsigned int out_rate,
 169                                        u32 *in, u32 *out, u32 *en)
 170 {
 171         struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
 172         unsigned int target_rate;
 173         u32 *target_val;
 174         u32 _in;
 175         u32 _out;
 176         u32 _en;
 177
 178         /* default = SSI WS */
 179         _in =
 180         _out = rsnd_adg_ssi_ws_timing_gen2(io);
 181
 182         target_rate = 0;
 183         target_val = NULL;
 184         _en = 0;
 185         if (runtime->rate != in_rate) {
 186                 target_rate = out_rate;
 187                 target_val  = &_out;
 188         } else if (runtime->rate != out_rate) {
 189                 target_rate = in_rate;
 190                 target_val  = &_in;
 191         }
 192
 193         if (target_rate)
 194                 __rsnd_adg_get_timesel_ratio(priv, io,
 195                                              target_rate,
 196                                              target_val, &_en);
 197
 198         if (in)
 199                 *in = _in;
 200         if (out)
 201                 *out = _out;
 202         if (en)
 203                 *en = _en;
 204 }
 205
 206 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod,
 207                                  struct rsnd_dai_stream *io)
 208 {
 209         struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod);
 210         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 211         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 212         int id = rsnd_mod_id(cmd_mod);
 213         int shift = (id % 2) ? 16 : 0;
 214         u32 mask, val;
 215
 216         rsnd_adg_get_timesel_ratio(priv, io,
 217                                    rsnd_src_get_in_rate(priv, io),
 218                                    rsnd_src_get_out_rate(priv, io),
 219                                    NULL, &val, NULL);
 220
 221         val  = val      << shift;
 222         mask = 0x0f1f   << shift;
 223
 224         rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);
 225
 226         return 0;
 227 }
 228
 229 int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod,
 230                                   struct rsnd_dai_stream *io,
 231                                   unsigned int in_rate,
 232                                   unsigned int out_rate)
 233 {
 234         struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
 235         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 236         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 237         u32 in, out;
 238         u32 mask, en;
 239         int id = rsnd_mod_id(src_mod);
 240         int shift = (id % 2) ? 16 : 0;
 241
 242         rsnd_mod_confirm_src(src_mod);
 243
 244         rsnd_adg_get_timesel_ratio(priv, io,
 245                                    in_rate, out_rate,
 246                                    &in, &out, &en);
 247
 248         in   = in       << shift;
 249         out  = out      << shift;
 250         mask = 0x0f1f   << shift;
 251
 252         rsnd_mod_bset(adg_mod, SRCIN_TIMSEL(id / 2),  mask, in);
 253         rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL(id / 2), mask, out);
 254
 255         if (en)
 256                 rsnd_mod_bset(adg_mod, DIV_EN, en, en);
 257
 258         return 0;
 259 }
 260
 261 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
 262 {
 263         struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
 264         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 265         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 266         struct device *dev = rsnd_priv_to_dev(priv);
 267         int id = rsnd_mod_id(ssi_mod);
 268         int shift = (id % 4) * 8;
 269         u32 mask = 0xFF << shift;
 270
 271         rsnd_mod_confirm_ssi(ssi_mod);
 272
 273         val = val << shift;
 274
 275         /*
 276          * SSI 8 is not connected to ADG.
 277          * it works with SSI 7
 278          */
 279         if (id == 8)
 280                 return;
 281
 282         rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL(id / 4), mask, val);
 283
 284         dev_dbg(dev, "AUDIO_CLK_SEL is 0x%x\n", val);
 285 }
 286
 287 int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate)
 288 {
 289         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 290         struct clk *clk;
 291         int i;
 292         int sel_table[] = {
 293                 [CLKA] = 0x1,
 294                 [CLKB] = 0x2,
 295                 [CLKC] = 0x3,
 296                 [CLKI] = 0x0,
 297         };
 298
 299         /*
 300          * find suitable clock from
 301          * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
 302          */
 303         for_each_rsnd_clk(clk, adg, i) {
 304                 if (rate == clk_get_rate(clk))
 305                         return sel_table[i];
 306         }
 307
 308         /*
 309          * find divided clock from BRGA/BRGB
 310          */
 311         if (rate == adg->rbga_rate_for_441khz)
 312                 return 0x10;
 313
 314         if (rate == adg->rbgb_rate_for_48khz)
 315                 return 0x20;
 316
 317         return -EIO;
 318 }
 319
 320 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod)
 321 {
 322         rsnd_adg_set_ssi_clk(ssi_mod, 0);
 323
 324         return 0;
 325 }
 326
 327 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
 328 {
 329         struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
 330         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 331         struct device *dev = rsnd_priv_to_dev(priv);
 332         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 333         int data;
 334         u32 ckr = 0;
 335
 336         data = rsnd_adg_clk_query(priv, rate);
 337         if (data < 0)
 338                 return data;
 339
 340         rsnd_adg_set_ssi_clk(ssi_mod, data);
 341
 342         if (rsnd_flags_has(adg, LRCLK_ASYNC)) {
 343                 if (rsnd_flags_has(adg, AUDIO_OUT_48))
 344                         ckr = 0x80000000;
 345         } else {
 346                 if (0 == (rate % 8000))
 347                         ckr = 0x80000000;
 348         }
 349
 350         rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr | ckr);
 351         rsnd_mod_write(adg_mod, BRRA,  adg->rbga);
 352         rsnd_mod_write(adg_mod, BRRB,  adg->rbgb);
 353
 354         dev_dbg(dev, "CLKOUT is based on BRG%c (= %dHz)\n",
 355                 (ckr) ? 'B' : 'A',
 356                 (ckr) ? adg->rbgb_rate_for_48khz :
 357                         adg->rbga_rate_for_441khz);
 358
 359         return 0;
 360 }
 361
 362 void rsnd_adg_clk_control(struct rsnd_priv *priv, int enable)
 363 {
 364         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 365         struct device *dev = rsnd_priv_to_dev(priv);
 366         struct clk *clk;
 367         int i, ret;
 368
 369         for_each_rsnd_clk(clk, adg, i) {
 370                 ret = 0;
 371                 if (enable)
 372                         ret = clk_prepare_enable(clk);
 373                 else
 374                         clk_disable_unprepare(clk);
 375
 376                 if (ret < 0)
 377                         dev_warn(dev, "can't use clk %d\n", i);
 378         }
 379 }
 380
 381 static void rsnd_adg_get_clkin(struct rsnd_priv *priv,
 382                                struct rsnd_adg *adg)
 383 {
 384         struct device *dev = rsnd_priv_to_dev(priv);
 385         struct clk *clk;
 386         int i;
 387
 388         for (i = 0; i < CLKMAX; i++) {
 389                 clk = devm_clk_get(dev, clk_name[i]);
 390                 adg->clk[i] = IS_ERR(clk) ? NULL : clk;
 391         }
 392 }
 393
 394 static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
 395                                 struct rsnd_adg *adg)
 396 {
 397         struct clk *clk;
 398         struct device *dev = rsnd_priv_to_dev(priv);
 399         struct device_node *np = dev->of_node;
 400         struct property *prop;
 401         u32 ckr, rbgx, rbga, rbgb;
 402         u32 rate, div;
 403 #define REQ_SIZE 2
 404         u32 req_rate[REQ_SIZE] = {};
 405         uint32_t count = 0;
 406         unsigned long req_48kHz_rate, req_441kHz_rate;
 407         int i, req_size;
 408         const char *parent_clk_name = NULL;
 409         static const char * const clkout_name[] = {
 410                 [CLKOUT]  = "audio_clkout",
 411                 [CLKOUT1] = "audio_clkout1",
 412                 [CLKOUT2] = "audio_clkout2",
 413                 [CLKOUT3] = "audio_clkout3",
 414         };
 415         int brg_table[] = {
 416                 [CLKA] = 0x0,
 417                 [CLKB] = 0x1,
 418                 [CLKC] = 0x4,
 419                 [CLKI] = 0x2,
 420         };
 421
 422         ckr = 0;
 423         rbga = 2; /* default 1/6 */
 424         rbgb = 2; /* default 1/6 */
 425
 426         /*
 427          * ADG supports BRRA/BRRB output only
 428          * this means all clkout0/1/2/3 will be same rate
 429          */
 430         prop = of_find_property(np, "clock-frequency", NULL);
 431         if (!prop)
 432                 goto rsnd_adg_get_clkout_end;
 433
 434         req_size = prop->length / sizeof(u32);
 435         if (req_size > REQ_SIZE) {
 436                 dev_err(dev,
 437                         "too many clock-frequency, use top %d\n", REQ_SIZE);
 438                 req_size = REQ_SIZE;
 439         }
 440
 441         of_property_read_u32_array(np, "clock-frequency", req_rate, req_size);
 442         req_48kHz_rate = 0;
 443         req_441kHz_rate = 0;
 444         for (i = 0; i < req_size; i++) {
 445                 if (0 == (req_rate[i] % 44100))
 446                         req_441kHz_rate = req_rate[i];
 447                 if (0 == (req_rate[i] % 48000))
 448                         req_48kHz_rate = req_rate[i];
 449         }
 450
 451         if (req_rate[0] % 48000 == 0)
 452                 rsnd_flags_set(adg, AUDIO_OUT_48);
 453
 454         if (of_get_property(np, "clkout-lr-asynchronous", NULL))
 455                 rsnd_flags_set(adg, LRCLK_ASYNC);
 456
 457         /*
 458          * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
 459          * have 44.1kHz or 48kHz base clocks for now.
 460          *
 461          * SSI itself can divide parent clock by 1/1 - 1/16
 462          * see
 463          *      rsnd_adg_ssi_clk_try_start()
 464          *      rsnd_ssi_master_clk_start()
 465          */
 466         adg->rbga_rate_for_441khz       = 0;
 467         adg->rbgb_rate_for_48khz        = 0;
 468         for_each_rsnd_clk(clk, adg, i) {
 469                 rate = clk_get_rate(clk);
 470
 471                 if (0 == rate) /* not used */
 472                         continue;
 473
 474                 /* RBGA */
 475                 if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) {
 476                         div = 6;
 477                         if (req_441kHz_rate)
 478                                 div = rate / req_441kHz_rate;
 479                         rbgx = rsnd_adg_calculate_rbgx(div);
 480                         if (BRRx_MASK(rbgx) == rbgx) {
 481                                 rbga = rbgx;
 482                                 adg->rbga_rate_for_441khz = rate / div;
 483                                 ckr |= brg_table[i] << 20;
 484                                 if (req_441kHz_rate &&
 485                                     !rsnd_flags_has(adg, AUDIO_OUT_48))
 486                                         parent_clk_name = __clk_get_name(clk);
 487                         }
 488                 }
 489
 490                 /* RBGB */
 491                 if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) {
 492                         div = 6;
 493                         if (req_48kHz_rate)
 494                                 div = rate / req_48kHz_rate;
 495                         rbgx = rsnd_adg_calculate_rbgx(div);
 496                         if (BRRx_MASK(rbgx) == rbgx) {
 497                                 rbgb = rbgx;
 498                                 adg->rbgb_rate_for_48khz = rate / div;
 499                                 ckr |= brg_table[i] << 16;
 500                                 if (req_48kHz_rate &&
 501                                     rsnd_flags_has(adg, AUDIO_OUT_48))
 502                                         parent_clk_name = __clk_get_name(clk);
 503                         }
 504                 }
 505         }
 506
 507         /*
 508          * ADG supports BRRA/BRRB output only.
 509          * this means all clkout0/1/2/3 will be * same rate
 510          */
 511
 512         of_property_read_u32(np, "#clock-cells", &count);
 513         /*
 514          * for clkout
 515          */
 516         if (!count) {
 517                 clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
 518                                               parent_clk_name, 0, req_rate[0]);
 519                 if (!IS_ERR(clk)) {
 520                         adg->clkout[CLKOUT] = clk;
 521                         of_clk_add_provider(np, of_clk_src_simple_get, clk);
 522                 }
 523         }
 524         /*
 525          * for clkout0/1/2/3
 526          */
 527         else {
 528                 for (i = 0; i < CLKOUTMAX; i++) {
 529                         clk = clk_register_fixed_rate(dev, clkout_name[i],
 530                                                       parent_clk_name, 0,
 531                                                       req_rate[0]);
 532                         if (!IS_ERR(clk))
 533                                 adg->clkout[i] = clk;
 534                 }
 535                 adg->onecell.clks       = adg->clkout;
 536                 adg->onecell.clk_num    = CLKOUTMAX;
 537                 of_clk_add_provider(np, of_clk_src_onecell_get,
 538                                     &adg->onecell);
 539         }
 540
 541 rsnd_adg_get_clkout_end:
 542         adg->ckr = ckr;
 543         adg->rbga = rbga;
 544         adg->rbgb = rbgb;
 545 }
 546
 547 #ifdef DEBUG
 548 static void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, struct rsnd_adg *adg)
 549 {
 550         struct device *dev = rsnd_priv_to_dev(priv);
 551         struct clk *clk;
 552         int i;
 553
 554         for_each_rsnd_clk(clk, adg, i)
 555                 dev_dbg(dev, "%s    : %pa : %ld\n",
 556                         clk_name[i], clk, clk_get_rate(clk));
 557
 558         dev_dbg(dev, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
 559                 adg->ckr, adg->rbga, adg->rbgb);
 560         dev_dbg(dev, "BRGA (for 44100 base) = %d\n", adg->rbga_rate_for_441khz);
 561         dev_dbg(dev, "BRGB (for 48000 base) = %d\n", adg->rbgb_rate_for_48khz);
 562
 563         /*
 564          * Actual CLKOUT will be exchanged in rsnd_adg_ssi_clk_try_start()
 565          * by BRGCKR::BRGCKR_31
 566          */
 567         for_each_rsnd_clkout(clk, adg, i)
 568                 dev_dbg(dev, "clkout %d : %pa : %ld\n", i,
 569                         clk, clk_get_rate(clk));
 570 }
 571 #else
 572 #define rsnd_adg_clk_dbg_info(priv, adg)
 573 #endif
 574
 575 int rsnd_adg_probe(struct rsnd_priv *priv)
 576 {
 577         struct rsnd_adg *adg;
 578         struct device *dev = rsnd_priv_to_dev(priv);
 579         int ret;
 580
 581         adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
 582         if (!adg)
 583                 return -ENOMEM;
 584
 585         ret = rsnd_mod_init(priv, &adg->mod, &adg_ops,
 586                       NULL, 0, 0);
 587         if (ret)
 588                 return ret;
 589
 590         rsnd_adg_get_clkin(priv, adg);
 591         rsnd_adg_get_clkout(priv, adg);
 592         rsnd_adg_clk_dbg_info(priv, adg);
 593
 594         priv->adg = adg;
 595
 596         rsnd_adg_clk_enable(priv);
 597
 598         return 0;
 599 }
 600
 601 void rsnd_adg_remove(struct rsnd_priv *priv)
 602 {
 603         struct device *dev = rsnd_priv_to_dev(priv);
 604         struct device_node *np = dev->of_node;
 605         struct rsnd_adg *adg = priv->adg;
 606         struct clk *clk;
 607         int i;
 608
 609         for_each_rsnd_clkout(clk, adg, i)
 610                 if (adg->clkout[i])
 611                         clk_unregister_fixed_rate(adg->clkout[i]);
 612
 613         of_clk_del_provider(np);
 614
 615         rsnd_adg_clk_disable(priv);
 616 }