1 // SPDX-License-Identifier: GPL-2.0
3 // Helper routines for R-Car sound ADG.
5 // Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 #include <linux/clk-provider.h>
7 #include <linux/clkdev.h>
22 #define BRRx_MASK(x) (0x3FF & x)
24 static struct rsnd_mod_ops adg_ops = {
29 struct clk *clk[CLKMAX];
30 struct clk *clkout[CLKOUTMAX];
32 struct clk_onecell_data onecell;
40 int rbga_rate_for_441khz; /* RBGA */
41 int rbgb_rate_for_48khz; /* RBGB */
44 #define LRCLK_ASYNC (1 << 0)
45 #define AUDIO_OUT_48 (1 << 1)
47 #define for_each_rsnd_clk(pos, adg, i) \
50 ((pos) = adg->clk[i]); \
52 #define for_each_rsnd_clkout(pos, adg, i) \
55 ((pos) = adg->clkout[i]); \
57 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
59 static const char * const clk_name[] = {
66 static u32 rsnd_adg_calculate_rbgx(unsigned long div)
73 for (i = 3; i >= 0; i--) {
74 int ratio = 2 << (i * 2);
75 if (0 == (div % ratio))
76 return (u32)((i << 8) | ((div / ratio) - 1));
82 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
84 struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io);
85 int id = rsnd_mod_id(ssi_mod);
88 if (rsnd_ssi_is_pin_sharing(io)) {
104 return (0x6 + ws) << 8;
107 static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
108 struct rsnd_dai_stream *io,
109 unsigned int target_rate,
110 unsigned int *target_val,
111 unsigned int *target_en)
113 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
114 struct device *dev = rsnd_priv_to_dev(priv);
116 unsigned int val, en;
117 unsigned int min, diff;
118 unsigned int sel_rate[] = {
119 adg->clk_rate[CLKA], /* 0000: CLKA */
120 adg->clk_rate[CLKB], /* 0001: CLKB */
121 adg->clk_rate[CLKC], /* 0010: CLKC */
122 adg->rbga_rate_for_441khz, /* 0011: RBGA */
123 adg->rbgb_rate_for_48khz, /* 0100: RBGB */
129 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
137 for (div = 2; div <= 98304; div += step) {
138 diff = abs(target_rate - sel_rate[sel] / div);
140 val = (sel << 8) | idx;
142 en = 1 << (sel + 1); /* fixme */
146 * step of 0_0000 / 0_0001 / 0_1101
149 if ((idx > 2) && (idx % 2))
160 dev_err(dev, "no Input clock\n");
169 static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
170 struct rsnd_dai_stream *io,
171 unsigned int in_rate,
172 unsigned int out_rate,
173 u32 *in, u32 *out, u32 *en)
175 struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
176 unsigned int target_rate;
182 /* default = SSI WS */
184 _out = rsnd_adg_ssi_ws_timing_gen2(io);
189 if (runtime->rate != in_rate) {
190 target_rate = out_rate;
192 } else if (runtime->rate != out_rate) {
193 target_rate = in_rate;
198 __rsnd_adg_get_timesel_ratio(priv, io,
210 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod,
211 struct rsnd_dai_stream *io)
213 struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod);
214 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
215 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
216 int id = rsnd_mod_id(cmd_mod);
217 int shift = (id % 2) ? 16 : 0;
220 rsnd_adg_get_timesel_ratio(priv, io,
221 rsnd_src_get_in_rate(priv, io),
222 rsnd_src_get_out_rate(priv, io),
226 mask = 0x0f1f << shift;
228 rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);
233 int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod,
234 struct rsnd_dai_stream *io,
235 unsigned int in_rate,
236 unsigned int out_rate)
238 struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
239 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
240 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
243 int id = rsnd_mod_id(src_mod);
244 int shift = (id % 2) ? 16 : 0;
246 rsnd_mod_confirm_src(src_mod);
248 rsnd_adg_get_timesel_ratio(priv, io,
254 mask = 0x0f1f << shift;
256 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL(id / 2), mask, in);
257 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL(id / 2), mask, out);
260 rsnd_mod_bset(adg_mod, DIV_EN, en, en);
265 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
267 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
268 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
269 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
270 struct device *dev = rsnd_priv_to_dev(priv);
271 int id = rsnd_mod_id(ssi_mod);
272 int shift = (id % 4) * 8;
273 u32 mask = 0xFF << shift;
275 rsnd_mod_confirm_ssi(ssi_mod);
280 * SSI 8 is not connected to ADG.
281 * it works with SSI 7
286 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL(id / 4), mask, val);
288 dev_dbg(dev, "AUDIO_CLK_SEL is 0x%x\n", val);
291 int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate)
293 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
303 * find suitable clock from
304 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
306 for (i = 0; i < CLKMAX; i++)
307 if (rate == adg->clk_rate[i])
311 * find divided clock from BRGA/BRGB
313 if (rate == adg->rbga_rate_for_441khz)
316 if (rate == adg->rbgb_rate_for_48khz)
322 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod)
324 rsnd_adg_set_ssi_clk(ssi_mod, 0);
329 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
331 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
332 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
333 struct device *dev = rsnd_priv_to_dev(priv);
334 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
338 data = rsnd_adg_clk_query(priv, rate);
342 rsnd_adg_set_ssi_clk(ssi_mod, data);
344 if (rsnd_flags_has(adg, LRCLK_ASYNC)) {
345 if (rsnd_flags_has(adg, AUDIO_OUT_48))
348 if (0 == (rate % 8000))
352 rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr | ckr);
353 rsnd_mod_write(adg_mod, BRRA, adg->rbga);
354 rsnd_mod_write(adg_mod, BRRB, adg->rbgb);
356 dev_dbg(dev, "CLKOUT is based on BRG%c (= %dHz)\n",
358 (ckr) ? adg->rbgb_rate_for_48khz :
359 adg->rbga_rate_for_441khz);
364 void rsnd_adg_clk_control(struct rsnd_priv *priv, int enable)
366 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
370 for_each_rsnd_clk(clk, adg, i) {
372 clk_prepare_enable(clk);
375 * We shouldn't use clk_get_rate() under
376 * atomic context. Let's keep it when
377 * rsnd_adg_clk_enable() was called
379 adg->clk_rate[i] = clk_get_rate(clk);
381 clk_disable_unprepare(clk);
386 static struct clk *rsnd_adg_create_null_clk(struct rsnd_priv *priv,
387 const char * const name,
390 struct device *dev = rsnd_priv_to_dev(priv);
393 clk = clk_register_fixed_rate(dev, name, parent, 0, 0);
395 dev_err(dev, "create null clk error\n");
402 static struct clk *rsnd_adg_null_clk_get(struct rsnd_priv *priv)
404 struct rsnd_adg *adg = priv->adg;
406 if (!adg->null_clk) {
407 static const char * const name = "rsnd_adg_null";
409 adg->null_clk = rsnd_adg_create_null_clk(priv, name, NULL);
412 return adg->null_clk;
415 static void rsnd_adg_null_clk_clean(struct rsnd_priv *priv)
417 struct rsnd_adg *adg = priv->adg;
420 clk_unregister_fixed_rate(adg->null_clk);
423 static int rsnd_adg_get_clkin(struct rsnd_priv *priv)
425 struct rsnd_adg *adg = priv->adg;
426 struct device *dev = rsnd_priv_to_dev(priv);
430 for (i = 0; i < CLKMAX; i++) {
431 clk = devm_clk_get(dev, clk_name[i]);
434 clk = rsnd_adg_null_clk_get(priv);
444 dev_err(dev, "adg clock IN get failed\n");
446 rsnd_adg_null_clk_clean(priv);
451 static void rsnd_adg_unregister_clkout(struct rsnd_priv *priv)
453 struct rsnd_adg *adg = priv->adg;
457 for_each_rsnd_clkout(clk, adg, i)
458 clk_unregister_fixed_rate(clk);
461 static int rsnd_adg_get_clkout(struct rsnd_priv *priv)
463 struct rsnd_adg *adg = priv->adg;
465 struct device *dev = rsnd_priv_to_dev(priv);
466 struct device_node *np = dev->of_node;
467 struct property *prop;
468 u32 ckr, rbgx, rbga, rbgb;
471 u32 req_rate[REQ_SIZE] = {};
473 unsigned long req_48kHz_rate, req_441kHz_rate;
475 const char *parent_clk_name = NULL;
476 static const char * const clkout_name[] = {
477 [CLKOUT] = "audio_clkout",
478 [CLKOUT1] = "audio_clkout1",
479 [CLKOUT2] = "audio_clkout2",
480 [CLKOUT3] = "audio_clkout3",
490 rbga = 2; /* default 1/6 */
491 rbgb = 2; /* default 1/6 */
494 * ADG supports BRRA/BRRB output only
495 * this means all clkout0/1/2/3 will be same rate
497 prop = of_find_property(np, "clock-frequency", NULL);
499 goto rsnd_adg_get_clkout_end;
501 req_size = prop->length / sizeof(u32);
502 if (req_size > REQ_SIZE) {
503 dev_err(dev, "too many clock-frequency\n");
507 of_property_read_u32_array(np, "clock-frequency", req_rate, req_size);
510 for (i = 0; i < req_size; i++) {
511 if (0 == (req_rate[i] % 44100))
512 req_441kHz_rate = req_rate[i];
513 if (0 == (req_rate[i] % 48000))
514 req_48kHz_rate = req_rate[i];
517 if (req_rate[0] % 48000 == 0)
518 rsnd_flags_set(adg, AUDIO_OUT_48);
520 if (of_get_property(np, "clkout-lr-asynchronous", NULL))
521 rsnd_flags_set(adg, LRCLK_ASYNC);
524 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
525 * have 44.1kHz or 48kHz base clocks for now.
527 * SSI itself can divide parent clock by 1/1 - 1/16
529 * rsnd_adg_ssi_clk_try_start()
530 * rsnd_ssi_master_clk_start()
532 adg->rbga_rate_for_441khz = 0;
533 adg->rbgb_rate_for_48khz = 0;
534 for_each_rsnd_clk(clk, adg, i) {
535 rate = clk_get_rate(clk);
537 if (0 == rate) /* not used */
541 if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) {
544 div = rate / req_441kHz_rate;
545 rbgx = rsnd_adg_calculate_rbgx(div);
546 if (BRRx_MASK(rbgx) == rbgx) {
548 adg->rbga_rate_for_441khz = rate / div;
549 ckr |= brg_table[i] << 20;
550 if (req_441kHz_rate &&
551 !rsnd_flags_has(adg, AUDIO_OUT_48))
552 parent_clk_name = __clk_get_name(clk);
557 if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) {
560 div = rate / req_48kHz_rate;
561 rbgx = rsnd_adg_calculate_rbgx(div);
562 if (BRRx_MASK(rbgx) == rbgx) {
564 adg->rbgb_rate_for_48khz = rate / div;
565 ckr |= brg_table[i] << 16;
566 if (req_48kHz_rate &&
567 rsnd_flags_has(adg, AUDIO_OUT_48))
568 parent_clk_name = __clk_get_name(clk);
574 * ADG supports BRRA/BRRB output only.
575 * this means all clkout0/1/2/3 will be * same rate
578 of_property_read_u32(np, "#clock-cells", &count);
583 clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
584 parent_clk_name, 0, req_rate[0]);
588 adg->clkout[CLKOUT] = clk;
589 of_clk_add_provider(np, of_clk_src_simple_get, clk);
595 for (i = 0; i < CLKOUTMAX; i++) {
596 clk = clk_register_fixed_rate(dev, clkout_name[i],
602 adg->clkout[i] = clk;
604 adg->onecell.clks = adg->clkout;
605 adg->onecell.clk_num = CLKOUTMAX;
606 of_clk_add_provider(np, of_clk_src_onecell_get,
610 rsnd_adg_get_clkout_end:
618 dev_err(dev, "adg clock OUT get failed\n");
620 rsnd_adg_unregister_clkout(priv);
625 #if defined(DEBUG) || defined(CONFIG_DEBUG_FS)
627 static void dbg_msg(struct device *dev, struct seq_file *m,
628 const char *fmt, ...)
634 vsnprintf(msg, sizeof(msg), fmt, args);
640 dev_dbg(dev, "%s", msg);
643 void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, struct seq_file *m)
645 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
646 struct device *dev = rsnd_priv_to_dev(priv);
650 for_each_rsnd_clk(clk, adg, i)
651 dbg_msg(dev, m, "%s : %pa : %ld\n",
652 clk_name[i], clk, clk_get_rate(clk));
654 dbg_msg(dev, m, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
655 adg->ckr, adg->rbga, adg->rbgb);
656 dbg_msg(dev, m, "BRGA (for 44100 base) = %d\n", adg->rbga_rate_for_441khz);
657 dbg_msg(dev, m, "BRGB (for 48000 base) = %d\n", adg->rbgb_rate_for_48khz);
660 * Actual CLKOUT will be exchanged in rsnd_adg_ssi_clk_try_start()
661 * by BRGCKR::BRGCKR_31
663 for_each_rsnd_clkout(clk, adg, i)
664 dbg_msg(dev, m, "clkout %d : %pa : %ld\n", i,
665 clk, clk_get_rate(clk));
668 #define rsnd_adg_clk_dbg_info(priv, m)
671 int rsnd_adg_probe(struct rsnd_priv *priv)
673 struct rsnd_adg *adg;
674 struct device *dev = rsnd_priv_to_dev(priv);
677 adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
681 ret = rsnd_mod_init(priv, &adg->mod, &adg_ops,
688 ret = rsnd_adg_get_clkin(priv);
692 ret = rsnd_adg_get_clkout(priv);
696 rsnd_adg_clk_enable(priv);
697 rsnd_adg_clk_dbg_info(priv, NULL);
702 void rsnd_adg_remove(struct rsnd_priv *priv)
704 struct device *dev = rsnd_priv_to_dev(priv);
705 struct device_node *np = dev->of_node;
707 rsnd_adg_unregister_clkout(priv);
709 of_clk_del_provider(np);
711 rsnd_adg_clk_disable(priv);
713 /* It should be called after rsnd_adg_clk_disable() */
714 rsnd_adg_null_clk_clean(priv);