1 // SPDX-License-Identifier: GPL-2.0+
3 // s3c24xx-i2s.c -- ALSA Soc Audio Layer
5 // (c) 2006 Wolfson Microelectronics PLC.
6 // Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
8 // Copyright 2004-2005 Simtec Electronics
9 // http://armlinux.simtec.co.uk/
10 // Ben Dooks <ben@simtec.co.uk>
12 #include <linux/delay.h>
13 #include <linux/clk.h>
15 #include <linux/gpio.h>
16 #include <linux/module.h>
18 #include <sound/soc.h>
19 #include <sound/pcm_params.h>
21 #include <mach/gpio-samsung.h>
22 #include <plat/gpio-cfg.h>
26 #include "s3c24xx-i2s.h"
28 static struct snd_dmaengine_dai_dma_data s3c24xx_i2s_pcm_stereo_out = {
33 static struct snd_dmaengine_dai_dma_data s3c24xx_i2s_pcm_stereo_in = {
38 struct s3c24xx_i2s_info {
46 static struct s3c24xx_i2s_info s3c24xx_i2s;
48 static void s3c24xx_snd_txctrl(int on)
54 iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
55 iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
56 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
58 pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
61 iisfcon |= S3C2410_IISFCON_TXDMA | S3C2410_IISFCON_TXENABLE;
62 iiscon |= S3C2410_IISCON_TXDMAEN | S3C2410_IISCON_IISEN;
63 iiscon &= ~S3C2410_IISCON_TXIDLE;
64 iismod |= S3C2410_IISMOD_TXMODE;
66 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
67 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
68 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
70 /* note, we have to disable the FIFOs otherwise bad things
71 * seem to happen when the DMA stops. According to the
72 * Samsung supplied kernel, this should allow the DMA
73 * engine and FIFOs to reset. If this isn't allowed, the
74 * DMA engine will simply freeze randomly.
77 iisfcon &= ~S3C2410_IISFCON_TXENABLE;
78 iisfcon &= ~S3C2410_IISFCON_TXDMA;
79 iiscon |= S3C2410_IISCON_TXIDLE;
80 iiscon &= ~S3C2410_IISCON_TXDMAEN;
81 iismod &= ~S3C2410_IISMOD_TXMODE;
83 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
84 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
85 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
88 pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
91 static void s3c24xx_snd_rxctrl(int on)
97 iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
98 iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
99 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
101 pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
104 iisfcon |= S3C2410_IISFCON_RXDMA | S3C2410_IISFCON_RXENABLE;
105 iiscon |= S3C2410_IISCON_RXDMAEN | S3C2410_IISCON_IISEN;
106 iiscon &= ~S3C2410_IISCON_RXIDLE;
107 iismod |= S3C2410_IISMOD_RXMODE;
109 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
110 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
111 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
113 /* note, we have to disable the FIFOs otherwise bad things
114 * seem to happen when the DMA stops. According to the
115 * Samsung supplied kernel, this should allow the DMA
116 * engine and FIFOs to reset. If this isn't allowed, the
117 * DMA engine will simply freeze randomly.
120 iisfcon &= ~S3C2410_IISFCON_RXENABLE;
121 iisfcon &= ~S3C2410_IISFCON_RXDMA;
122 iiscon |= S3C2410_IISCON_RXIDLE;
123 iiscon &= ~S3C2410_IISCON_RXDMAEN;
124 iismod &= ~S3C2410_IISMOD_RXMODE;
126 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
127 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
128 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
131 pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
135 * Wait for the LR signal to allow synchronisation to the L/R clock
136 * from the codec. May only be needed for slave mode.
138 static int s3c24xx_snd_lrsync(void)
141 int timeout = 50; /* 5ms */
144 iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
145 if (iiscon & S3C2410_IISCON_LRINDEX)
157 * Check whether CPU is the master or slave
159 static inline int s3c24xx_snd_is_clkmaster(void)
161 return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C2410_IISMOD_SLAVE) ? 0:1;
165 * Set S3C24xx I2S DAI format
167 static int s3c24xx_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
172 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
173 pr_debug("hw_params r: IISMOD: %x \n", iismod);
175 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
176 case SND_SOC_DAIFMT_CBM_CFM:
177 iismod |= S3C2410_IISMOD_SLAVE;
179 case SND_SOC_DAIFMT_CBS_CFS:
180 iismod &= ~S3C2410_IISMOD_SLAVE;
186 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
187 case SND_SOC_DAIFMT_LEFT_J:
188 iismod |= S3C2410_IISMOD_MSB;
190 case SND_SOC_DAIFMT_I2S:
191 iismod &= ~S3C2410_IISMOD_MSB;
197 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
198 pr_debug("hw_params w: IISMOD: %x \n", iismod);
203 static int s3c24xx_i2s_hw_params(struct snd_pcm_substream *substream,
204 struct snd_pcm_hw_params *params,
205 struct snd_soc_dai *dai)
207 struct snd_dmaengine_dai_dma_data *dma_data;
210 dma_data = snd_soc_dai_get_dma_data(dai, substream);
212 /* Working copies of register */
213 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
214 pr_debug("hw_params r: IISMOD: %x\n", iismod);
216 switch (params_width(params)) {
218 iismod &= ~S3C2410_IISMOD_16BIT;
219 dma_data->addr_width = 1;
222 iismod |= S3C2410_IISMOD_16BIT;
223 dma_data->addr_width = 2;
229 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
230 pr_debug("hw_params w: IISMOD: %x\n", iismod);
235 static int s3c24xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
236 struct snd_soc_dai *dai)
241 case SNDRV_PCM_TRIGGER_START:
242 case SNDRV_PCM_TRIGGER_RESUME:
243 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
244 if (!s3c24xx_snd_is_clkmaster()) {
245 ret = s3c24xx_snd_lrsync();
250 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
251 s3c24xx_snd_rxctrl(1);
253 s3c24xx_snd_txctrl(1);
256 case SNDRV_PCM_TRIGGER_STOP:
257 case SNDRV_PCM_TRIGGER_SUSPEND:
258 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
259 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
260 s3c24xx_snd_rxctrl(0);
262 s3c24xx_snd_txctrl(0);
274 * Set S3C24xx Clock source
276 static int s3c24xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
277 int clk_id, unsigned int freq, int dir)
279 u32 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
281 iismod &= ~S3C2440_IISMOD_MPLL;
284 case S3C24XX_CLKSRC_PCLK:
286 case S3C24XX_CLKSRC_MPLL:
287 iismod |= S3C2440_IISMOD_MPLL;
293 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
298 * Set S3C24xx Clock dividers
300 static int s3c24xx_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
306 case S3C24XX_DIV_BCLK:
307 reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2410_IISMOD_FS_MASK;
308 writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
310 case S3C24XX_DIV_MCLK:
311 reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~(S3C2410_IISMOD_384FS);
312 writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
314 case S3C24XX_DIV_PRESCALER:
315 writel(div, s3c24xx_i2s.regs + S3C2410_IISPSR);
316 reg = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
317 writel(reg | S3C2410_IISCON_PSCEN, s3c24xx_i2s.regs + S3C2410_IISCON);
327 * To avoid duplicating clock code, allow machine driver to
328 * get the clockrate from here.
330 u32 s3c24xx_i2s_get_clockrate(void)
332 return clk_get_rate(s3c24xx_i2s.iis_clk);
334 EXPORT_SYMBOL_GPL(s3c24xx_i2s_get_clockrate);
336 static int s3c24xx_i2s_probe(struct snd_soc_dai *dai)
339 snd_soc_dai_init_dma_data(dai, &s3c24xx_i2s_pcm_stereo_out,
340 &s3c24xx_i2s_pcm_stereo_in);
342 s3c24xx_i2s.iis_clk = devm_clk_get(dai->dev, "iis");
343 if (IS_ERR(s3c24xx_i2s.iis_clk)) {
344 pr_err("failed to get iis_clock\n");
345 return PTR_ERR(s3c24xx_i2s.iis_clk);
347 ret = clk_prepare_enable(s3c24xx_i2s.iis_clk);
351 /* Configure the I2S pins (GPE0...GPE4) in correct mode */
352 s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
355 writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON);
357 s3c24xx_snd_txctrl(0);
358 s3c24xx_snd_rxctrl(0);
364 static int s3c24xx_i2s_suspend(struct snd_soc_component *component)
366 s3c24xx_i2s.iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
367 s3c24xx_i2s.iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
368 s3c24xx_i2s.iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
369 s3c24xx_i2s.iispsr = readl(s3c24xx_i2s.regs + S3C2410_IISPSR);
371 clk_disable_unprepare(s3c24xx_i2s.iis_clk);
376 static int s3c24xx_i2s_resume(struct snd_soc_component *component)
380 ret = clk_prepare_enable(s3c24xx_i2s.iis_clk);
384 writel(s3c24xx_i2s.iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
385 writel(s3c24xx_i2s.iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
386 writel(s3c24xx_i2s.iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
387 writel(s3c24xx_i2s.iispsr, s3c24xx_i2s.regs + S3C2410_IISPSR);
392 #define s3c24xx_i2s_suspend NULL
393 #define s3c24xx_i2s_resume NULL
396 #define S3C24XX_I2S_RATES \
397 (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
398 SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
399 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
401 static const struct snd_soc_dai_ops s3c24xx_i2s_dai_ops = {
402 .trigger = s3c24xx_i2s_trigger,
403 .hw_params = s3c24xx_i2s_hw_params,
404 .set_fmt = s3c24xx_i2s_set_fmt,
405 .set_clkdiv = s3c24xx_i2s_set_clkdiv,
406 .set_sysclk = s3c24xx_i2s_set_sysclk,
409 static struct snd_soc_dai_driver s3c24xx_i2s_dai = {
410 .probe = s3c24xx_i2s_probe,
414 .rates = S3C24XX_I2S_RATES,
415 .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
419 .rates = S3C24XX_I2S_RATES,
420 .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
421 .ops = &s3c24xx_i2s_dai_ops,
424 static const struct snd_soc_component_driver s3c24xx_i2s_component = {
425 .name = "s3c24xx-i2s",
426 .suspend = s3c24xx_i2s_suspend,
427 .resume = s3c24xx_i2s_resume,
430 static int s3c24xx_iis_dev_probe(struct platform_device *pdev)
432 struct resource *res;
435 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
436 s3c24xx_i2s.regs = devm_ioremap_resource(&pdev->dev, res);
437 if (IS_ERR(s3c24xx_i2s.regs))
438 return PTR_ERR(s3c24xx_i2s.regs);
440 s3c24xx_i2s_pcm_stereo_out.addr = res->start + S3C2410_IISFIFO;
441 s3c24xx_i2s_pcm_stereo_in.addr = res->start + S3C2410_IISFIFO;
443 ret = samsung_asoc_dma_platform_register(&pdev->dev, NULL,
446 dev_err(&pdev->dev, "Failed to register the DMA: %d\n", ret);
450 ret = devm_snd_soc_register_component(&pdev->dev,
451 &s3c24xx_i2s_component, &s3c24xx_i2s_dai, 1);
453 dev_err(&pdev->dev, "Failed to register the DAI\n");
458 static struct platform_driver s3c24xx_iis_driver = {
459 .probe = s3c24xx_iis_dev_probe,
461 .name = "s3c24xx-iis",
465 module_platform_driver(s3c24xx_iis_driver);
467 /* Module information */
468 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
469 MODULE_DESCRIPTION("s3c24xx I2S SoC Interface");
470 MODULE_LICENSE("GPL");
471 MODULE_ALIAS("platform:s3c24xx-iis");