1 // SPDX-License-Identifier: GPL-2.0-only
2 /* sound/soc/rockchip/rk_spdif.c
4 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
6 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
7 * Author: Jianqun <jay.xu@rock-chips.com>
8 * Copyright (c) 2015 Collabora Ltd.
9 * Author: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/of_gpio.h>
15 #include <linux/clk.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/regmap.h>
19 #include <sound/pcm_params.h>
20 #include <sound/dmaengine_pcm.h>
22 #include "rockchip_spdif.h"
31 #define RK3288_GRF_SOC_CON2 0x24c
39 struct snd_dmaengine_dai_dma_data playback_dma_data;
41 struct regmap *regmap;
44 static const struct of_device_id rk_spdif_match[] = {
45 { .compatible = "rockchip,rk3066-spdif",
46 .data = (void *)RK_SPDIF_RK3066 },
47 { .compatible = "rockchip,rk3188-spdif",
48 .data = (void *)RK_SPDIF_RK3188 },
49 { .compatible = "rockchip,rk3228-spdif",
50 .data = (void *)RK_SPDIF_RK3366 },
51 { .compatible = "rockchip,rk3288-spdif",
52 .data = (void *)RK_SPDIF_RK3288 },
53 { .compatible = "rockchip,rk3328-spdif",
54 .data = (void *)RK_SPDIF_RK3366 },
55 { .compatible = "rockchip,rk3366-spdif",
56 .data = (void *)RK_SPDIF_RK3366 },
57 { .compatible = "rockchip,rk3368-spdif",
58 .data = (void *)RK_SPDIF_RK3366 },
59 { .compatible = "rockchip,rk3399-spdif",
60 .data = (void *)RK_SPDIF_RK3366 },
63 MODULE_DEVICE_TABLE(of, rk_spdif_match);
65 static int __maybe_unused rk_spdif_runtime_suspend(struct device *dev)
67 struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
69 regcache_cache_only(spdif->regmap, true);
70 clk_disable_unprepare(spdif->mclk);
71 clk_disable_unprepare(spdif->hclk);
76 static int __maybe_unused rk_spdif_runtime_resume(struct device *dev)
78 struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
81 ret = clk_prepare_enable(spdif->mclk);
83 dev_err(spdif->dev, "mclk clock enable failed %d\n", ret);
87 ret = clk_prepare_enable(spdif->hclk);
89 dev_err(spdif->dev, "hclk clock enable failed %d\n", ret);
93 regcache_cache_only(spdif->regmap, false);
94 regcache_mark_dirty(spdif->regmap);
96 ret = regcache_sync(spdif->regmap);
98 clk_disable_unprepare(spdif->mclk);
99 clk_disable_unprepare(spdif->hclk);
105 static int rk_spdif_hw_params(struct snd_pcm_substream *substream,
106 struct snd_pcm_hw_params *params,
107 struct snd_soc_dai *dai)
109 struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
110 unsigned int val = SPDIF_CFGR_HALFWORD_ENABLE;
114 srate = params_rate(params);
117 switch (params_format(params)) {
118 case SNDRV_PCM_FORMAT_S16_LE:
119 val |= SPDIF_CFGR_VDW_16;
121 case SNDRV_PCM_FORMAT_S20_3LE:
122 val |= SPDIF_CFGR_VDW_20;
124 case SNDRV_PCM_FORMAT_S24_LE:
125 val |= SPDIF_CFGR_VDW_24;
131 /* Set clock and calculate divider */
132 ret = clk_set_rate(spdif->mclk, mclk);
134 dev_err(spdif->dev, "Failed to set module clock rate: %d\n",
139 ret = regmap_update_bits(spdif->regmap, SPDIF_CFGR,
140 SPDIF_CFGR_CLK_DIV_MASK | SPDIF_CFGR_HALFWORD_ENABLE |
147 static int rk_spdif_trigger(struct snd_pcm_substream *substream,
148 int cmd, struct snd_soc_dai *dai)
150 struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
154 case SNDRV_PCM_TRIGGER_START:
155 case SNDRV_PCM_TRIGGER_RESUME:
156 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
157 ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
158 SPDIF_DMACR_TDE_ENABLE |
159 SPDIF_DMACR_TDL_MASK,
160 SPDIF_DMACR_TDE_ENABLE |
161 SPDIF_DMACR_TDL(16));
166 ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
167 SPDIF_XFER_TXS_START,
168 SPDIF_XFER_TXS_START);
170 case SNDRV_PCM_TRIGGER_SUSPEND:
171 case SNDRV_PCM_TRIGGER_STOP:
172 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
173 ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
174 SPDIF_DMACR_TDE_ENABLE,
175 SPDIF_DMACR_TDE_DISABLE);
180 ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
181 SPDIF_XFER_TXS_START,
182 SPDIF_XFER_TXS_STOP);
192 static int rk_spdif_dai_probe(struct snd_soc_dai *dai)
194 struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
196 dai->playback_dma_data = &spdif->playback_dma_data;
201 static const struct snd_soc_dai_ops rk_spdif_dai_ops = {
202 .hw_params = rk_spdif_hw_params,
203 .trigger = rk_spdif_trigger,
206 static struct snd_soc_dai_driver rk_spdif_dai = {
207 .probe = rk_spdif_dai_probe,
209 .stream_name = "Playback",
212 .rates = (SNDRV_PCM_RATE_32000 |
213 SNDRV_PCM_RATE_44100 |
214 SNDRV_PCM_RATE_48000 |
215 SNDRV_PCM_RATE_96000 |
216 SNDRV_PCM_RATE_192000),
217 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
218 SNDRV_PCM_FMTBIT_S20_3LE |
219 SNDRV_PCM_FMTBIT_S24_LE),
221 .ops = &rk_spdif_dai_ops,
224 static const struct snd_soc_component_driver rk_spdif_component = {
225 .name = "rockchip-spdif",
228 static bool rk_spdif_wr_reg(struct device *dev, unsigned int reg)
242 static bool rk_spdif_rd_reg(struct device *dev, unsigned int reg)
256 static bool rk_spdif_volatile_reg(struct device *dev, unsigned int reg)
267 static const struct regmap_config rk_spdif_regmap_config = {
271 .max_register = SPDIF_SMPDR,
272 .writeable_reg = rk_spdif_wr_reg,
273 .readable_reg = rk_spdif_rd_reg,
274 .volatile_reg = rk_spdif_volatile_reg,
275 .cache_type = REGCACHE_FLAT,
278 static int rk_spdif_probe(struct platform_device *pdev)
280 struct device_node *np = pdev->dev.of_node;
281 struct rk_spdif_dev *spdif;
282 const struct of_device_id *match;
283 struct resource *res;
287 match = of_match_node(rk_spdif_match, np);
288 if (match->data == (void *)RK_SPDIF_RK3288) {
291 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
294 "rockchip_spdif missing 'rockchip,grf' \n");
298 /* Select the 8 channel SPDIF solution on RK3288 as
299 * the 2 channel one does not appear to work
301 regmap_write(grf, RK3288_GRF_SOC_CON2, BIT(1) << 16);
304 spdif = devm_kzalloc(&pdev->dev, sizeof(*spdif), GFP_KERNEL);
308 spdif->hclk = devm_clk_get(&pdev->dev, "hclk");
309 if (IS_ERR(spdif->hclk)) {
310 dev_err(&pdev->dev, "Can't retrieve rk_spdif bus clock\n");
311 return PTR_ERR(spdif->hclk);
313 ret = clk_prepare_enable(spdif->hclk);
315 dev_err(spdif->dev, "hclock enable failed %d\n", ret);
319 spdif->mclk = devm_clk_get(&pdev->dev, "mclk");
320 if (IS_ERR(spdif->mclk)) {
321 dev_err(&pdev->dev, "Can't retrieve rk_spdif master clock\n");
322 ret = PTR_ERR(spdif->mclk);
323 goto err_disable_hclk;
326 ret = clk_prepare_enable(spdif->mclk);
328 dev_err(spdif->dev, "clock enable failed %d\n", ret);
329 goto err_disable_clocks;
332 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
333 regs = devm_ioremap_resource(&pdev->dev, res);
336 goto err_disable_clocks;
339 spdif->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "hclk", regs,
340 &rk_spdif_regmap_config);
341 if (IS_ERR(spdif->regmap)) {
343 "Failed to initialise managed register map\n");
344 ret = PTR_ERR(spdif->regmap);
345 goto err_disable_clocks;
348 spdif->playback_dma_data.addr = res->start + SPDIF_SMPDR;
349 spdif->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
350 spdif->playback_dma_data.maxburst = 4;
352 spdif->dev = &pdev->dev;
353 dev_set_drvdata(&pdev->dev, spdif);
355 pm_runtime_set_active(&pdev->dev);
356 pm_runtime_enable(&pdev->dev);
357 pm_request_idle(&pdev->dev);
359 ret = devm_snd_soc_register_component(&pdev->dev,
363 dev_err(&pdev->dev, "Could not register DAI\n");
367 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
369 dev_err(&pdev->dev, "Could not register PCM\n");
376 pm_runtime_disable(&pdev->dev);
378 clk_disable_unprepare(spdif->mclk);
380 clk_disable_unprepare(spdif->hclk);
385 static int rk_spdif_remove(struct platform_device *pdev)
387 struct rk_spdif_dev *spdif = dev_get_drvdata(&pdev->dev);
389 pm_runtime_disable(&pdev->dev);
390 if (!pm_runtime_status_suspended(&pdev->dev))
391 rk_spdif_runtime_suspend(&pdev->dev);
393 clk_disable_unprepare(spdif->mclk);
394 clk_disable_unprepare(spdif->hclk);
399 static const struct dev_pm_ops rk_spdif_pm_ops = {
400 SET_RUNTIME_PM_OPS(rk_spdif_runtime_suspend, rk_spdif_runtime_resume,
404 static struct platform_driver rk_spdif_driver = {
405 .probe = rk_spdif_probe,
406 .remove = rk_spdif_remove,
408 .name = "rockchip-spdif",
409 .of_match_table = of_match_ptr(rk_spdif_match),
410 .pm = &rk_spdif_pm_ops,
413 module_platform_driver(rk_spdif_driver);
415 MODULE_ALIAS("platform:rockchip-spdif");
416 MODULE_DESCRIPTION("ROCKCHIP SPDIF transceiver Interface");
417 MODULE_AUTHOR("Sjoerd Simons <sjoerd.simons@collabora.co.uk>");
418 MODULE_LICENSE("GPL v2");