1 // SPDX-License-Identifier: GPL-2.0-only
2 /* sound/soc/rockchip/rockchip_i2s.c
4 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
6 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
7 * Author: Jianqun <jay.xu@rock-chips.com>
10 #include <linux/module.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/delay.h>
13 #include <linux/of_gpio.h>
14 #include <linux/of_device.h>
15 #include <linux/clk.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/spinlock.h>
19 #include <sound/pcm_params.h>
20 #include <sound/dmaengine_pcm.h>
22 #include "rockchip_i2s.h"
24 #define DRV_NAME "rockchip-i2s"
37 struct snd_dmaengine_dai_dma_data capture_dma_data;
38 struct snd_dmaengine_dai_dma_data playback_dma_data;
40 struct regmap *regmap;
47 * Used to indicate the tx/rx status.
48 * I2S controller hopes to start the tx and rx together,
49 * also to stop them when they are both try to stop.
54 const struct rk_i2s_pins *pins;
55 unsigned int bclk_ratio;
56 spinlock_t lock; /* tx/rx lock */
59 static int i2s_runtime_suspend(struct device *dev)
61 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
63 regcache_cache_only(i2s->regmap, true);
64 clk_disable_unprepare(i2s->mclk);
69 static int i2s_runtime_resume(struct device *dev)
71 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
74 ret = clk_prepare_enable(i2s->mclk);
76 dev_err(i2s->dev, "clock enable failed %d\n", ret);
80 regcache_cache_only(i2s->regmap, false);
81 regcache_mark_dirty(i2s->regmap);
83 ret = regcache_sync(i2s->regmap);
85 clk_disable_unprepare(i2s->mclk);
90 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
92 return snd_soc_dai_get_drvdata(dai);
95 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
100 spin_lock(&i2s->lock);
102 regmap_update_bits(i2s->regmap, I2S_DMACR,
103 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
105 regmap_update_bits(i2s->regmap, I2S_XFER,
106 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
107 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
109 i2s->tx_start = true;
111 i2s->tx_start = false;
113 regmap_update_bits(i2s->regmap, I2S_DMACR,
114 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
116 if (!i2s->rx_start) {
117 regmap_update_bits(i2s->regmap, I2S_XFER,
124 regmap_update_bits(i2s->regmap, I2S_CLR,
125 I2S_CLR_TXC | I2S_CLR_RXC,
126 I2S_CLR_TXC | I2S_CLR_RXC);
128 regmap_read(i2s->regmap, I2S_CLR, &val);
130 /* Should wait for clear operation to finish */
132 regmap_read(i2s->regmap, I2S_CLR, &val);
135 dev_warn(i2s->dev, "fail to clear\n");
141 spin_unlock(&i2s->lock);
144 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
146 unsigned int val = 0;
149 spin_lock(&i2s->lock);
151 regmap_update_bits(i2s->regmap, I2S_DMACR,
152 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
154 regmap_update_bits(i2s->regmap, I2S_XFER,
155 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
156 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
158 i2s->rx_start = true;
160 i2s->rx_start = false;
162 regmap_update_bits(i2s->regmap, I2S_DMACR,
163 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
165 if (!i2s->tx_start) {
166 regmap_update_bits(i2s->regmap, I2S_XFER,
173 regmap_update_bits(i2s->regmap, I2S_CLR,
174 I2S_CLR_TXC | I2S_CLR_RXC,
175 I2S_CLR_TXC | I2S_CLR_RXC);
177 regmap_read(i2s->regmap, I2S_CLR, &val);
179 /* Should wait for clear operation to finish */
181 regmap_read(i2s->regmap, I2S_CLR, &val);
184 dev_warn(i2s->dev, "fail to clear\n");
190 spin_unlock(&i2s->lock);
193 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
196 struct rk_i2s_dev *i2s = to_info(cpu_dai);
197 unsigned int mask = 0, val = 0;
200 pm_runtime_get_sync(cpu_dai->dev);
201 mask = I2S_CKR_MSS_MASK;
202 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
203 case SND_SOC_DAIFMT_CBS_CFS:
204 /* Set source clock in Master mode */
205 val = I2S_CKR_MSS_MASTER;
206 i2s->is_master_mode = true;
208 case SND_SOC_DAIFMT_CBM_CFM:
209 val = I2S_CKR_MSS_SLAVE;
210 i2s->is_master_mode = false;
217 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
219 mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK;
220 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
221 case SND_SOC_DAIFMT_NB_NF:
222 val = I2S_CKR_CKP_NORMAL |
226 case SND_SOC_DAIFMT_NB_IF:
227 val = I2S_CKR_CKP_NORMAL |
228 I2S_CKR_TLP_INVERTED |
229 I2S_CKR_RLP_INVERTED;
231 case SND_SOC_DAIFMT_IB_NF:
232 val = I2S_CKR_CKP_INVERTED |
236 case SND_SOC_DAIFMT_IB_IF:
237 val = I2S_CKR_CKP_INVERTED |
238 I2S_CKR_TLP_INVERTED |
239 I2S_CKR_RLP_INVERTED;
246 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
248 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
249 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
250 case SND_SOC_DAIFMT_RIGHT_J:
251 val = I2S_TXCR_IBM_RSJM;
253 case SND_SOC_DAIFMT_LEFT_J:
254 val = I2S_TXCR_IBM_LSJM;
256 case SND_SOC_DAIFMT_I2S:
257 val = I2S_TXCR_IBM_NORMAL;
259 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */
260 val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
262 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
263 val = I2S_TXCR_TFS_PCM;
270 regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
272 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
273 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
274 case SND_SOC_DAIFMT_RIGHT_J:
275 val = I2S_RXCR_IBM_RSJM;
277 case SND_SOC_DAIFMT_LEFT_J:
278 val = I2S_RXCR_IBM_LSJM;
280 case SND_SOC_DAIFMT_I2S:
281 val = I2S_RXCR_IBM_NORMAL;
283 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */
284 val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
286 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
287 val = I2S_RXCR_TFS_PCM;
294 regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
297 pm_runtime_put(cpu_dai->dev);
302 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
303 struct snd_pcm_hw_params *params,
304 struct snd_soc_dai *dai)
306 struct rk_i2s_dev *i2s = to_info(dai);
307 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
308 unsigned int val = 0;
309 unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
311 if (i2s->is_master_mode) {
312 mclk_rate = clk_get_rate(i2s->mclk);
313 bclk_rate = i2s->bclk_ratio * params_rate(params);
317 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
318 div_lrck = bclk_rate / params_rate(params);
319 regmap_update_bits(i2s->regmap, I2S_CKR,
321 I2S_CKR_MDIV(div_bclk));
323 regmap_update_bits(i2s->regmap, I2S_CKR,
326 I2S_CKR_TSD(div_lrck) |
327 I2S_CKR_RSD(div_lrck));
330 switch (params_format(params)) {
331 case SNDRV_PCM_FORMAT_S8:
332 val |= I2S_TXCR_VDW(8);
334 case SNDRV_PCM_FORMAT_S16_LE:
335 val |= I2S_TXCR_VDW(16);
337 case SNDRV_PCM_FORMAT_S20_3LE:
338 val |= I2S_TXCR_VDW(20);
340 case SNDRV_PCM_FORMAT_S24_LE:
341 val |= I2S_TXCR_VDW(24);
343 case SNDRV_PCM_FORMAT_S32_LE:
344 val |= I2S_TXCR_VDW(32);
350 switch (params_channels(params)) {
364 dev_err(i2s->dev, "invalid channel: %d\n",
365 params_channels(params));
369 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
370 regmap_update_bits(i2s->regmap, I2S_RXCR,
371 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
374 regmap_update_bits(i2s->regmap, I2S_TXCR,
375 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
378 if (!IS_ERR(i2s->grf) && i2s->pins) {
379 regmap_read(i2s->regmap, I2S_TXCR, &val);
380 val &= I2S_TXCR_CSR_MASK;
384 val = I2S_IO_4CH_OUT_6CH_IN;
387 val = I2S_IO_6CH_OUT_4CH_IN;
390 val = I2S_IO_8CH_OUT_2CH_IN;
393 val = I2S_IO_2CH_OUT_8CH_IN;
397 val <<= i2s->pins->shift;
398 val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16;
399 regmap_write(i2s->grf, i2s->pins->reg_offset, val);
402 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
404 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
407 val = I2S_CKR_TRCM_TXRX;
408 if (dai->driver->symmetric_rate && rtd->dai_link->symmetric_rate)
409 val = I2S_CKR_TRCM_TXONLY;
411 regmap_update_bits(i2s->regmap, I2S_CKR,
417 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
418 int cmd, struct snd_soc_dai *dai)
420 struct rk_i2s_dev *i2s = to_info(dai);
424 case SNDRV_PCM_TRIGGER_START:
425 case SNDRV_PCM_TRIGGER_RESUME:
426 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
427 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
428 rockchip_snd_rxctrl(i2s, 1);
430 rockchip_snd_txctrl(i2s, 1);
432 case SNDRV_PCM_TRIGGER_SUSPEND:
433 case SNDRV_PCM_TRIGGER_STOP:
434 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
435 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
436 rockchip_snd_rxctrl(i2s, 0);
438 rockchip_snd_txctrl(i2s, 0);
448 static int rockchip_i2s_set_bclk_ratio(struct snd_soc_dai *dai,
451 struct rk_i2s_dev *i2s = to_info(dai);
453 i2s->bclk_ratio = ratio;
458 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
459 unsigned int freq, int dir)
461 struct rk_i2s_dev *i2s = to_info(cpu_dai);
467 ret = clk_set_rate(i2s->mclk, freq);
469 dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
474 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
476 struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
478 snd_soc_dai_init_dma_data(dai,
479 i2s->has_playback ? &i2s->playback_dma_data : NULL,
480 i2s->has_capture ? &i2s->capture_dma_data : NULL);
485 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
486 .hw_params = rockchip_i2s_hw_params,
487 .set_bclk_ratio = rockchip_i2s_set_bclk_ratio,
488 .set_sysclk = rockchip_i2s_set_sysclk,
489 .set_fmt = rockchip_i2s_set_fmt,
490 .trigger = rockchip_i2s_trigger,
493 static struct snd_soc_dai_driver rockchip_i2s_dai = {
494 .probe = rockchip_i2s_dai_probe,
495 .ops = &rockchip_i2s_dai_ops,
499 static const struct snd_soc_component_driver rockchip_i2s_component = {
503 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
520 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
540 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
554 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
564 static const struct reg_default rockchip_i2s_reg_defaults[] = {
572 static const struct regmap_config rockchip_i2s_regmap_config = {
576 .max_register = I2S_RXDR,
577 .reg_defaults = rockchip_i2s_reg_defaults,
578 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
579 .writeable_reg = rockchip_i2s_wr_reg,
580 .readable_reg = rockchip_i2s_rd_reg,
581 .volatile_reg = rockchip_i2s_volatile_reg,
582 .precious_reg = rockchip_i2s_precious_reg,
583 .cache_type = REGCACHE_FLAT,
586 static const struct rk_i2s_pins rk3399_i2s_pins = {
587 .reg_offset = 0xe220,
591 static const struct of_device_id rockchip_i2s_match[] __maybe_unused = {
592 { .compatible = "rockchip,px30-i2s", },
593 { .compatible = "rockchip,rk1808-i2s", },
594 { .compatible = "rockchip,rk3036-i2s", },
595 { .compatible = "rockchip,rk3066-i2s", },
596 { .compatible = "rockchip,rk3128-i2s", },
597 { .compatible = "rockchip,rk3188-i2s", },
598 { .compatible = "rockchip,rk3228-i2s", },
599 { .compatible = "rockchip,rk3288-i2s", },
600 { .compatible = "rockchip,rk3308-i2s", },
601 { .compatible = "rockchip,rk3328-i2s", },
602 { .compatible = "rockchip,rk3366-i2s", },
603 { .compatible = "rockchip,rk3368-i2s", },
604 { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
605 { .compatible = "rockchip,rv1126-i2s", },
609 static int rockchip_i2s_init_dai(struct rk_i2s_dev *i2s, struct resource *res,
610 struct snd_soc_dai_driver **dp)
612 struct device_node *node = i2s->dev->of_node;
613 struct snd_soc_dai_driver *dai;
614 struct property *dma_names;
615 const char *dma_name;
618 of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
619 if (!strcmp(dma_name, "tx"))
620 i2s->has_playback = true;
621 if (!strcmp(dma_name, "rx"))
622 i2s->has_capture = true;
625 dai = devm_kmemdup(i2s->dev, &rockchip_i2s_dai,
626 sizeof(*dai), GFP_KERNEL);
630 if (i2s->has_playback) {
631 dai->playback.stream_name = "Playback";
632 dai->playback.channels_min = 2;
633 dai->playback.channels_max = 8;
634 dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
635 dai->playback.formats = SNDRV_PCM_FMTBIT_S8 |
636 SNDRV_PCM_FMTBIT_S16_LE |
637 SNDRV_PCM_FMTBIT_S20_3LE |
638 SNDRV_PCM_FMTBIT_S24_LE |
639 SNDRV_PCM_FMTBIT_S32_LE;
641 i2s->playback_dma_data.addr = res->start + I2S_TXDR;
642 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
643 i2s->playback_dma_data.maxburst = 8;
645 if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
646 if (val >= 2 && val <= 8)
647 dai->playback.channels_max = val;
651 if (i2s->has_capture) {
652 dai->capture.stream_name = "Capture";
653 dai->capture.channels_min = 2;
654 dai->capture.channels_max = 8;
655 dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
656 dai->capture.formats = SNDRV_PCM_FMTBIT_S8 |
657 SNDRV_PCM_FMTBIT_S16_LE |
658 SNDRV_PCM_FMTBIT_S20_3LE |
659 SNDRV_PCM_FMTBIT_S24_LE |
660 SNDRV_PCM_FMTBIT_S32_LE;
662 i2s->capture_dma_data.addr = res->start + I2S_RXDR;
663 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
664 i2s->capture_dma_data.maxburst = 8;
666 if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
667 if (val >= 2 && val <= 8)
668 dai->capture.channels_max = val;
678 static int rockchip_i2s_probe(struct platform_device *pdev)
680 struct device_node *node = pdev->dev.of_node;
681 const struct of_device_id *of_id;
682 struct rk_i2s_dev *i2s;
683 struct snd_soc_dai_driver *dai;
684 struct resource *res;
688 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
692 spin_lock_init(&i2s->lock);
693 i2s->dev = &pdev->dev;
695 i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
696 if (!IS_ERR(i2s->grf)) {
697 of_id = of_match_device(rockchip_i2s_match, &pdev->dev);
698 if (!of_id || !of_id->data)
701 i2s->pins = of_id->data;
704 /* try to prepare related clocks */
705 i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
706 if (IS_ERR(i2s->hclk)) {
707 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
708 return PTR_ERR(i2s->hclk);
710 ret = clk_prepare_enable(i2s->hclk);
712 dev_err(i2s->dev, "hclock enable failed %d\n", ret);
716 i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
717 if (IS_ERR(i2s->mclk)) {
718 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
719 ret = PTR_ERR(i2s->mclk);
723 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
729 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
730 &rockchip_i2s_regmap_config);
731 if (IS_ERR(i2s->regmap)) {
733 "Failed to initialise managed register map\n");
734 ret = PTR_ERR(i2s->regmap);
738 i2s->bclk_ratio = 64;
740 dev_set_drvdata(&pdev->dev, i2s);
742 pm_runtime_enable(&pdev->dev);
743 if (!pm_runtime_enabled(&pdev->dev)) {
744 ret = i2s_runtime_resume(&pdev->dev);
749 ret = rockchip_i2s_init_dai(i2s, res, &dai);
753 ret = devm_snd_soc_register_component(&pdev->dev,
754 &rockchip_i2s_component,
758 dev_err(&pdev->dev, "Could not register DAI\n");
762 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
764 dev_err(&pdev->dev, "Could not register PCM\n");
771 if (!pm_runtime_status_suspended(&pdev->dev))
772 i2s_runtime_suspend(&pdev->dev);
774 pm_runtime_disable(&pdev->dev);
776 clk_disable_unprepare(i2s->hclk);
780 static int rockchip_i2s_remove(struct platform_device *pdev)
782 struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
784 pm_runtime_disable(&pdev->dev);
785 if (!pm_runtime_status_suspended(&pdev->dev))
786 i2s_runtime_suspend(&pdev->dev);
788 clk_disable_unprepare(i2s->hclk);
793 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
794 SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
798 static struct platform_driver rockchip_i2s_driver = {
799 .probe = rockchip_i2s_probe,
800 .remove = rockchip_i2s_remove,
803 .of_match_table = of_match_ptr(rockchip_i2s_match),
804 .pm = &rockchip_i2s_pm_ops,
807 module_platform_driver(rockchip_i2s_driver);
809 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
810 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
811 MODULE_LICENSE("GPL v2");
812 MODULE_ALIAS("platform:" DRV_NAME);
813 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);