sound/soc/rockchip/rockchip_i2s.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* sound/soc/rockchip/rockchip_i2s.c
   3  *
   4  * ALSA SoC Audio Layer - Rockchip I2S Controller driver
   5  *
   6  * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
   7  * Author: Jianqun <jay.xu@rock-chips.com>
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/mfd/syscon.h>
  12 #include <linux/delay.h>
  13 #include <linux/of_gpio.h>
  14 #include <linux/of_device.h>
  15 #include <linux/clk.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/regmap.h>
  18 #include <linux/spinlock.h>
  19 #include <sound/pcm_params.h>
  20 #include <sound/dmaengine_pcm.h>
  21
  22 #include "rockchip_i2s.h"
  23
  24 #define DRV_NAME "rockchip-i2s"
  25
  26 struct rk_i2s_pins {
  27         u32 reg_offset;
  28         u32 shift;
  29 };
  30
  31 struct rk_i2s_dev {
  32         struct device *dev;
  33
  34         struct clk *hclk;
  35         struct clk *mclk;
  36
  37         struct snd_dmaengine_dai_dma_data capture_dma_data;
  38         struct snd_dmaengine_dai_dma_data playback_dma_data;
  39
  40         struct regmap *regmap;
  41         struct regmap *grf;
  42
  43         bool has_capture;
  44         bool has_playback;
  45
  46 /*
  47  * Used to indicate the tx/rx status.
  48  * I2S controller hopes to start the tx and rx together,
  49  * also to stop them when they are both try to stop.
  50 */
  51         bool tx_start;
  52         bool rx_start;
  53         bool is_master_mode;
  54         const struct rk_i2s_pins *pins;
  55         unsigned int bclk_ratio;
  56         spinlock_t lock; /* tx/rx lock */
  57 };
  58
  59 static int i2s_runtime_suspend(struct device *dev)
  60 {
  61         struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
  62
  63         regcache_cache_only(i2s->regmap, true);
  64         clk_disable_unprepare(i2s->mclk);
  65
  66         return 0;
  67 }
  68
  69 static int i2s_runtime_resume(struct device *dev)
  70 {
  71         struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
  72         int ret;
  73
  74         ret = clk_prepare_enable(i2s->mclk);
  75         if (ret) {
  76                 dev_err(i2s->dev, "clock enable failed %d\n", ret);
  77                 return ret;
  78         }
  79
  80         regcache_cache_only(i2s->regmap, false);
  81         regcache_mark_dirty(i2s->regmap);
  82
  83         ret = regcache_sync(i2s->regmap);
  84         if (ret)
  85                 clk_disable_unprepare(i2s->mclk);
  86
  87         return ret;
  88 }
  89
  90 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
  91 {
  92         return snd_soc_dai_get_drvdata(dai);
  93 }
  94
  95 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
  96 {
  97         unsigned int val = 0;
  98         int retry = 10;
  99
 100         spin_lock(&i2s->lock);
 101         if (on) {
 102                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 103                                    I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
 104
 105                 regmap_update_bits(i2s->regmap, I2S_XFER,
 106                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START,
 107                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START);
 108
 109                 i2s->tx_start = true;
 110         } else {
 111                 i2s->tx_start = false;
 112
 113                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 114                                    I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
 115
 116                 if (!i2s->rx_start) {
 117                         regmap_update_bits(i2s->regmap, I2S_XFER,
 118                                            I2S_XFER_TXS_START |
 119                                            I2S_XFER_RXS_START,
 120                                            I2S_XFER_TXS_STOP |
 121                                            I2S_XFER_RXS_STOP);
 122
 123                         udelay(150);
 124                         regmap_update_bits(i2s->regmap, I2S_CLR,
 125                                            I2S_CLR_TXC | I2S_CLR_RXC,
 126                                            I2S_CLR_TXC | I2S_CLR_RXC);
 127
 128                         regmap_read(i2s->regmap, I2S_CLR, &val);
 129
 130                         /* Should wait for clear operation to finish */
 131                         while (val) {
 132                                 regmap_read(i2s->regmap, I2S_CLR, &val);
 133                                 retry--;
 134                                 if (!retry) {
 135                                         dev_warn(i2s->dev, "fail to clear\n");
 136                                         break;
 137                                 }
 138                         }
 139                 }
 140         }
 141         spin_unlock(&i2s->lock);
 142 }
 143
 144 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
 145 {
 146         unsigned int val = 0;
 147         int retry = 10;
 148
 149         spin_lock(&i2s->lock);
 150         if (on) {
 151                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 152                                    I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
 153
 154                 regmap_update_bits(i2s->regmap, I2S_XFER,
 155                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START,
 156                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START);
 157
 158                 i2s->rx_start = true;
 159         } else {
 160                 i2s->rx_start = false;
 161
 162                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 163                                    I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
 164
 165                 if (!i2s->tx_start) {
 166                         regmap_update_bits(i2s->regmap, I2S_XFER,
 167                                            I2S_XFER_TXS_START |
 168                                            I2S_XFER_RXS_START,
 169                                            I2S_XFER_TXS_STOP |
 170                                            I2S_XFER_RXS_STOP);
 171
 172                         udelay(150);
 173                         regmap_update_bits(i2s->regmap, I2S_CLR,
 174                                            I2S_CLR_TXC | I2S_CLR_RXC,
 175                                            I2S_CLR_TXC | I2S_CLR_RXC);
 176
 177                         regmap_read(i2s->regmap, I2S_CLR, &val);
 178
 179                         /* Should wait for clear operation to finish */
 180                         while (val) {
 181                                 regmap_read(i2s->regmap, I2S_CLR, &val);
 182                                 retry--;
 183                                 if (!retry) {
 184                                         dev_warn(i2s->dev, "fail to clear\n");
 185                                         break;
 186                                 }
 187                         }
 188                 }
 189         }
 190         spin_unlock(&i2s->lock);
 191 }
 192
 193 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
 194                                 unsigned int fmt)
 195 {
 196         struct rk_i2s_dev *i2s = to_info(cpu_dai);
 197         unsigned int mask = 0, val = 0;
 198         int ret = 0;
 199
 200         pm_runtime_get_sync(cpu_dai->dev);
 201         mask = I2S_CKR_MSS_MASK;
 202         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 203         case SND_SOC_DAIFMT_CBS_CFS:
 204                 /* Set source clock in Master mode */
 205                 val = I2S_CKR_MSS_MASTER;
 206                 i2s->is_master_mode = true;
 207                 break;
 208         case SND_SOC_DAIFMT_CBM_CFM:
 209                 val = I2S_CKR_MSS_SLAVE;
 210                 i2s->is_master_mode = false;
 211                 break;
 212         default:
 213                 ret = -EINVAL;
 214                 goto err_pm_put;
 215         }
 216
 217         regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
 218
 219         mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK;
 220         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 221         case SND_SOC_DAIFMT_NB_NF:
 222                 val = I2S_CKR_CKP_NORMAL |
 223                       I2S_CKR_TLP_NORMAL |
 224                       I2S_CKR_RLP_NORMAL;
 225                 break;
 226         case SND_SOC_DAIFMT_NB_IF:
 227                 val = I2S_CKR_CKP_NORMAL |
 228                       I2S_CKR_TLP_INVERTED |
 229                       I2S_CKR_RLP_INVERTED;
 230                 break;
 231         case SND_SOC_DAIFMT_IB_NF:
 232                 val = I2S_CKR_CKP_INVERTED |
 233                       I2S_CKR_TLP_NORMAL |
 234                       I2S_CKR_RLP_NORMAL;
 235                 break;
 236         case SND_SOC_DAIFMT_IB_IF:
 237                 val = I2S_CKR_CKP_INVERTED |
 238                       I2S_CKR_TLP_INVERTED |
 239                       I2S_CKR_RLP_INVERTED;
 240                 break;
 241         default:
 242                 ret = -EINVAL;
 243                 goto err_pm_put;
 244         }
 245
 246         regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
 247
 248         mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
 249         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 250         case SND_SOC_DAIFMT_RIGHT_J:
 251                 val = I2S_TXCR_IBM_RSJM;
 252                 break;
 253         case SND_SOC_DAIFMT_LEFT_J:
 254                 val = I2S_TXCR_IBM_LSJM;
 255                 break;
 256         case SND_SOC_DAIFMT_I2S:
 257                 val = I2S_TXCR_IBM_NORMAL;
 258                 break;
 259         case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */
 260                 val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
 261                 break;
 262         case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
 263                 val = I2S_TXCR_TFS_PCM;
 264                 break;
 265         default:
 266                 ret = -EINVAL;
 267                 goto err_pm_put;
 268         }
 269
 270         regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
 271
 272         mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
 273         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 274         case SND_SOC_DAIFMT_RIGHT_J:
 275                 val = I2S_RXCR_IBM_RSJM;
 276                 break;
 277         case SND_SOC_DAIFMT_LEFT_J:
 278                 val = I2S_RXCR_IBM_LSJM;
 279                 break;
 280         case SND_SOC_DAIFMT_I2S:
 281                 val = I2S_RXCR_IBM_NORMAL;
 282                 break;
 283         case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */
 284                 val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
 285                 break;
 286         case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
 287                 val = I2S_RXCR_TFS_PCM;
 288                 break;
 289         default:
 290                 ret = -EINVAL;
 291                 goto err_pm_put;
 292         }
 293
 294         regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
 295
 296 err_pm_put:
 297         pm_runtime_put(cpu_dai->dev);
 298
 299         return ret;
 300 }
 301
 302 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
 303                                   struct snd_pcm_hw_params *params,
 304                                   struct snd_soc_dai *dai)
 305 {
 306         struct rk_i2s_dev *i2s = to_info(dai);
 307         struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
 308         unsigned int val = 0;
 309         unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
 310
 311         if (i2s->is_master_mode) {
 312                 mclk_rate = clk_get_rate(i2s->mclk);
 313                 bclk_rate = i2s->bclk_ratio * params_rate(params);
 314                 if (!bclk_rate)
 315                         return -EINVAL;
 316
 317                 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
 318                 div_lrck = bclk_rate / params_rate(params);
 319                 regmap_update_bits(i2s->regmap, I2S_CKR,
 320                                    I2S_CKR_MDIV_MASK,
 321                                    I2S_CKR_MDIV(div_bclk));
 322
 323                 regmap_update_bits(i2s->regmap, I2S_CKR,
 324                                    I2S_CKR_TSD_MASK |
 325                                    I2S_CKR_RSD_MASK,
 326                                    I2S_CKR_TSD(div_lrck) |
 327                                    I2S_CKR_RSD(div_lrck));
 328         }
 329
 330         switch (params_format(params)) {
 331         case SNDRV_PCM_FORMAT_S8:
 332                 val |= I2S_TXCR_VDW(8);
 333                 break;
 334         case SNDRV_PCM_FORMAT_S16_LE:
 335                 val |= I2S_TXCR_VDW(16);
 336                 break;
 337         case SNDRV_PCM_FORMAT_S20_3LE:
 338                 val |= I2S_TXCR_VDW(20);
 339                 break;
 340         case SNDRV_PCM_FORMAT_S24_LE:
 341                 val |= I2S_TXCR_VDW(24);
 342                 break;
 343         case SNDRV_PCM_FORMAT_S32_LE:
 344                 val |= I2S_TXCR_VDW(32);
 345                 break;
 346         default:
 347                 return -EINVAL;
 348         }
 349
 350         switch (params_channels(params)) {
 351         case 8:
 352                 val |= I2S_CHN_8;
 353                 break;
 354         case 6:
 355                 val |= I2S_CHN_6;
 356                 break;
 357         case 4:
 358                 val |= I2S_CHN_4;
 359                 break;
 360         case 2:
 361                 val |= I2S_CHN_2;
 362                 break;
 363         default:
 364                 dev_err(i2s->dev, "invalid channel: %d\n",
 365                         params_channels(params));
 366                 return -EINVAL;
 367         }
 368
 369         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 370                 regmap_update_bits(i2s->regmap, I2S_RXCR,
 371                                    I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
 372                                    val);
 373         else
 374                 regmap_update_bits(i2s->regmap, I2S_TXCR,
 375                                    I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
 376                                    val);
 377
 378         if (!IS_ERR(i2s->grf) && i2s->pins) {
 379                 regmap_read(i2s->regmap, I2S_TXCR, &val);
 380                 val &= I2S_TXCR_CSR_MASK;
 381
 382                 switch (val) {
 383                 case I2S_CHN_4:
 384                         val = I2S_IO_4CH_OUT_6CH_IN;
 385                         break;
 386                 case I2S_CHN_6:
 387                         val = I2S_IO_6CH_OUT_4CH_IN;
 388                         break;
 389                 case I2S_CHN_8:
 390                         val = I2S_IO_8CH_OUT_2CH_IN;
 391                         break;
 392                 default:
 393                         val = I2S_IO_2CH_OUT_8CH_IN;
 394                         break;
 395                 }
 396
 397                 val <<= i2s->pins->shift;
 398                 val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16;
 399                 regmap_write(i2s->grf, i2s->pins->reg_offset, val);
 400         }
 401
 402         regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
 403                            I2S_DMACR_TDL(16));
 404         regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
 405                            I2S_DMACR_RDL(16));
 406
 407         val = I2S_CKR_TRCM_TXRX;
 408         if (dai->driver->symmetric_rate && rtd->dai_link->symmetric_rate)
 409                 val = I2S_CKR_TRCM_TXONLY;
 410
 411         regmap_update_bits(i2s->regmap, I2S_CKR,
 412                            I2S_CKR_TRCM_MASK,
 413                            val);
 414         return 0;
 415 }
 416
 417 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
 418                                 int cmd, struct snd_soc_dai *dai)
 419 {
 420         struct rk_i2s_dev *i2s = to_info(dai);
 421         int ret = 0;
 422
 423         switch (cmd) {
 424         case SNDRV_PCM_TRIGGER_START:
 425         case SNDRV_PCM_TRIGGER_RESUME:
 426         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 427                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 428                         rockchip_snd_rxctrl(i2s, 1);
 429                 else
 430                         rockchip_snd_txctrl(i2s, 1);
 431                 break;
 432         case SNDRV_PCM_TRIGGER_SUSPEND:
 433         case SNDRV_PCM_TRIGGER_STOP:
 434         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 435                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 436                         rockchip_snd_rxctrl(i2s, 0);
 437                 else
 438                         rockchip_snd_txctrl(i2s, 0);
 439                 break;
 440         default:
 441                 ret = -EINVAL;
 442                 break;
 443         }
 444
 445         return ret;
 446 }
 447
 448 static int rockchip_i2s_set_bclk_ratio(struct snd_soc_dai *dai,
 449                                        unsigned int ratio)
 450 {
 451         struct rk_i2s_dev *i2s = to_info(dai);
 452
 453         i2s->bclk_ratio = ratio;
 454
 455         return 0;
 456 }
 457
 458 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
 459                                    unsigned int freq, int dir)
 460 {
 461         struct rk_i2s_dev *i2s = to_info(cpu_dai);
 462         int ret;
 463
 464         if (freq == 0)
 465                 return 0;
 466
 467         ret = clk_set_rate(i2s->mclk, freq);
 468         if (ret)
 469                 dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
 470
 471         return ret;
 472 }
 473
 474 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
 475 {
 476         struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
 477
 478         snd_soc_dai_init_dma_data(dai,
 479                 i2s->has_playback ? &i2s->playback_dma_data : NULL,
 480                 i2s->has_capture  ? &i2s->capture_dma_data  : NULL);
 481
 482         return 0;
 483 }
 484
 485 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
 486         .hw_params = rockchip_i2s_hw_params,
 487         .set_bclk_ratio = rockchip_i2s_set_bclk_ratio,
 488         .set_sysclk = rockchip_i2s_set_sysclk,
 489         .set_fmt = rockchip_i2s_set_fmt,
 490         .trigger = rockchip_i2s_trigger,
 491 };
 492
 493 static struct snd_soc_dai_driver rockchip_i2s_dai = {
 494         .probe = rockchip_i2s_dai_probe,
 495         .ops = &rockchip_i2s_dai_ops,
 496         .symmetric_rate = 1,
 497 };
 498
 499 static const struct snd_soc_component_driver rockchip_i2s_component = {
 500         .name = DRV_NAME,
 501 };
 502
 503 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
 504 {
 505         switch (reg) {
 506         case I2S_TXCR:
 507         case I2S_RXCR:
 508         case I2S_CKR:
 509         case I2S_DMACR:
 510         case I2S_INTCR:
 511         case I2S_XFER:
 512         case I2S_CLR:
 513         case I2S_TXDR:
 514                 return true;
 515         default:
 516                 return false;
 517         }
 518 }
 519
 520 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
 521 {
 522         switch (reg) {
 523         case I2S_TXCR:
 524         case I2S_RXCR:
 525         case I2S_CKR:
 526         case I2S_DMACR:
 527         case I2S_INTCR:
 528         case I2S_XFER:
 529         case I2S_CLR:
 530         case I2S_TXDR:
 531         case I2S_RXDR:
 532         case I2S_FIFOLR:
 533         case I2S_INTSR:
 534                 return true;
 535         default:
 536                 return false;
 537         }
 538 }
 539
 540 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
 541 {
 542         switch (reg) {
 543         case I2S_INTSR:
 544         case I2S_CLR:
 545         case I2S_FIFOLR:
 546         case I2S_TXDR:
 547         case I2S_RXDR:
 548                 return true;
 549         default:
 550                 return false;
 551         }
 552 }
 553
 554 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
 555 {
 556         switch (reg) {
 557         case I2S_RXDR:
 558                 return true;
 559         default:
 560                 return false;
 561         }
 562 }
 563
 564 static const struct reg_default rockchip_i2s_reg_defaults[] = {
 565         {0x00, 0x0000000f},
 566         {0x04, 0x0000000f},
 567         {0x08, 0x00071f1f},
 568         {0x10, 0x001f0000},
 569         {0x14, 0x01f00000},
 570 };
 571
 572 static const struct regmap_config rockchip_i2s_regmap_config = {
 573         .reg_bits = 32,
 574         .reg_stride = 4,
 575         .val_bits = 32,
 576         .max_register = I2S_RXDR,
 577         .reg_defaults = rockchip_i2s_reg_defaults,
 578         .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
 579         .writeable_reg = rockchip_i2s_wr_reg,
 580         .readable_reg = rockchip_i2s_rd_reg,
 581         .volatile_reg = rockchip_i2s_volatile_reg,
 582         .precious_reg = rockchip_i2s_precious_reg,
 583         .cache_type = REGCACHE_FLAT,
 584 };
 585
 586 static const struct rk_i2s_pins rk3399_i2s_pins = {
 587         .reg_offset = 0xe220,
 588         .shift = 11,
 589 };
 590
 591 static const struct of_device_id rockchip_i2s_match[] __maybe_unused = {
 592         { .compatible = "rockchip,px30-i2s", },
 593         { .compatible = "rockchip,rk1808-i2s", },
 594         { .compatible = "rockchip,rk3036-i2s", },
 595         { .compatible = "rockchip,rk3066-i2s", },
 596         { .compatible = "rockchip,rk3128-i2s", },
 597         { .compatible = "rockchip,rk3188-i2s", },
 598         { .compatible = "rockchip,rk3228-i2s", },
 599         { .compatible = "rockchip,rk3288-i2s", },
 600         { .compatible = "rockchip,rk3308-i2s", },
 601         { .compatible = "rockchip,rk3328-i2s", },
 602         { .compatible = "rockchip,rk3366-i2s", },
 603         { .compatible = "rockchip,rk3368-i2s", },
 604         { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
 605         { .compatible = "rockchip,rv1126-i2s", },
 606         {},
 607 };
 608
 609 static int rockchip_i2s_init_dai(struct rk_i2s_dev *i2s, struct resource *res,
 610                                  struct snd_soc_dai_driver **dp)
 611 {
 612         struct device_node *node = i2s->dev->of_node;
 613         struct snd_soc_dai_driver *dai;
 614         struct property *dma_names;
 615         const char *dma_name;
 616         unsigned int val;
 617
 618         of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
 619                 if (!strcmp(dma_name, "tx"))
 620                         i2s->has_playback = true;
 621                 if (!strcmp(dma_name, "rx"))
 622                         i2s->has_capture = true;
 623         }
 624
 625         dai = devm_kmemdup(i2s->dev, &rockchip_i2s_dai,
 626                            sizeof(*dai), GFP_KERNEL);
 627         if (!dai)
 628                 return -ENOMEM;
 629
 630         if (i2s->has_playback) {
 631                 dai->playback.stream_name = "Playback";
 632                 dai->playback.channels_min = 2;
 633                 dai->playback.channels_max = 8;
 634                 dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
 635                 dai->playback.formats = SNDRV_PCM_FMTBIT_S8 |
 636                                         SNDRV_PCM_FMTBIT_S16_LE |
 637                                         SNDRV_PCM_FMTBIT_S20_3LE |
 638                                         SNDRV_PCM_FMTBIT_S24_LE |
 639                                         SNDRV_PCM_FMTBIT_S32_LE;
 640
 641                 i2s->playback_dma_data.addr = res->start + I2S_TXDR;
 642                 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 643                 i2s->playback_dma_data.maxburst = 8;
 644
 645                 if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
 646                         if (val >= 2 && val <= 8)
 647                                 dai->playback.channels_max = val;
 648                 }
 649         }
 650
 651         if (i2s->has_capture) {
 652                 dai->capture.stream_name = "Capture";
 653                 dai->capture.channels_min = 2;
 654                 dai->capture.channels_max = 8;
 655                 dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
 656                 dai->capture.formats = SNDRV_PCM_FMTBIT_S8 |
 657                                        SNDRV_PCM_FMTBIT_S16_LE |
 658                                        SNDRV_PCM_FMTBIT_S20_3LE |
 659                                        SNDRV_PCM_FMTBIT_S24_LE |
 660                                        SNDRV_PCM_FMTBIT_S32_LE;
 661
 662                 i2s->capture_dma_data.addr = res->start + I2S_RXDR;
 663                 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 664                 i2s->capture_dma_data.maxburst = 8;
 665
 666                 if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
 667                         if (val >= 2 && val <= 8)
 668                                 dai->capture.channels_max = val;
 669                 }
 670         }
 671
 672         if (dp)
 673                 *dp = dai;
 674
 675         return 0;
 676 }
 677
 678 static int rockchip_i2s_probe(struct platform_device *pdev)
 679 {
 680         struct device_node *node = pdev->dev.of_node;
 681         const struct of_device_id *of_id;
 682         struct rk_i2s_dev *i2s;
 683         struct snd_soc_dai_driver *dai;
 684         struct resource *res;
 685         void __iomem *regs;
 686         int ret;
 687
 688         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
 689         if (!i2s)
 690                 return -ENOMEM;
 691
 692         spin_lock_init(&i2s->lock);
 693         i2s->dev = &pdev->dev;
 694
 695         i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
 696         if (!IS_ERR(i2s->grf)) {
 697                 of_id = of_match_device(rockchip_i2s_match, &pdev->dev);
 698                 if (!of_id || !of_id->data)
 699                         return -EINVAL;
 700
 701                 i2s->pins = of_id->data;
 702         }
 703
 704         /* try to prepare related clocks */
 705         i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
 706         if (IS_ERR(i2s->hclk)) {
 707                 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
 708                 return PTR_ERR(i2s->hclk);
 709         }
 710         ret = clk_prepare_enable(i2s->hclk);
 711         if (ret) {
 712                 dev_err(i2s->dev, "hclock enable failed %d\n", ret);
 713                 return ret;
 714         }
 715
 716         i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
 717         if (IS_ERR(i2s->mclk)) {
 718                 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
 719                 ret = PTR_ERR(i2s->mclk);
 720                 goto err_clk;
 721         }
 722
 723         regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
 724         if (IS_ERR(regs)) {
 725                 ret = PTR_ERR(regs);
 726                 goto err_clk;
 727         }
 728
 729         i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
 730                                             &rockchip_i2s_regmap_config);
 731         if (IS_ERR(i2s->regmap)) {
 732                 dev_err(&pdev->dev,
 733                         "Failed to initialise managed register map\n");
 734                 ret = PTR_ERR(i2s->regmap);
 735                 goto err_clk;
 736         }
 737
 738         i2s->bclk_ratio = 64;
 739
 740         dev_set_drvdata(&pdev->dev, i2s);
 741
 742         pm_runtime_enable(&pdev->dev);
 743         if (!pm_runtime_enabled(&pdev->dev)) {
 744                 ret = i2s_runtime_resume(&pdev->dev);
 745                 if (ret)
 746                         goto err_pm_disable;
 747         }
 748
 749         ret = rockchip_i2s_init_dai(i2s, res, &dai);
 750         if (ret)
 751                 goto err_pm_disable;
 752
 753         ret = devm_snd_soc_register_component(&pdev->dev,
 754                                               &rockchip_i2s_component,
 755                                               dai, 1);
 756
 757         if (ret) {
 758                 dev_err(&pdev->dev, "Could not register DAI\n");
 759                 goto err_suspend;
 760         }
 761
 762         ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
 763         if (ret) {
 764                 dev_err(&pdev->dev, "Could not register PCM\n");
 765                 goto err_suspend;
 766         }
 767
 768         return 0;
 769
 770 err_suspend:
 771         if (!pm_runtime_status_suspended(&pdev->dev))
 772                 i2s_runtime_suspend(&pdev->dev);
 773 err_pm_disable:
 774         pm_runtime_disable(&pdev->dev);
 775 err_clk:
 776         clk_disable_unprepare(i2s->hclk);
 777         return ret;
 778 }
 779
 780 static int rockchip_i2s_remove(struct platform_device *pdev)
 781 {
 782         struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
 783
 784         pm_runtime_disable(&pdev->dev);
 785         if (!pm_runtime_status_suspended(&pdev->dev))
 786                 i2s_runtime_suspend(&pdev->dev);
 787
 788         clk_disable_unprepare(i2s->hclk);
 789
 790         return 0;
 791 }
 792
 793 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
 794         SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
 795                            NULL)
 796 };
 797
 798 static struct platform_driver rockchip_i2s_driver = {
 799         .probe = rockchip_i2s_probe,
 800         .remove = rockchip_i2s_remove,
 801         .driver = {
 802                 .name = DRV_NAME,
 803                 .of_match_table = of_match_ptr(rockchip_i2s_match),
 804                 .pm = &rockchip_i2s_pm_ops,
 805         },
 806 };
 807 module_platform_driver(rockchip_i2s_driver);
 808
 809 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
 810 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
 811 MODULE_LICENSE("GPL v2");
 812 MODULE_ALIAS("platform:" DRV_NAME);
 813 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);