1 // SPDX-License-Identifier: GPL-2.0-only
2 /* sound/soc/rockchip/rockchip_i2s.c
4 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
6 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
7 * Author: Jianqun <jay.xu@rock-chips.com>
10 #include <linux/module.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/delay.h>
13 #include <linux/of_gpio.h>
14 #include <linux/of_device.h>
15 #include <linux/clk.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <sound/pcm_params.h>
19 #include <sound/dmaengine_pcm.h>
21 #include "rockchip_i2s.h"
22 #include "rockchip_pcm.h"
24 #define DRV_NAME "rockchip-i2s"
37 struct snd_dmaengine_dai_dma_data capture_dma_data;
38 struct snd_dmaengine_dai_dma_data playback_dma_data;
40 struct regmap *regmap;
44 * Used to indicate the tx/rx status.
45 * I2S controller hopes to start the tx and rx together,
46 * also to stop them when they are both try to stop.
51 const struct rk_i2s_pins *pins;
54 static int i2s_runtime_suspend(struct device *dev)
56 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
58 regcache_cache_only(i2s->regmap, true);
59 clk_disable_unprepare(i2s->mclk);
64 static int i2s_runtime_resume(struct device *dev)
66 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
69 ret = clk_prepare_enable(i2s->mclk);
71 dev_err(i2s->dev, "clock enable failed %d\n", ret);
75 regcache_cache_only(i2s->regmap, false);
76 regcache_mark_dirty(i2s->regmap);
78 ret = regcache_sync(i2s->regmap);
80 clk_disable_unprepare(i2s->mclk);
85 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
87 return snd_soc_dai_get_drvdata(dai);
90 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
96 regmap_update_bits(i2s->regmap, I2S_DMACR,
97 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
99 regmap_update_bits(i2s->regmap, I2S_XFER,
100 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
101 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
103 i2s->tx_start = true;
105 i2s->tx_start = false;
107 regmap_update_bits(i2s->regmap, I2S_DMACR,
108 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
110 if (!i2s->rx_start) {
111 regmap_update_bits(i2s->regmap, I2S_XFER,
118 regmap_update_bits(i2s->regmap, I2S_CLR,
119 I2S_CLR_TXC | I2S_CLR_RXC,
120 I2S_CLR_TXC | I2S_CLR_RXC);
122 regmap_read(i2s->regmap, I2S_CLR, &val);
124 /* Should wait for clear operation to finish */
126 regmap_read(i2s->regmap, I2S_CLR, &val);
129 dev_warn(i2s->dev, "fail to clear\n");
137 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
139 unsigned int val = 0;
143 regmap_update_bits(i2s->regmap, I2S_DMACR,
144 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
146 regmap_update_bits(i2s->regmap, I2S_XFER,
147 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
148 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
150 i2s->rx_start = true;
152 i2s->rx_start = false;
154 regmap_update_bits(i2s->regmap, I2S_DMACR,
155 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
157 if (!i2s->tx_start) {
158 regmap_update_bits(i2s->regmap, I2S_XFER,
165 regmap_update_bits(i2s->regmap, I2S_CLR,
166 I2S_CLR_TXC | I2S_CLR_RXC,
167 I2S_CLR_TXC | I2S_CLR_RXC);
169 regmap_read(i2s->regmap, I2S_CLR, &val);
171 /* Should wait for clear operation to finish */
173 regmap_read(i2s->regmap, I2S_CLR, &val);
176 dev_warn(i2s->dev, "fail to clear\n");
184 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
187 struct rk_i2s_dev *i2s = to_info(cpu_dai);
188 unsigned int mask = 0, val = 0;
190 mask = I2S_CKR_MSS_MASK;
191 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
192 case SND_SOC_DAIFMT_CBS_CFS:
193 /* Set source clock in Master mode */
194 val = I2S_CKR_MSS_MASTER;
195 i2s->is_master_mode = true;
197 case SND_SOC_DAIFMT_CBM_CFM:
198 val = I2S_CKR_MSS_SLAVE;
199 i2s->is_master_mode = false;
205 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
207 mask = I2S_CKR_CKP_MASK;
208 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
209 case SND_SOC_DAIFMT_NB_NF:
210 val = I2S_CKR_CKP_NEG;
212 case SND_SOC_DAIFMT_IB_NF:
213 val = I2S_CKR_CKP_POS;
219 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
221 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
222 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
223 case SND_SOC_DAIFMT_RIGHT_J:
224 val = I2S_TXCR_IBM_RSJM;
226 case SND_SOC_DAIFMT_LEFT_J:
227 val = I2S_TXCR_IBM_LSJM;
229 case SND_SOC_DAIFMT_I2S:
230 val = I2S_TXCR_IBM_NORMAL;
232 case SND_SOC_DAIFMT_DSP_A: /* PCM no delay mode */
233 val = I2S_TXCR_TFS_PCM;
235 case SND_SOC_DAIFMT_DSP_B: /* PCM delay 1 mode */
236 val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
242 regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
244 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
245 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
246 case SND_SOC_DAIFMT_RIGHT_J:
247 val = I2S_RXCR_IBM_RSJM;
249 case SND_SOC_DAIFMT_LEFT_J:
250 val = I2S_RXCR_IBM_LSJM;
252 case SND_SOC_DAIFMT_I2S:
253 val = I2S_RXCR_IBM_NORMAL;
255 case SND_SOC_DAIFMT_DSP_A: /* PCM no delay mode */
256 val = I2S_RXCR_TFS_PCM;
258 case SND_SOC_DAIFMT_DSP_B: /* PCM delay 1 mode */
259 val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
265 regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
270 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
271 struct snd_pcm_hw_params *params,
272 struct snd_soc_dai *dai)
274 struct rk_i2s_dev *i2s = to_info(dai);
275 struct snd_soc_pcm_runtime *rtd = substream->private_data;
276 unsigned int val = 0;
277 unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
279 if (i2s->is_master_mode) {
280 mclk_rate = clk_get_rate(i2s->mclk);
281 bclk_rate = 2 * 32 * params_rate(params);
282 if (bclk_rate && mclk_rate % bclk_rate)
285 div_bclk = mclk_rate / bclk_rate;
286 div_lrck = bclk_rate / params_rate(params);
287 regmap_update_bits(i2s->regmap, I2S_CKR,
289 I2S_CKR_MDIV(div_bclk));
291 regmap_update_bits(i2s->regmap, I2S_CKR,
294 I2S_CKR_TSD(div_lrck) |
295 I2S_CKR_RSD(div_lrck));
298 switch (params_format(params)) {
299 case SNDRV_PCM_FORMAT_S8:
300 val |= I2S_TXCR_VDW(8);
302 case SNDRV_PCM_FORMAT_S16_LE:
303 val |= I2S_TXCR_VDW(16);
305 case SNDRV_PCM_FORMAT_S20_3LE:
306 val |= I2S_TXCR_VDW(20);
308 case SNDRV_PCM_FORMAT_S24_LE:
309 val |= I2S_TXCR_VDW(24);
311 case SNDRV_PCM_FORMAT_S32_LE:
312 val |= I2S_TXCR_VDW(32);
318 switch (params_channels(params)) {
332 dev_err(i2s->dev, "invalid channel: %d\n",
333 params_channels(params));
337 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
338 regmap_update_bits(i2s->regmap, I2S_RXCR,
339 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
342 regmap_update_bits(i2s->regmap, I2S_TXCR,
343 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
346 if (!IS_ERR(i2s->grf) && i2s->pins) {
347 regmap_read(i2s->regmap, I2S_TXCR, &val);
348 val &= I2S_TXCR_CSR_MASK;
352 val = I2S_IO_4CH_OUT_6CH_IN;
355 val = I2S_IO_6CH_OUT_4CH_IN;
358 val = I2S_IO_8CH_OUT_2CH_IN;
361 val = I2S_IO_2CH_OUT_8CH_IN;
365 val <<= i2s->pins->shift;
366 val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16;
367 regmap_write(i2s->grf, i2s->pins->reg_offset, val);
370 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
372 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
375 val = I2S_CKR_TRCM_TXRX;
376 if (dai->driver->symmetric_rates && rtd->dai_link->symmetric_rates)
377 val = I2S_CKR_TRCM_TXONLY;
379 regmap_update_bits(i2s->regmap, I2S_CKR,
385 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
386 int cmd, struct snd_soc_dai *dai)
388 struct rk_i2s_dev *i2s = to_info(dai);
392 case SNDRV_PCM_TRIGGER_START:
393 case SNDRV_PCM_TRIGGER_RESUME:
394 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
395 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
396 rockchip_snd_rxctrl(i2s, 1);
398 rockchip_snd_txctrl(i2s, 1);
400 case SNDRV_PCM_TRIGGER_SUSPEND:
401 case SNDRV_PCM_TRIGGER_STOP:
402 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
403 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
404 rockchip_snd_rxctrl(i2s, 0);
406 rockchip_snd_txctrl(i2s, 0);
416 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
417 unsigned int freq, int dir)
419 struct rk_i2s_dev *i2s = to_info(cpu_dai);
425 ret = clk_set_rate(i2s->mclk, freq);
427 dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
432 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
434 struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
436 dai->capture_dma_data = &i2s->capture_dma_data;
437 dai->playback_dma_data = &i2s->playback_dma_data;
442 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
443 .hw_params = rockchip_i2s_hw_params,
444 .set_sysclk = rockchip_i2s_set_sysclk,
445 .set_fmt = rockchip_i2s_set_fmt,
446 .trigger = rockchip_i2s_trigger,
449 static struct snd_soc_dai_driver rockchip_i2s_dai = {
450 .probe = rockchip_i2s_dai_probe,
452 .stream_name = "Playback",
455 .rates = SNDRV_PCM_RATE_8000_192000,
456 .formats = (SNDRV_PCM_FMTBIT_S8 |
457 SNDRV_PCM_FMTBIT_S16_LE |
458 SNDRV_PCM_FMTBIT_S20_3LE |
459 SNDRV_PCM_FMTBIT_S24_LE |
460 SNDRV_PCM_FMTBIT_S32_LE),
463 .stream_name = "Capture",
466 .rates = SNDRV_PCM_RATE_8000_192000,
467 .formats = (SNDRV_PCM_FMTBIT_S8 |
468 SNDRV_PCM_FMTBIT_S16_LE |
469 SNDRV_PCM_FMTBIT_S20_3LE |
470 SNDRV_PCM_FMTBIT_S24_LE |
471 SNDRV_PCM_FMTBIT_S32_LE),
473 .ops = &rockchip_i2s_dai_ops,
474 .symmetric_rates = 1,
477 static const struct snd_soc_component_driver rockchip_i2s_component = {
481 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
498 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
518 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
532 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
542 static const struct reg_default rockchip_i2s_reg_defaults[] = {
550 static const struct regmap_config rockchip_i2s_regmap_config = {
554 .max_register = I2S_RXDR,
555 .reg_defaults = rockchip_i2s_reg_defaults,
556 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
557 .writeable_reg = rockchip_i2s_wr_reg,
558 .readable_reg = rockchip_i2s_rd_reg,
559 .volatile_reg = rockchip_i2s_volatile_reg,
560 .precious_reg = rockchip_i2s_precious_reg,
561 .cache_type = REGCACHE_FLAT,
564 static const struct rk_i2s_pins rk3399_i2s_pins = {
565 .reg_offset = 0xe220,
569 static const struct of_device_id rockchip_i2s_match[] = {
570 { .compatible = "rockchip,rk3066-i2s", },
571 { .compatible = "rockchip,rk3188-i2s", },
572 { .compatible = "rockchip,rk3288-i2s", },
573 { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
577 static int rockchip_i2s_probe(struct platform_device *pdev)
579 struct device_node *node = pdev->dev.of_node;
580 const struct of_device_id *of_id;
581 struct rk_i2s_dev *i2s;
582 struct snd_soc_dai_driver *soc_dai;
583 struct resource *res;
588 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
592 i2s->dev = &pdev->dev;
594 i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
595 if (!IS_ERR(i2s->grf)) {
596 of_id = of_match_device(rockchip_i2s_match, &pdev->dev);
597 if (!of_id || !of_id->data)
600 i2s->pins = of_id->data;
603 /* try to prepare related clocks */
604 i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
605 if (IS_ERR(i2s->hclk)) {
606 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
607 return PTR_ERR(i2s->hclk);
609 ret = clk_prepare_enable(i2s->hclk);
611 dev_err(i2s->dev, "hclock enable failed %d\n", ret);
615 i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
616 if (IS_ERR(i2s->mclk)) {
617 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
618 return PTR_ERR(i2s->mclk);
621 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
622 regs = devm_ioremap_resource(&pdev->dev, res);
624 return PTR_ERR(regs);
626 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
627 &rockchip_i2s_regmap_config);
628 if (IS_ERR(i2s->regmap)) {
630 "Failed to initialise managed register map\n");
631 return PTR_ERR(i2s->regmap);
634 i2s->playback_dma_data.addr = res->start + I2S_TXDR;
635 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
636 i2s->playback_dma_data.maxburst = 4;
638 i2s->capture_dma_data.addr = res->start + I2S_RXDR;
639 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
640 i2s->capture_dma_data.maxburst = 4;
642 dev_set_drvdata(&pdev->dev, i2s);
644 pm_runtime_enable(&pdev->dev);
645 if (!pm_runtime_enabled(&pdev->dev)) {
646 ret = i2s_runtime_resume(&pdev->dev);
651 soc_dai = devm_kmemdup(&pdev->dev, &rockchip_i2s_dai,
652 sizeof(*soc_dai), GFP_KERNEL);
658 if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
659 if (val >= 2 && val <= 8)
660 soc_dai->playback.channels_max = val;
663 if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
664 if (val >= 2 && val <= 8)
665 soc_dai->capture.channels_max = val;
668 ret = devm_snd_soc_register_component(&pdev->dev,
669 &rockchip_i2s_component,
673 dev_err(&pdev->dev, "Could not register DAI\n");
677 ret = rockchip_pcm_platform_register(&pdev->dev);
679 dev_err(&pdev->dev, "Could not register PCM\n");
686 if (!pm_runtime_status_suspended(&pdev->dev))
687 i2s_runtime_suspend(&pdev->dev);
689 pm_runtime_disable(&pdev->dev);
694 static int rockchip_i2s_remove(struct platform_device *pdev)
696 struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
698 pm_runtime_disable(&pdev->dev);
699 if (!pm_runtime_status_suspended(&pdev->dev))
700 i2s_runtime_suspend(&pdev->dev);
702 clk_disable_unprepare(i2s->hclk);
707 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
708 SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
712 static struct platform_driver rockchip_i2s_driver = {
713 .probe = rockchip_i2s_probe,
714 .remove = rockchip_i2s_remove,
717 .of_match_table = of_match_ptr(rockchip_i2s_match),
718 .pm = &rockchip_i2s_pm_ops,
721 module_platform_driver(rockchip_i2s_driver);
723 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
724 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
725 MODULE_LICENSE("GPL v2");
726 MODULE_ALIAS("platform:" DRV_NAME);
727 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);