1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2010-2011,2013-2015,2020 The Linux Foundation. All rights reserved.
5 * lpass.h - Definitions for the QTi LPASS
11 #include <linux/clk.h>
12 #include <linux/compiler.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15 #include <dt-bindings/sound/sc7180-lpass.h>
16 #include "lpass-hdmi.h"
18 #define LPASS_AHBIX_CLOCK_FREQUENCY 131072000
19 #define LPASS_MAX_MI2S_PORTS (8)
20 #define LPASS_MAX_DMA_CHANNELS (8)
21 #define LPASS_MAX_HDMI_DMA_CHANNELS (4)
23 #define QCOM_REGMAP_FIELD_ALLOC(d, m, f, mf) \
25 mf = devm_regmap_field_alloc(d, m, f); \
31 struct regmap_field *loopback;
32 struct regmap_field *spken;
33 struct regmap_field *spkmode;
34 struct regmap_field *spkmono;
35 struct regmap_field *micen;
36 struct regmap_field *micmode;
37 struct regmap_field *micmono;
38 struct regmap_field *wssrc;
39 struct regmap_field *bitwidth;
44 struct regmap_field *intf;
45 struct regmap_field *bursten;
46 struct regmap_field *wpscnt;
47 struct regmap_field *fifowm;
48 struct regmap_field *enable;
49 struct regmap_field *dyncclk;
50 struct regmap_field *burst8;
51 struct regmap_field *burst16;
52 struct regmap_field *dynburst;
55 /* Both the CPU DAI and platform drivers will access this data */
58 /* AHB-I/X bus clocks inside the low-power audio subsystem (LPASS) */
59 struct clk *ahbix_clk;
61 /* MI2S system clock */
62 struct clk *mi2s_osr_clk[LPASS_MAX_MI2S_PORTS];
64 /* MI2S bit clock (derived from system clock by a divider */
65 struct clk *mi2s_bit_clk[LPASS_MAX_MI2S_PORTS];
67 /* MI2S SD lines to use for playback/capture */
68 unsigned int mi2s_playback_sd_mode[LPASS_MAX_MI2S_PORTS];
69 unsigned int mi2s_capture_sd_mode[LPASS_MAX_MI2S_PORTS];
72 /* low-power audio interface (LPAIF) registers */
76 /* regmap backed by the low-power audio interface (LPAIF) registers */
77 struct regmap *lpaif_map;
78 struct regmap *hdmiif_map;
80 /* interrupts from the low-power audio interface (LPAIF) */
83 /* SOC specific variations in the LPASS IP integration */
84 struct lpass_variant *variant;
86 /* bit map to keep track of static channel allocations */
87 unsigned long dma_ch_bit_map;
88 unsigned long hdmi_dma_ch_bit_map;
90 /* used it for handling interrupt per dma channel */
91 struct snd_pcm_substream *substream[LPASS_MAX_DMA_CHANNELS];
92 struct snd_pcm_substream *hdmi_substream[LPASS_MAX_HDMI_DMA_CHANNELS];
94 /* SOC specific clock list */
95 struct clk_bulk_data *clks;
98 /* Regmap fields of I2SCTL & DMACTL registers bitfields */
99 struct lpaif_i2sctl *i2sctl;
100 struct lpaif_dmactl *rd_dmactl;
101 struct lpaif_dmactl *wr_dmactl;
102 struct lpaif_dmactl *hdmi_rd_dmactl;
103 /* Regmap fields of HDMI_CTRL registers*/
104 struct regmap_field *hdmitx_legacy_en;
105 struct regmap_field *hdmitx_parity_calc_en;
106 struct regmap_field *hdmitx_ch_msb[LPASS_MAX_HDMI_DMA_CHANNELS];
107 struct regmap_field *hdmitx_ch_lsb[LPASS_MAX_HDMI_DMA_CHANNELS];
108 struct lpass_hdmi_tx_ctl *tx_ctl;
109 struct lpass_vbit_ctrl *vbit_ctl;
110 struct lpass_hdmitx_dmactl *hdmi_tx_dmactl[LPASS_MAX_HDMI_DMA_CHANNELS];
111 struct lpass_dp_metadata_ctl *meta_ctl;
112 struct lpass_sstream_ctl *sstream_ctl;
115 /* Vairant data per each SOC */
116 struct lpass_variant {
123 u32 hdmi_rdma_reg_base;
124 u32 hdmi_rdma_reg_stride;
125 u32 hdmi_rdma_channels;
127 u32 wrdma_reg_stride;
129 u32 i2sctrl_reg_base;
130 u32 i2sctrl_reg_stride;
133 /* I2SCTL Register fields */
134 struct reg_field loopback;
135 struct reg_field spken;
136 struct reg_field spkmode;
137 struct reg_field spkmono;
138 struct reg_field micen;
139 struct reg_field micmode;
140 struct reg_field micmono;
141 struct reg_field wssrc;
142 struct reg_field bitwidth;
144 u32 hdmi_irq_reg_base;
145 u32 hdmi_irq_reg_stride;
148 /* HDMI specific controls */
149 u32 hdmi_tx_ctl_addr;
150 u32 hdmi_legacy_addr;
152 u32 hdmi_ch_lsb_addr;
153 u32 hdmi_ch_msb_addr;
155 u32 hdmi_parity_addr;
156 u32 hdmi_dmactl_addr;
159 u32 hdmi_sstream_addr;
161 /* HDMI SSTREAM CTRL fields */
162 struct reg_field sstream_en;
163 struct reg_field dma_sel;
164 struct reg_field auto_bbit_en;
165 struct reg_field layout;
166 struct reg_field layout_sp;
167 struct reg_field set_sp_on_en;
168 struct reg_field dp_audio;
169 struct reg_field dp_staffing_en;
170 struct reg_field dp_sp_b_hw_en;
172 /* HDMI DP METADATA CTL fields */
173 struct reg_field mute;
174 struct reg_field as_sdp_cc;
175 struct reg_field as_sdp_ct;
176 struct reg_field aif_db4;
177 struct reg_field frequency;
178 struct reg_field mst_index;
179 struct reg_field dptx_index;
181 /* HDMI TX CTRL fields */
182 struct reg_field soft_reset;
183 struct reg_field force_reset;
185 /* HDMI TX DMA CTRL */
186 struct reg_field use_hw_chs;
187 struct reg_field use_hw_usr;
188 struct reg_field hw_chs_sel;
189 struct reg_field hw_usr_sel;
192 struct reg_field replace_vbit;
193 struct reg_field vbit_stream;
196 struct reg_field legacy_en;
199 struct reg_field calc_en;
202 struct reg_field lsb_bits;
205 struct reg_field msb_bits;
207 struct reg_field hdmi_rdma_bursten;
208 struct reg_field hdmi_rdma_wpscnt;
209 struct reg_field hdmi_rdma_fifowm;
210 struct reg_field hdmi_rdma_enable;
211 struct reg_field hdmi_rdma_dyncclk;
212 struct reg_field hdmi_rdma_burst8;
213 struct reg_field hdmi_rdma_burst16;
214 struct reg_field hdmi_rdma_dynburst;
216 /* RD_DMA Register fields */
217 struct reg_field rdma_intf;
218 struct reg_field rdma_bursten;
219 struct reg_field rdma_wpscnt;
220 struct reg_field rdma_fifowm;
221 struct reg_field rdma_enable;
222 struct reg_field rdma_dyncclk;
224 /* WR_DMA Register fields */
225 struct reg_field wrdma_intf;
226 struct reg_field wrdma_bursten;
227 struct reg_field wrdma_wpscnt;
228 struct reg_field wrdma_fifowm;
229 struct reg_field wrdma_enable;
230 struct reg_field wrdma_dyncclk;
233 * on SOCs like APQ8016 the channel control bits start
234 * at different offset to ipq806x
236 u32 dmactl_audif_start;
237 u32 wrdma_channel_start;
238 /* SOC specific initialization like clocks */
239 int (*init)(struct platform_device *pdev);
240 int (*exit)(struct platform_device *pdev);
241 int (*alloc_dma_channel)(struct lpass_data *data, int direction, unsigned int dai_id);
242 int (*free_dma_channel)(struct lpass_data *data, int ch, unsigned int dai_id);
244 /* SOC specific dais */
245 struct snd_soc_dai_driver *dai_driver;
247 const char * const *dai_osr_clk_names;
248 const char * const *dai_bit_clk_names;
250 /* SOC specific clocks configuration */
251 const char **clk_name;
255 /* register the platform driver from the CPU DAI driver */
256 int asoc_qcom_lpass_platform_register(struct platform_device *);
257 int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev);
258 int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev);
259 int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai);
260 extern const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops;
262 #endif /* __LPASS_H__ */