sound/soc/qcom/lpass-sc7180.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4  *
   5  * lpass-sc7180.c -- ALSA SoC platform-machine driver for QTi LPASS
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/device.h>
  10 #include <linux/err.h>
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/of.h>
  14 #include <linux/platform_device.h>
  15 #include <dt-bindings/sound/sc7180-lpass.h>
  16 #include <sound/pcm.h>
  17 #include <sound/soc.h>
  18
  19 #include "lpass-lpaif-reg.h"
  20 #include "lpass.h"
  21
  22 static struct snd_soc_dai_driver sc7180_lpass_cpu_dai_driver[] = {
  23         {
  24                 .id = MI2S_PRIMARY,
  25                 .name = "Primary MI2S",
  26                 .playback = {
  27                         .stream_name = "Primary Playback",
  28                         .formats        = SNDRV_PCM_FMTBIT_S16,
  29                         .rates = SNDRV_PCM_RATE_48000,
  30                         .rate_min       = 48000,
  31                         .rate_max       = 48000,
  32                         .channels_min   = 2,
  33                         .channels_max   = 2,
  34                 },
  35                 .capture = {
  36                         .stream_name = "Primary Capture",
  37                         .formats = SNDRV_PCM_FMTBIT_S16 |
  38                                 SNDRV_PCM_FMTBIT_S32,
  39                         .rates = SNDRV_PCM_RATE_48000,
  40                         .rate_min       = 48000,
  41                         .rate_max       = 48000,
  42                         .channels_min   = 2,
  43                         .channels_max   = 2,
  44                 },
  45                 .probe  = &asoc_qcom_lpass_cpu_dai_probe,
  46                 .ops    = &asoc_qcom_lpass_cpu_dai_ops,
  47         }, {
  48                 .id = MI2S_SECONDARY,
  49                 .name = "Secondary MI2S",
  50                 .playback = {
  51                         .stream_name = "Secondary Playback",
  52                         .formats        = SNDRV_PCM_FMTBIT_S16,
  53                         .rates = SNDRV_PCM_RATE_48000,
  54                         .rate_min       = 48000,
  55                         .rate_max       = 48000,
  56                         .channels_min   = 2,
  57                         .channels_max   = 2,
  58                 },
  59                 .probe  = &asoc_qcom_lpass_cpu_dai_probe,
  60                 .ops    = &asoc_qcom_lpass_cpu_dai_ops,
  61         }, {
  62                 .id = LPASS_DP_RX,
  63                 .name = "Hdmi",
  64                 .playback = {
  65                         .stream_name = "Hdmi Playback",
  66                         .formats        = SNDRV_PCM_FMTBIT_S24,
  67                         .rates = SNDRV_PCM_RATE_48000,
  68                         .rate_min       = 48000,
  69                         .rate_max       = 48000,
  70                         .channels_min   = 2,
  71                         .channels_max   = 2,
  72                 },
  73                 .ops    = &asoc_qcom_lpass_hdmi_dai_ops,
  74         },
  75 };
  76
  77 static int sc7180_lpass_alloc_dma_channel(struct lpass_data *drvdata,
  78                                            int direction, unsigned int dai_id)
  79 {
  80         struct lpass_variant *v = drvdata->variant;
  81         int chan = 0;
  82
  83         if (dai_id == LPASS_DP_RX) {
  84                 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
  85                         chan = find_first_zero_bit(&drvdata->hdmi_dma_ch_bit_map,
  86                                                 v->hdmi_rdma_channels);
  87
  88                         if (chan >= v->hdmi_rdma_channels)
  89                                 return -EBUSY;
  90                 }
  91                 set_bit(chan, &drvdata->hdmi_dma_ch_bit_map);
  92         } else {
  93                 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
  94                         chan = find_first_zero_bit(&drvdata->dma_ch_bit_map,
  95                                                 v->rdma_channels);
  96
  97                         if (chan >= v->rdma_channels)
  98                                 return -EBUSY;
  99                 } else {
 100                         chan = find_next_zero_bit(&drvdata->dma_ch_bit_map,
 101                                         v->wrdma_channel_start +
 102                                         v->wrdma_channels,
 103                                         v->wrdma_channel_start);
 104
 105                         if (chan >=  v->wrdma_channel_start + v->wrdma_channels)
 106                                 return -EBUSY;
 107                 }
 108
 109                 set_bit(chan, &drvdata->dma_ch_bit_map);
 110         }
 111         return chan;
 112 }
 113
 114 static int sc7180_lpass_free_dma_channel(struct lpass_data *drvdata, int chan, unsigned int dai_id)
 115 {
 116         if (dai_id == LPASS_DP_RX)
 117                 clear_bit(chan, &drvdata->hdmi_dma_ch_bit_map);
 118         else
 119                 clear_bit(chan, &drvdata->dma_ch_bit_map);
 120
 121         return 0;
 122 }
 123
 124 static int sc7180_lpass_init(struct platform_device *pdev)
 125 {
 126         struct lpass_data *drvdata = platform_get_drvdata(pdev);
 127         struct lpass_variant *variant = drvdata->variant;
 128         struct device *dev = &pdev->dev;
 129         int ret, i;
 130
 131         drvdata->clks = devm_kcalloc(dev, variant->num_clks,
 132                                      sizeof(*drvdata->clks), GFP_KERNEL);
 133         drvdata->num_clks = variant->num_clks;
 134
 135         for (i = 0; i < drvdata->num_clks; i++)
 136                 drvdata->clks[i].id = variant->clk_name[i];
 137
 138         ret = devm_clk_bulk_get(dev, drvdata->num_clks, drvdata->clks);
 139         if (ret) {
 140                 dev_err(dev, "Failed to get clocks %d\n", ret);
 141                 return ret;
 142         }
 143
 144         ret = clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks);
 145         if (ret) {
 146                 dev_err(dev, "sc7180 clk_enable failed\n");
 147                 return ret;
 148         }
 149
 150         return 0;
 151 }
 152
 153 static int sc7180_lpass_exit(struct platform_device *pdev)
 154 {
 155         struct lpass_data *drvdata = platform_get_drvdata(pdev);
 156
 157         clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks);
 158
 159         return 0;
 160 }
 161
 162 static struct lpass_variant sc7180_data = {
 163         .i2sctrl_reg_base       = 0x1000,
 164         .i2sctrl_reg_stride     = 0x1000,
 165         .i2s_ports              = 3,
 166         .irq_reg_base           = 0x9000,
 167         .irq_reg_stride         = 0x1000,
 168         .irq_ports              = 3,
 169         .rdma_reg_base          = 0xC000,
 170         .rdma_reg_stride        = 0x1000,
 171         .rdma_channels          = 5,
 172         .hdmi_rdma_reg_base             = 0x64000,
 173         .hdmi_rdma_reg_stride   = 0x1000,
 174         .hdmi_rdma_channels             = 4,
 175         .dmactl_audif_start     = 1,
 176         .wrdma_reg_base         = 0x18000,
 177         .wrdma_reg_stride       = 0x1000,
 178         .wrdma_channel_start    = 5,
 179         .wrdma_channels         = 4,
 180
 181         .loopback               = REG_FIELD_ID(0x1000, 17, 17, 3, 0x1000),
 182         .spken                  = REG_FIELD_ID(0x1000, 16, 16, 3, 0x1000),
 183         .spkmode                = REG_FIELD_ID(0x1000, 11, 15, 3, 0x1000),
 184         .spkmono                = REG_FIELD_ID(0x1000, 10, 10, 3, 0x1000),
 185         .micen                  = REG_FIELD_ID(0x1000, 9, 9, 3, 0x1000),
 186         .micmode                = REG_FIELD_ID(0x1000, 4, 8, 3, 0x1000),
 187         .micmono                = REG_FIELD_ID(0x1000, 3, 3, 3, 0x1000),
 188         .wssrc                  = REG_FIELD_ID(0x1000, 2, 2, 3, 0x1000),
 189         .bitwidth               = REG_FIELD_ID(0x1000, 0, 1, 3, 0x1000),
 190
 191         .rdma_dyncclk           = REG_FIELD_ID(0xC000, 21, 21, 5, 0x1000),
 192         .rdma_bursten           = REG_FIELD_ID(0xC000, 20, 20, 5, 0x1000),
 193         .rdma_wpscnt            = REG_FIELD_ID(0xC000, 16, 19, 5, 0x1000),
 194         .rdma_intf                      = REG_FIELD_ID(0xC000, 12, 15, 5, 0x1000),
 195         .rdma_fifowm            = REG_FIELD_ID(0xC000, 1, 5, 5, 0x1000),
 196         .rdma_enable            = REG_FIELD_ID(0xC000, 0, 0, 5, 0x1000),
 197
 198         .wrdma_dyncclk          = REG_FIELD_ID(0x18000, 22, 22, 4, 0x1000),
 199         .wrdma_bursten          = REG_FIELD_ID(0x18000, 21, 21, 4, 0x1000),
 200         .wrdma_wpscnt           = REG_FIELD_ID(0x18000, 17, 20, 4, 0x1000),
 201         .wrdma_intf             = REG_FIELD_ID(0x18000, 12, 16, 4, 0x1000),
 202         .wrdma_fifowm           = REG_FIELD_ID(0x18000, 1, 5, 4, 0x1000),
 203         .wrdma_enable           = REG_FIELD_ID(0x18000, 0, 0, 4, 0x1000),
 204
 205         .hdmi_tx_ctl_addr       = 0x1000,
 206         .hdmi_legacy_addr       = 0x1008,
 207         .hdmi_vbit_addr         = 0x610c0,
 208         .hdmi_ch_lsb_addr       = 0x61048,
 209         .hdmi_ch_msb_addr       = 0x6104c,
 210         .ch_stride              = 0x8,
 211         .hdmi_parity_addr       = 0x61034,
 212         .hdmi_dmactl_addr       = 0x61038,
 213         .hdmi_dma_stride        = 0x4,
 214         .hdmi_DP_addr           = 0x610c8,
 215         .hdmi_sstream_addr      = 0x6101c,
 216         .hdmi_irq_reg_base              = 0x63000,
 217         .hdmi_irq_ports         = 1,
 218
 219         .hdmi_rdma_dyncclk              = REG_FIELD_ID(0x64000, 14, 14, 4, 0x1000),
 220         .hdmi_rdma_bursten              = REG_FIELD_ID(0x64000, 13, 13, 4, 0x1000),
 221         .hdmi_rdma_burst8               = REG_FIELD_ID(0x64000, 15, 15, 4, 0x1000),
 222         .hdmi_rdma_burst16              = REG_FIELD_ID(0x64000, 16, 16, 4, 0x1000),
 223         .hdmi_rdma_dynburst             = REG_FIELD_ID(0x64000, 18, 18, 4, 0x1000),
 224         .hdmi_rdma_wpscnt               = REG_FIELD_ID(0x64000, 10, 12, 4, 0x1000),
 225         .hdmi_rdma_fifowm               = REG_FIELD_ID(0x64000, 1, 5, 4, 0x1000),
 226         .hdmi_rdma_enable               = REG_FIELD_ID(0x64000, 0, 0, 4, 0x1000),
 227
 228         .sstream_en             = REG_FIELD(0x6101c, 0, 0),
 229         .dma_sel                        = REG_FIELD(0x6101c, 1, 2),
 230         .auto_bbit_en   = REG_FIELD(0x6101c, 3, 3),
 231         .layout                 = REG_FIELD(0x6101c, 4, 4),
 232         .layout_sp              = REG_FIELD(0x6101c, 5, 8),
 233         .set_sp_on_en   = REG_FIELD(0x6101c, 10, 10),
 234         .dp_audio               = REG_FIELD(0x6101c, 11, 11),
 235         .dp_staffing_en = REG_FIELD(0x6101c, 12, 12),
 236         .dp_sp_b_hw_en  = REG_FIELD(0x6101c, 13, 13),
 237
 238         .mute                   = REG_FIELD(0x610c8, 0, 0),
 239         .as_sdp_cc              = REG_FIELD(0x610c8, 1, 3),
 240         .as_sdp_ct              = REG_FIELD(0x610c8, 4, 7),
 241         .aif_db4                        = REG_FIELD(0x610c8, 8, 15),
 242         .frequency              = REG_FIELD(0x610c8, 16, 21),
 243         .mst_index              = REG_FIELD(0x610c8, 28, 29),
 244         .dptx_index             = REG_FIELD(0x610c8, 30, 31),
 245
 246         .soft_reset             = REG_FIELD(0x1000, 31, 31),
 247         .force_reset    = REG_FIELD(0x1000, 30, 30),
 248
 249         .use_hw_chs             = REG_FIELD(0x61038, 0, 0),
 250         .use_hw_usr             = REG_FIELD(0x61038, 1, 1),
 251         .hw_chs_sel             = REG_FIELD(0x61038, 2, 4),
 252         .hw_usr_sel             = REG_FIELD(0x61038, 5, 6),
 253
 254         .replace_vbit   = REG_FIELD(0x610c0, 0, 0),
 255         .vbit_stream    = REG_FIELD(0x610c0, 1, 1),
 256
 257         .legacy_en              =  REG_FIELD(0x1008, 0, 0),
 258         .calc_en                =  REG_FIELD(0x61034, 0, 0),
 259         .lsb_bits               =  REG_FIELD(0x61048, 0, 31),
 260         .msb_bits               =  REG_FIELD(0x6104c, 0, 31),
 261
 262
 263         .clk_name               = (const char*[]) {
 264                                    "pcnoc-sway-clk",
 265                                    "audio-core",
 266                                    "pcnoc-mport-clk",
 267                                 },
 268         .num_clks               = 3,
 269         .dai_driver             = sc7180_lpass_cpu_dai_driver,
 270         .num_dai                = ARRAY_SIZE(sc7180_lpass_cpu_dai_driver),
 271         .dai_osr_clk_names      = (const char *[]) {
 272                                    "mclk0",
 273                                    "null",
 274                                 },
 275         .dai_bit_clk_names      = (const char *[]) {
 276                                    "mi2s-bit-clk0",
 277                                    "mi2s-bit-clk1",
 278                                 },
 279         .init                   = sc7180_lpass_init,
 280         .exit                   = sc7180_lpass_exit,
 281         .alloc_dma_channel      = sc7180_lpass_alloc_dma_channel,
 282         .free_dma_channel       = sc7180_lpass_free_dma_channel,
 283 };
 284
 285 static const struct of_device_id sc7180_lpass_cpu_device_id[] __maybe_unused = {
 286         {.compatible = "qcom,sc7180-lpass-cpu", .data = &sc7180_data},
 287         {}
 288 };
 289 MODULE_DEVICE_TABLE(of, sc7180_lpass_cpu_device_id);
 290
 291 static struct platform_driver sc7180_lpass_cpu_platform_driver = {
 292         .driver = {
 293                 .name = "sc7180-lpass-cpu",
 294                 .of_match_table = of_match_ptr(sc7180_lpass_cpu_device_id),
 295         },
 296         .probe = asoc_qcom_lpass_cpu_platform_probe,
 297         .remove = asoc_qcom_lpass_cpu_platform_remove,
 298         .shutdown = asoc_qcom_lpass_cpu_platform_shutdown,
 299 };
 300
 301 module_platform_driver(sc7180_lpass_cpu_platform_driver);
 302
 303 MODULE_DESCRIPTION("SC7180 LPASS CPU DRIVER");
 304 MODULE_LICENSE("GPL v2");