1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
5 * lpass-platform.c -- ALSA SoC platform driver for QTi LPASS
8 #include <linux/dma-mapping.h>
9 #include <linux/export.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <sound/pcm_params.h>
14 #include <linux/regmap.h>
15 #include <sound/soc.h>
16 #include "lpass-lpaif-reg.h"
19 #define DRV_NAME "lpass-platform"
21 struct lpass_pcm_data {
26 #define LPASS_PLATFORM_BUFFER_SIZE (24 * 2 * 1024)
27 #define LPASS_PLATFORM_PERIODS 2
29 static const struct snd_pcm_hardware lpass_platform_pcm_hardware = {
30 .info = SNDRV_PCM_INFO_MMAP |
31 SNDRV_PCM_INFO_MMAP_VALID |
32 SNDRV_PCM_INFO_INTERLEAVED |
33 SNDRV_PCM_INFO_PAUSE |
34 SNDRV_PCM_INFO_RESUME,
35 .formats = SNDRV_PCM_FMTBIT_S16 |
36 SNDRV_PCM_FMTBIT_S24 |
38 .rates = SNDRV_PCM_RATE_8000_192000,
43 .buffer_bytes_max = LPASS_PLATFORM_BUFFER_SIZE,
44 .period_bytes_max = LPASS_PLATFORM_BUFFER_SIZE /
45 LPASS_PLATFORM_PERIODS,
46 .period_bytes_min = LPASS_PLATFORM_BUFFER_SIZE /
47 LPASS_PLATFORM_PERIODS,
48 .periods_min = LPASS_PLATFORM_PERIODS,
49 .periods_max = LPASS_PLATFORM_PERIODS,
53 static int lpass_platform_alloc_dmactl_fields(struct device *dev,
56 struct lpass_data *drvdata = dev_get_drvdata(dev);
57 struct lpass_variant *v = drvdata->variant;
58 struct lpaif_dmactl *rd_dmactl, *wr_dmactl;
61 drvdata->rd_dmactl = devm_kzalloc(dev, sizeof(struct lpaif_dmactl),
63 if (drvdata->rd_dmactl == NULL)
66 drvdata->wr_dmactl = devm_kzalloc(dev, sizeof(struct lpaif_dmactl),
68 if (drvdata->wr_dmactl == NULL)
71 rd_dmactl = drvdata->rd_dmactl;
72 wr_dmactl = drvdata->wr_dmactl;
74 rval = devm_regmap_field_bulk_alloc(dev, map, &rd_dmactl->intf,
79 return devm_regmap_field_bulk_alloc(dev, map, &wr_dmactl->intf,
83 static int lpass_platform_alloc_hdmidmactl_fields(struct device *dev,
86 struct lpass_data *drvdata = dev_get_drvdata(dev);
87 struct lpass_variant *v = drvdata->variant;
88 struct lpaif_dmactl *rd_dmactl;
90 rd_dmactl = devm_kzalloc(dev, sizeof(struct lpaif_dmactl), GFP_KERNEL);
91 if (rd_dmactl == NULL)
94 drvdata->hdmi_rd_dmactl = rd_dmactl;
96 return devm_regmap_field_bulk_alloc(dev, map, &rd_dmactl->bursten,
97 &v->hdmi_rdma_bursten, 8);
100 static int lpass_platform_pcmops_open(struct snd_soc_component *component,
101 struct snd_pcm_substream *substream)
103 struct snd_pcm_runtime *runtime = substream->runtime;
104 struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
105 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
106 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
107 struct lpass_variant *v = drvdata->variant;
108 int ret, dma_ch, dir = substream->stream;
109 struct lpass_pcm_data *data;
111 unsigned int dai_id = cpu_dai->driver->id;
113 component->id = dai_id;
114 data = kzalloc(sizeof(*data), GFP_KERNEL);
118 data->i2s_port = cpu_dai->driver->id;
119 runtime->private_data = data;
121 if (v->alloc_dma_channel)
122 dma_ch = v->alloc_dma_channel(drvdata, dir, dai_id);
131 if (cpu_dai->driver->id == LPASS_DP_RX) {
132 map = drvdata->hdmiif_map;
133 drvdata->hdmi_substream[dma_ch] = substream;
135 map = drvdata->lpaif_map;
136 drvdata->substream[dma_ch] = substream;
138 data->dma_ch = dma_ch;
139 ret = regmap_write(map,
140 LPAIF_DMACTL_REG(v, dma_ch, dir, data->i2s_port), 0);
142 dev_err(soc_runtime->dev,
143 "error writing to rdmactl reg: %d\n", ret);
146 snd_soc_set_runtime_hwparams(substream, &lpass_platform_pcm_hardware);
148 runtime->dma_bytes = lpass_platform_pcm_hardware.buffer_bytes_max;
150 ret = snd_pcm_hw_constraint_integer(runtime,
151 SNDRV_PCM_HW_PARAM_PERIODS);
154 dev_err(soc_runtime->dev, "setting constraints failed: %d\n",
162 static int lpass_platform_pcmops_close(struct snd_soc_component *component,
163 struct snd_pcm_substream *substream)
165 struct snd_pcm_runtime *runtime = substream->runtime;
166 struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
167 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
168 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
169 struct lpass_variant *v = drvdata->variant;
170 struct lpass_pcm_data *data;
171 unsigned int dai_id = cpu_dai->driver->id;
173 data = runtime->private_data;
174 if (dai_id == LPASS_DP_RX)
175 drvdata->hdmi_substream[data->dma_ch] = NULL;
177 drvdata->substream[data->dma_ch] = NULL;
178 if (v->free_dma_channel)
179 v->free_dma_channel(drvdata, data->dma_ch, dai_id);
185 static int lpass_platform_pcmops_hw_params(struct snd_soc_component *component,
186 struct snd_pcm_substream *substream,
187 struct snd_pcm_hw_params *params)
189 struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
190 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
191 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
192 struct snd_pcm_runtime *rt = substream->runtime;
193 struct lpass_pcm_data *pcm_data = rt->private_data;
194 struct lpass_variant *v = drvdata->variant;
195 snd_pcm_format_t format = params_format(params);
196 unsigned int channels = params_channels(params);
198 struct lpaif_dmactl *dmactl;
199 int id, dir = substream->stream;
201 int ret, dma_port = pcm_data->i2s_port + v->dmactl_audif_start;
202 unsigned int dai_id = cpu_dai->driver->id;
204 if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
205 id = pcm_data->dma_ch;
206 if (dai_id == LPASS_DP_RX)
207 dmactl = drvdata->hdmi_rd_dmactl;
209 dmactl = drvdata->rd_dmactl;
212 dmactl = drvdata->wr_dmactl;
213 id = pcm_data->dma_ch - v->wrdma_channel_start;
216 bitwidth = snd_pcm_format_width(format);
218 dev_err(soc_runtime->dev, "invalid bit width given: %d\n",
223 ret = regmap_fields_write(dmactl->bursten, id, LPAIF_DMACTL_BURSTEN_INCR4);
225 dev_err(soc_runtime->dev, "error updating bursten field: %d\n", ret);
229 ret = regmap_fields_write(dmactl->fifowm, id, LPAIF_DMACTL_FIFOWM_8);
231 dev_err(soc_runtime->dev, "error updating fifowm field: %d\n", ret);
237 ret = regmap_fields_write(dmactl->burst8, id,
238 LPAIF_DMACTL_BURSTEN_INCR4);
240 dev_err(soc_runtime->dev, "error updating burst8en field: %d\n", ret);
243 ret = regmap_fields_write(dmactl->burst16, id,
244 LPAIF_DMACTL_BURSTEN_INCR4);
246 dev_err(soc_runtime->dev, "error updating burst16en field: %d\n", ret);
249 ret = regmap_fields_write(dmactl->dynburst, id,
250 LPAIF_DMACTL_BURSTEN_INCR4);
252 dev_err(soc_runtime->dev, "error updating dynbursten field: %d\n", ret);
259 case MI2S_QUATERNARY:
261 ret = regmap_fields_write(dmactl->intf, id,
262 LPAIF_DMACTL_AUDINTF(dma_port));
264 dev_err(soc_runtime->dev, "error updating audio interface field: %d\n",
271 dev_err(soc_runtime->dev, "%s: invalid interface: %d\n", __func__, dai_id);
279 regval = LPAIF_DMACTL_WPSCNT_ONE;
282 regval = LPAIF_DMACTL_WPSCNT_TWO;
285 regval = LPAIF_DMACTL_WPSCNT_THREE;
288 regval = LPAIF_DMACTL_WPSCNT_FOUR;
291 dev_err(soc_runtime->dev, "invalid PCM config given: bw=%d, ch=%u\n",
300 regval = LPAIF_DMACTL_WPSCNT_ONE;
303 regval = (dai_id == LPASS_DP_RX ?
304 LPAIF_DMACTL_WPSCNT_ONE :
305 LPAIF_DMACTL_WPSCNT_TWO);
308 regval = (dai_id == LPASS_DP_RX ?
309 LPAIF_DMACTL_WPSCNT_TWO :
310 LPAIF_DMACTL_WPSCNT_FOUR);
313 regval = (dai_id == LPASS_DP_RX ?
314 LPAIF_DMACTL_WPSCNT_THREE :
315 LPAIF_DMACTL_WPSCNT_SIX);
318 regval = (dai_id == LPASS_DP_RX ?
319 LPAIF_DMACTL_WPSCNT_FOUR :
320 LPAIF_DMACTL_WPSCNT_EIGHT);
323 dev_err(soc_runtime->dev, "invalid PCM config given: bw=%d, ch=%u\n",
329 dev_err(soc_runtime->dev, "invalid PCM config given: bw=%d, ch=%u\n",
334 ret = regmap_fields_write(dmactl->wpscnt, id, regval);
336 dev_err(soc_runtime->dev, "error writing to dmactl reg: %d\n",
344 static int lpass_platform_pcmops_hw_free(struct snd_soc_component *component,
345 struct snd_pcm_substream *substream)
347 struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
348 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
349 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
350 struct snd_pcm_runtime *rt = substream->runtime;
351 struct lpass_pcm_data *pcm_data = rt->private_data;
352 struct lpass_variant *v = drvdata->variant;
356 unsigned int dai_id = cpu_dai->driver->id;
358 if (dai_id == LPASS_DP_RX)
359 map = drvdata->hdmiif_map;
361 map = drvdata->lpaif_map;
363 reg = LPAIF_DMACTL_REG(v, pcm_data->dma_ch, substream->stream, dai_id);
364 ret = regmap_write(map, reg, 0);
366 dev_err(soc_runtime->dev, "error writing to rdmactl reg: %d\n",
372 static int lpass_platform_pcmops_prepare(struct snd_soc_component *component,
373 struct snd_pcm_substream *substream)
375 struct snd_pcm_runtime *runtime = substream->runtime;
376 struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
377 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
378 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
379 struct snd_pcm_runtime *rt = substream->runtime;
380 struct lpass_pcm_data *pcm_data = rt->private_data;
381 struct lpass_variant *v = drvdata->variant;
382 struct lpaif_dmactl *dmactl;
384 int ret, id, ch, dir = substream->stream;
385 unsigned int dai_id = cpu_dai->driver->id;
388 ch = pcm_data->dma_ch;
389 if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
390 if (dai_id == LPASS_DP_RX) {
391 dmactl = drvdata->hdmi_rd_dmactl;
392 map = drvdata->hdmiif_map;
394 dmactl = drvdata->rd_dmactl;
395 map = drvdata->lpaif_map;
398 id = pcm_data->dma_ch;
400 dmactl = drvdata->wr_dmactl;
401 id = pcm_data->dma_ch - v->wrdma_channel_start;
402 map = drvdata->lpaif_map;
405 ret = regmap_write(map, LPAIF_DMABASE_REG(v, ch, dir, dai_id),
408 dev_err(soc_runtime->dev, "error writing to rdmabase reg: %d\n",
413 ret = regmap_write(map, LPAIF_DMABUFF_REG(v, ch, dir, dai_id),
414 (snd_pcm_lib_buffer_bytes(substream) >> 2) - 1);
416 dev_err(soc_runtime->dev, "error writing to rdmabuff reg: %d\n",
421 ret = regmap_write(map, LPAIF_DMAPER_REG(v, ch, dir, dai_id),
422 (snd_pcm_lib_period_bytes(substream) >> 2) - 1);
424 dev_err(soc_runtime->dev, "error writing to rdmaper reg: %d\n",
429 ret = regmap_fields_write(dmactl->enable, id, LPAIF_DMACTL_ENABLE_ON);
431 dev_err(soc_runtime->dev, "error writing to rdmactl reg: %d\n",
439 static int lpass_platform_pcmops_trigger(struct snd_soc_component *component,
440 struct snd_pcm_substream *substream,
443 struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
444 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
445 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
446 struct snd_pcm_runtime *rt = substream->runtime;
447 struct lpass_pcm_data *pcm_data = rt->private_data;
448 struct lpass_variant *v = drvdata->variant;
449 struct lpaif_dmactl *dmactl;
452 int dir = substream->stream;
453 unsigned int reg_irqclr = 0, val_irqclr = 0;
454 unsigned int reg_irqen = 0, val_irqen = 0, val_mask = 0;
455 unsigned int dai_id = cpu_dai->driver->id;
457 ch = pcm_data->dma_ch;
458 if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
459 id = pcm_data->dma_ch;
460 if (dai_id == LPASS_DP_RX) {
461 dmactl = drvdata->hdmi_rd_dmactl;
462 map = drvdata->hdmiif_map;
464 dmactl = drvdata->rd_dmactl;
465 map = drvdata->lpaif_map;
468 dmactl = drvdata->wr_dmactl;
469 id = pcm_data->dma_ch - v->wrdma_channel_start;
470 map = drvdata->lpaif_map;
474 case SNDRV_PCM_TRIGGER_START:
475 case SNDRV_PCM_TRIGGER_RESUME:
476 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
477 ret = regmap_fields_write(dmactl->enable, id,
478 LPAIF_DMACTL_ENABLE_ON);
480 dev_err(soc_runtime->dev,
481 "error writing to rdmactl reg: %d\n", ret);
486 ret = regmap_fields_write(dmactl->dyncclk, id,
487 LPAIF_DMACTL_DYNCLK_ON);
489 dev_err(soc_runtime->dev,
490 "error writing to rdmactl reg: %d\n", ret);
493 reg_irqclr = LPASS_HDMITX_APP_IRQCLEAR_REG(v);
494 val_irqclr = (LPAIF_IRQ_ALL(ch) |
495 LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(ch) |
496 LPAIF_IRQ_HDMI_METADONE |
497 LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(ch));
499 reg_irqen = LPASS_HDMITX_APP_IRQEN_REG(v);
500 val_mask = (LPAIF_IRQ_ALL(ch) |
501 LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(ch) |
502 LPAIF_IRQ_HDMI_METADONE |
503 LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(ch));
504 val_irqen = (LPAIF_IRQ_ALL(ch) |
505 LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(ch) |
506 LPAIF_IRQ_HDMI_METADONE |
507 LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(ch));
512 case MI2S_QUATERNARY:
514 reg_irqclr = LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
515 val_irqclr = LPAIF_IRQ_ALL(ch);
518 reg_irqen = LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST);
519 val_mask = LPAIF_IRQ_ALL(ch);
520 val_irqen = LPAIF_IRQ_ALL(ch);
523 dev_err(soc_runtime->dev, "%s: invalid %d interface\n", __func__, dai_id);
527 ret = regmap_update_bits(map, reg_irqclr, val_irqclr, val_irqclr);
529 dev_err(soc_runtime->dev, "error writing to irqclear reg: %d\n", ret);
532 ret = regmap_update_bits(map, reg_irqen, val_mask, val_irqen);
534 dev_err(soc_runtime->dev, "error writing to irqen reg: %d\n", ret);
538 case SNDRV_PCM_TRIGGER_STOP:
539 case SNDRV_PCM_TRIGGER_SUSPEND:
540 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
541 ret = regmap_fields_write(dmactl->enable, id,
542 LPAIF_DMACTL_ENABLE_OFF);
544 dev_err(soc_runtime->dev,
545 "error writing to rdmactl reg: %d\n", ret);
550 ret = regmap_fields_write(dmactl->dyncclk, id,
551 LPAIF_DMACTL_DYNCLK_OFF);
553 dev_err(soc_runtime->dev,
554 "error writing to rdmactl reg: %d\n", ret);
557 reg_irqen = LPASS_HDMITX_APP_IRQEN_REG(v);
558 val_mask = (LPAIF_IRQ_ALL(ch) |
559 LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(ch) |
560 LPAIF_IRQ_HDMI_METADONE |
561 LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(ch));
567 case MI2S_QUATERNARY:
569 reg_irqen = LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST);
570 val_mask = LPAIF_IRQ_ALL(ch);
574 dev_err(soc_runtime->dev, "%s: invalid %d interface\n", __func__, dai_id);
578 ret = regmap_update_bits(map, reg_irqen, val_mask, val_irqen);
580 dev_err(soc_runtime->dev,
581 "error writing to irqen reg: %d\n", ret);
590 static snd_pcm_uframes_t lpass_platform_pcmops_pointer(
591 struct snd_soc_component *component,
592 struct snd_pcm_substream *substream)
594 struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
595 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
596 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
597 struct snd_pcm_runtime *rt = substream->runtime;
598 struct lpass_pcm_data *pcm_data = rt->private_data;
599 struct lpass_variant *v = drvdata->variant;
600 unsigned int base_addr, curr_addr;
601 int ret, ch, dir = substream->stream;
603 unsigned int dai_id = cpu_dai->driver->id;
605 if (dai_id == LPASS_DP_RX)
606 map = drvdata->hdmiif_map;
608 map = drvdata->lpaif_map;
610 ch = pcm_data->dma_ch;
612 ret = regmap_read(map,
613 LPAIF_DMABASE_REG(v, ch, dir, dai_id), &base_addr);
615 dev_err(soc_runtime->dev,
616 "error reading from rdmabase reg: %d\n", ret);
620 ret = regmap_read(map,
621 LPAIF_DMACURR_REG(v, ch, dir, dai_id), &curr_addr);
623 dev_err(soc_runtime->dev,
624 "error reading from rdmacurr reg: %d\n", ret);
628 return bytes_to_frames(substream->runtime, curr_addr - base_addr);
631 static irqreturn_t lpass_dma_interrupt_handler(
632 struct snd_pcm_substream *substream,
633 struct lpass_data *drvdata,
634 int chan, u32 interrupts)
636 struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
637 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
638 struct lpass_variant *v = drvdata->variant;
639 irqreturn_t ret = IRQ_NONE;
641 unsigned int reg, val, mask;
643 unsigned int dai_id = cpu_dai->driver->id;
645 mask = LPAIF_IRQ_ALL(chan);
648 map = drvdata->hdmiif_map;
649 reg = LPASS_HDMITX_APP_IRQCLEAR_REG(v);
650 val = (LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(chan) |
651 LPAIF_IRQ_HDMI_METADONE |
652 LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(chan));
657 case MI2S_QUATERNARY:
659 map = drvdata->lpaif_map;
660 reg = LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
664 dev_err(soc_runtime->dev, "%s: invalid %d interface\n", __func__, dai_id);
667 if (interrupts & LPAIF_IRQ_PER(chan)) {
668 rv = regmap_update_bits(map, reg, mask, (LPAIF_IRQ_PER(chan) | val));
670 dev_err(soc_runtime->dev,
671 "error writing to irqclear reg: %d\n", rv);
674 snd_pcm_period_elapsed(substream);
678 if (interrupts & LPAIF_IRQ_XRUN(chan)) {
679 rv = regmap_update_bits(map, reg, mask, (LPAIF_IRQ_XRUN(chan) | val));
681 dev_err(soc_runtime->dev,
682 "error writing to irqclear reg: %d\n", rv);
685 dev_warn(soc_runtime->dev, "xrun warning\n");
686 snd_pcm_stop_xrun(substream);
690 if (interrupts & LPAIF_IRQ_ERR(chan)) {
691 rv = regmap_update_bits(map, reg, mask, (LPAIF_IRQ_ERR(chan) | val));
693 dev_err(soc_runtime->dev,
694 "error writing to irqclear reg: %d\n", rv);
697 dev_err(soc_runtime->dev, "bus access error\n");
698 snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED);
702 if (interrupts & val) {
703 rv = regmap_write(map, reg, val);
705 dev_err(soc_runtime->dev,
706 "error writing to irqclear reg: %d\n", rv);
715 static irqreturn_t lpass_platform_lpaif_irq(int irq, void *data)
717 struct lpass_data *drvdata = data;
718 struct lpass_variant *v = drvdata->variant;
722 rv = regmap_read(drvdata->lpaif_map,
723 LPAIF_IRQSTAT_REG(v, LPAIF_IRQ_PORT_HOST), &irqs);
725 pr_err("error reading from irqstat reg: %d\n", rv);
729 /* Handle per channel interrupts */
730 for (chan = 0; chan < LPASS_MAX_DMA_CHANNELS; chan++) {
731 if (irqs & LPAIF_IRQ_ALL(chan) && drvdata->substream[chan]) {
732 rv = lpass_dma_interrupt_handler(
733 drvdata->substream[chan],
734 drvdata, chan, irqs);
735 if (rv != IRQ_HANDLED)
743 static irqreturn_t lpass_platform_hdmiif_irq(int irq, void *data)
745 struct lpass_data *drvdata = data;
746 struct lpass_variant *v = drvdata->variant;
750 rv = regmap_read(drvdata->hdmiif_map,
751 LPASS_HDMITX_APP_IRQSTAT_REG(v), &irqs);
753 pr_err("error reading from irqstat reg: %d\n", rv);
757 /* Handle per channel interrupts */
758 for (chan = 0; chan < LPASS_MAX_HDMI_DMA_CHANNELS; chan++) {
759 if (irqs & (LPAIF_IRQ_ALL(chan) | LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(chan) |
760 LPAIF_IRQ_HDMI_METADONE |
761 LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(chan))
762 && drvdata->hdmi_substream[chan]) {
763 rv = lpass_dma_interrupt_handler(
764 drvdata->hdmi_substream[chan],
765 drvdata, chan, irqs);
766 if (rv != IRQ_HANDLED)
774 static int lpass_platform_pcm_new(struct snd_soc_component *component,
775 struct snd_soc_pcm_runtime *soc_runtime)
777 struct snd_pcm *pcm = soc_runtime->pcm;
778 size_t size = lpass_platform_pcm_hardware.buffer_bytes_max;
780 return snd_pcm_set_fixed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
781 component->dev, size);
784 static int lpass_platform_pcmops_suspend(struct snd_soc_component *component)
786 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
788 unsigned int dai_id = component->id;
790 if (dai_id == LPASS_DP_RX)
791 map = drvdata->hdmiif_map;
793 map = drvdata->lpaif_map;
795 regcache_cache_only(map, true);
796 regcache_mark_dirty(map);
801 static int lpass_platform_pcmops_resume(struct snd_soc_component *component)
803 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
805 unsigned int dai_id = component->id;
807 if (dai_id == LPASS_DP_RX)
808 map = drvdata->hdmiif_map;
810 map = drvdata->lpaif_map;
812 regcache_cache_only(map, false);
813 return regcache_sync(map);
817 static const struct snd_soc_component_driver lpass_component_driver = {
819 .open = lpass_platform_pcmops_open,
820 .close = lpass_platform_pcmops_close,
821 .hw_params = lpass_platform_pcmops_hw_params,
822 .hw_free = lpass_platform_pcmops_hw_free,
823 .prepare = lpass_platform_pcmops_prepare,
824 .trigger = lpass_platform_pcmops_trigger,
825 .pointer = lpass_platform_pcmops_pointer,
826 .pcm_construct = lpass_platform_pcm_new,
827 .suspend = lpass_platform_pcmops_suspend,
828 .resume = lpass_platform_pcmops_resume,
832 int asoc_qcom_lpass_platform_register(struct platform_device *pdev)
834 struct lpass_data *drvdata = platform_get_drvdata(pdev);
835 struct lpass_variant *v = drvdata->variant;
838 drvdata->lpaif_irq = platform_get_irq_byname(pdev, "lpass-irq-lpaif");
839 if (drvdata->lpaif_irq < 0)
842 /* ensure audio hardware is disabled */
843 ret = regmap_write(drvdata->lpaif_map,
844 LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST), 0);
846 dev_err(&pdev->dev, "error writing to irqen reg: %d\n", ret);
850 ret = devm_request_irq(&pdev->dev, drvdata->lpaif_irq,
851 lpass_platform_lpaif_irq, IRQF_TRIGGER_RISING,
852 "lpass-irq-lpaif", drvdata);
854 dev_err(&pdev->dev, "irq request failed: %d\n", ret);
858 ret = lpass_platform_alloc_dmactl_fields(&pdev->dev,
862 "error initializing dmactl fields: %d\n", ret);
866 if (drvdata->hdmi_port_enable) {
867 drvdata->hdmiif_irq = platform_get_irq_byname(pdev, "lpass-irq-hdmi");
868 if (drvdata->hdmiif_irq < 0)
871 ret = devm_request_irq(&pdev->dev, drvdata->hdmiif_irq,
872 lpass_platform_hdmiif_irq, 0, "lpass-irq-hdmi", drvdata);
874 dev_err(&pdev->dev, "irq hdmi request failed: %d\n", ret);
877 ret = regmap_write(drvdata->hdmiif_map,
878 LPASS_HDMITX_APP_IRQEN_REG(v), 0);
880 dev_err(&pdev->dev, "error writing to hdmi irqen reg: %d\n", ret);
884 ret = lpass_platform_alloc_hdmidmactl_fields(&pdev->dev,
885 drvdata->hdmiif_map);
888 "error initializing hdmidmactl fields: %d\n", ret);
892 return devm_snd_soc_register_component(&pdev->dev,
893 &lpass_component_driver, NULL, 0);
895 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_platform_register);
897 MODULE_DESCRIPTION("QTi LPASS Platform Driver");
898 MODULE_LICENSE("GPL v2");