sound/soc/qcom/lpass-cpu.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
   4  *
   5  * lpass-cpu.c -- ALSA SoC CPU DAI driver for QTi LPASS
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/platform_device.h>
  14 #include <sound/pcm.h>
  15 #include <sound/pcm_params.h>
  16 #include <linux/regmap.h>
  17 #include <sound/soc.h>
  18 #include <sound/soc-dai.h>
  19 #include "lpass-lpaif-reg.h"
  20 #include "lpass.h"
  21
  22 #define LPASS_CPU_MAX_MI2S_LINES        4
  23 #define LPASS_CPU_I2S_SD0_MASK          BIT(0)
  24 #define LPASS_CPU_I2S_SD1_MASK          BIT(1)
  25 #define LPASS_CPU_I2S_SD2_MASK          BIT(2)
  26 #define LPASS_CPU_I2S_SD3_MASK          BIT(3)
  27 #define LPASS_CPU_I2S_SD0_1_MASK        GENMASK(1, 0)
  28 #define LPASS_CPU_I2S_SD2_3_MASK        GENMASK(3, 2)
  29 #define LPASS_CPU_I2S_SD0_1_2_MASK      GENMASK(2, 0)
  30 #define LPASS_CPU_I2S_SD0_1_2_3_MASK    GENMASK(3, 0)
  31
  32 static int lpass_cpu_init_i2sctl_bitfields(struct device *dev,
  33                         struct lpaif_i2sctl *i2sctl, struct regmap *map)
  34 {
  35         struct lpass_data *drvdata = dev_get_drvdata(dev);
  36         struct lpass_variant *v = drvdata->variant;
  37
  38         i2sctl->loopback = devm_regmap_field_alloc(dev, map, v->loopback);
  39         i2sctl->spken = devm_regmap_field_alloc(dev, map, v->spken);
  40         i2sctl->spkmode = devm_regmap_field_alloc(dev, map, v->spkmode);
  41         i2sctl->spkmono = devm_regmap_field_alloc(dev, map, v->spkmono);
  42         i2sctl->micen = devm_regmap_field_alloc(dev, map, v->micen);
  43         i2sctl->micmode = devm_regmap_field_alloc(dev, map, v->micmode);
  44         i2sctl->micmono = devm_regmap_field_alloc(dev, map, v->micmono);
  45         i2sctl->wssrc = devm_regmap_field_alloc(dev, map, v->wssrc);
  46         i2sctl->bitwidth = devm_regmap_field_alloc(dev, map, v->bitwidth);
  47
  48         if (IS_ERR(i2sctl->loopback) || IS_ERR(i2sctl->spken) ||
  49             IS_ERR(i2sctl->spkmode) || IS_ERR(i2sctl->spkmono) ||
  50             IS_ERR(i2sctl->micen) || IS_ERR(i2sctl->micmode) ||
  51             IS_ERR(i2sctl->micmono) || IS_ERR(i2sctl->wssrc) ||
  52             IS_ERR(i2sctl->bitwidth))
  53                 return -EINVAL;
  54
  55         return 0;
  56 }
  57
  58 static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id,
  59                 unsigned int freq, int dir)
  60 {
  61         struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
  62         int ret;
  63
  64         ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->driver->id], freq);
  65         if (ret)
  66                 dev_err(dai->dev, "error setting mi2s osrclk to %u: %d\n",
  67                         freq, ret);
  68
  69         return ret;
  70 }
  71
  72 static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream,
  73                 struct snd_soc_dai *dai)
  74 {
  75         struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
  76         int ret;
  77
  78         ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->driver->id]);
  79         if (ret) {
  80                 dev_err(dai->dev, "error in enabling mi2s osr clk: %d\n", ret);
  81                 return ret;
  82         }
  83         ret = clk_prepare(drvdata->mi2s_bit_clk[dai->driver->id]);
  84         if (ret) {
  85                 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
  86                 clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
  87                 return ret;
  88         }
  89         return 0;
  90 }
  91
  92 static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream,
  93                 struct snd_soc_dai *dai)
  94 {
  95         struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
  96
  97         clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
  98         clk_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]);
  99 }
 100
 101 static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream,
 102                 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 103 {
 104         struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
 105         struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
 106         unsigned int id = dai->driver->id;
 107         snd_pcm_format_t format = params_format(params);
 108         unsigned int channels = params_channels(params);
 109         unsigned int rate = params_rate(params);
 110         unsigned int mode;
 111         unsigned int regval;
 112         int bitwidth, ret;
 113
 114         bitwidth = snd_pcm_format_width(format);
 115         if (bitwidth < 0) {
 116                 dev_err(dai->dev, "invalid bit width given: %d\n", bitwidth);
 117                 return bitwidth;
 118         }
 119
 120         ret = regmap_fields_write(i2sctl->loopback, id,
 121                                  LPAIF_I2SCTL_LOOPBACK_DISABLE);
 122         if (ret) {
 123                 dev_err(dai->dev, "error updating loopback field: %d\n", ret);
 124                 return ret;
 125         }
 126
 127         ret = regmap_fields_write(i2sctl->wssrc, id,
 128                                  LPAIF_I2SCTL_WSSRC_INTERNAL);
 129         if (ret) {
 130                 dev_err(dai->dev, "error updating wssrc field: %d\n", ret);
 131                 return ret;
 132         }
 133
 134         switch (bitwidth) {
 135         case 16:
 136                 regval = LPAIF_I2SCTL_BITWIDTH_16;
 137                 break;
 138         case 24:
 139                 regval = LPAIF_I2SCTL_BITWIDTH_24;
 140                 break;
 141         case 32:
 142                 regval = LPAIF_I2SCTL_BITWIDTH_32;
 143                 break;
 144         default:
 145                 dev_err(dai->dev, "invalid bitwidth given: %d\n", bitwidth);
 146                 return -EINVAL;
 147         }
 148
 149         ret = regmap_fields_write(i2sctl->bitwidth, id, regval);
 150         if (ret) {
 151                 dev_err(dai->dev, "error updating bitwidth field: %d\n", ret);
 152                 return ret;
 153         }
 154
 155         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 156                 mode = drvdata->mi2s_playback_sd_mode[id];
 157         else
 158                 mode = drvdata->mi2s_capture_sd_mode[id];
 159
 160         if (!mode) {
 161                 dev_err(dai->dev, "no line is assigned\n");
 162                 return -EINVAL;
 163         }
 164
 165         switch (channels) {
 166         case 1:
 167         case 2:
 168                 switch (mode) {
 169                 case LPAIF_I2SCTL_MODE_QUAD01:
 170                 case LPAIF_I2SCTL_MODE_6CH:
 171                 case LPAIF_I2SCTL_MODE_8CH:
 172                         mode = LPAIF_I2SCTL_MODE_SD0;
 173                         break;
 174                 case LPAIF_I2SCTL_MODE_QUAD23:
 175                         mode = LPAIF_I2SCTL_MODE_SD2;
 176                         break;
 177                 }
 178
 179                 break;
 180         case 4:
 181                 if (mode < LPAIF_I2SCTL_MODE_QUAD01) {
 182                         dev_err(dai->dev, "cannot configure 4 channels with mode %d\n",
 183                                 mode);
 184                         return -EINVAL;
 185                 }
 186
 187                 switch (mode) {
 188                 case LPAIF_I2SCTL_MODE_6CH:
 189                 case LPAIF_I2SCTL_MODE_8CH:
 190                         mode = LPAIF_I2SCTL_MODE_QUAD01;
 191                         break;
 192                 }
 193                 break;
 194         case 6:
 195                 if (mode < LPAIF_I2SCTL_MODE_6CH) {
 196                         dev_err(dai->dev, "cannot configure 6 channels with mode %d\n",
 197                                 mode);
 198                         return -EINVAL;
 199                 }
 200
 201                 switch (mode) {
 202                 case LPAIF_I2SCTL_MODE_8CH:
 203                         mode = LPAIF_I2SCTL_MODE_6CH;
 204                         break;
 205                 }
 206                 break;
 207         case 8:
 208                 if (mode < LPAIF_I2SCTL_MODE_8CH) {
 209                         dev_err(dai->dev, "cannot configure 8 channels with mode %d\n",
 210                                 mode);
 211                         return -EINVAL;
 212                 }
 213                 break;
 214         default:
 215                 dev_err(dai->dev, "invalid channels given: %u\n", channels);
 216                 return -EINVAL;
 217         }
 218
 219         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 220                 ret = regmap_fields_write(i2sctl->spkmode, id,
 221                                          LPAIF_I2SCTL_SPKMODE(mode));
 222                 if (ret) {
 223                         dev_err(dai->dev, "error writing to i2sctl spkr mode: %d\n",
 224                                 ret);
 225                         return ret;
 226                 }
 227                 if (channels >= 2)
 228                         ret = regmap_fields_write(i2sctl->spkmono, id,
 229                                                  LPAIF_I2SCTL_SPKMONO_STEREO);
 230                 else
 231                         ret = regmap_fields_write(i2sctl->spkmono, id,
 232                                                  LPAIF_I2SCTL_SPKMONO_MONO);
 233         } else {
 234                 ret = regmap_fields_write(i2sctl->micmode, id,
 235                                          LPAIF_I2SCTL_MICMODE(mode));
 236                 if (ret) {
 237                         dev_err(dai->dev, "error writing to i2sctl mic mode: %d\n",
 238                                 ret);
 239                         return ret;
 240                 }
 241                 if (channels >= 2)
 242                         ret = regmap_fields_write(i2sctl->micmono, id,
 243                                                  LPAIF_I2SCTL_MICMONO_STEREO);
 244                 else
 245                         ret = regmap_fields_write(i2sctl->micmono, id,
 246                                                  LPAIF_I2SCTL_MICMONO_MONO);
 247         }
 248
 249         if (ret) {
 250                 dev_err(dai->dev, "error writing to i2sctl channels mode: %d\n",
 251                         ret);
 252                 return ret;
 253         }
 254
 255         ret = clk_set_rate(drvdata->mi2s_bit_clk[id],
 256                            rate * bitwidth * 2);
 257         if (ret) {
 258                 dev_err(dai->dev, "error setting mi2s bitclk to %u: %d\n",
 259                         rate * bitwidth * 2, ret);
 260                 return ret;
 261         }
 262
 263         return 0;
 264 }
 265
 266 static int lpass_cpu_daiops_trigger(struct snd_pcm_substream *substream,
 267                 int cmd, struct snd_soc_dai *dai)
 268 {
 269         struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
 270         struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
 271         unsigned int id = dai->driver->id;
 272         int ret = -EINVAL;
 273         unsigned int val = 0;
 274
 275         ret = regmap_read(drvdata->lpaif_map,
 276                                 LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id), &val);
 277         if (ret) {
 278                 dev_err(dai->dev, "error reading from i2sctl reg: %d\n", ret);
 279                 return ret;
 280         }
 281         if (val == LPAIF_I2SCTL_RESET_STATE) {
 282                 dev_err(dai->dev, "error in i2sctl register state\n");
 283                 return -ENOTRECOVERABLE;
 284         }
 285
 286         switch (cmd) {
 287         case SNDRV_PCM_TRIGGER_START:
 288         case SNDRV_PCM_TRIGGER_RESUME:
 289         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 290                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 291                         ret = regmap_fields_write(i2sctl->spken, id,
 292                                                  LPAIF_I2SCTL_SPKEN_ENABLE);
 293                 } else  {
 294                         ret = regmap_fields_write(i2sctl->micen, id,
 295                                                  LPAIF_I2SCTL_MICEN_ENABLE);
 296                 }
 297                 if (ret)
 298                         dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
 299                                 ret);
 300
 301                 if (drvdata->bit_clk_state[id] == LPAIF_BIT_CLK_DISABLE) {
 302                         ret = clk_enable(drvdata->mi2s_bit_clk[id]);
 303                         if (ret) {
 304                                 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
 305                                 clk_disable(drvdata->mi2s_osr_clk[id]);
 306                                 return ret;
 307                         }
 308                         drvdata->bit_clk_state[id] = LPAIF_BIT_CLK_ENABLE;
 309                 }
 310
 311                 break;
 312         case SNDRV_PCM_TRIGGER_STOP:
 313         case SNDRV_PCM_TRIGGER_SUSPEND:
 314         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 315                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 316                         ret = regmap_fields_write(i2sctl->spken, id,
 317                                                  LPAIF_I2SCTL_SPKEN_DISABLE);
 318                 } else  {
 319                         ret = regmap_fields_write(i2sctl->micen, id,
 320                                                  LPAIF_I2SCTL_MICEN_DISABLE);
 321                 }
 322                 if (ret)
 323                         dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
 324                                 ret);
 325                 if (drvdata->bit_clk_state[id] == LPAIF_BIT_CLK_ENABLE) {
 326                         clk_disable(drvdata->mi2s_bit_clk[dai->driver->id]);
 327                         drvdata->bit_clk_state[id] = LPAIF_BIT_CLK_DISABLE;
 328                 }
 329                 break;
 330         }
 331
 332         return ret;
 333 }
 334
 335 const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops = {
 336         .set_sysclk     = lpass_cpu_daiops_set_sysclk,
 337         .startup        = lpass_cpu_daiops_startup,
 338         .shutdown       = lpass_cpu_daiops_shutdown,
 339         .hw_params      = lpass_cpu_daiops_hw_params,
 340         .trigger        = lpass_cpu_daiops_trigger,
 341 };
 342 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_ops);
 343
 344 int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai)
 345 {
 346         struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
 347         int ret;
 348
 349         /* ensure audio hardware is disabled */
 350         ret = regmap_write(drvdata->lpaif_map,
 351                         LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id), 0);
 352         if (ret)
 353                 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
 354
 355         return ret;
 356 }
 357 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_probe);
 358
 359 static const struct snd_soc_component_driver lpass_cpu_comp_driver = {
 360         .name = "lpass-cpu",
 361 };
 362
 363 static bool lpass_cpu_regmap_writeable(struct device *dev, unsigned int reg)
 364 {
 365         struct lpass_data *drvdata = dev_get_drvdata(dev);
 366         struct lpass_variant *v = drvdata->variant;
 367         int i;
 368
 369         for (i = 0; i < v->i2s_ports; ++i)
 370                 if (reg == LPAIF_I2SCTL_REG(v, i))
 371                         return true;
 372
 373         for (i = 0; i < v->irq_ports; ++i) {
 374                 if (reg == LPAIF_IRQEN_REG(v, i))
 375                         return true;
 376                 if (reg == LPAIF_IRQCLEAR_REG(v, i))
 377                         return true;
 378         }
 379
 380         for (i = 0; i < v->rdma_channels; ++i) {
 381                 if (reg == LPAIF_RDMACTL_REG(v, i))
 382                         return true;
 383                 if (reg == LPAIF_RDMABASE_REG(v, i))
 384                         return true;
 385                 if (reg == LPAIF_RDMABUFF_REG(v, i))
 386                         return true;
 387                 if (reg == LPAIF_RDMAPER_REG(v, i))
 388                         return true;
 389         }
 390
 391         for (i = 0; i < v->wrdma_channels; ++i) {
 392                 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
 393                         return true;
 394                 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
 395                         return true;
 396                 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
 397                         return true;
 398                 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
 399                         return true;
 400         }
 401
 402         return false;
 403 }
 404
 405 static bool lpass_cpu_regmap_readable(struct device *dev, unsigned int reg)
 406 {
 407         struct lpass_data *drvdata = dev_get_drvdata(dev);
 408         struct lpass_variant *v = drvdata->variant;
 409         int i;
 410
 411         for (i = 0; i < v->i2s_ports; ++i)
 412                 if (reg == LPAIF_I2SCTL_REG(v, i))
 413                         return true;
 414
 415         for (i = 0; i < v->irq_ports; ++i) {
 416                 if (reg == LPAIF_IRQEN_REG(v, i))
 417                         return true;
 418                 if (reg == LPAIF_IRQSTAT_REG(v, i))
 419                         return true;
 420         }
 421
 422         for (i = 0; i < v->rdma_channels; ++i) {
 423                 if (reg == LPAIF_RDMACTL_REG(v, i))
 424                         return true;
 425                 if (reg == LPAIF_RDMABASE_REG(v, i))
 426                         return true;
 427                 if (reg == LPAIF_RDMABUFF_REG(v, i))
 428                         return true;
 429                 if (reg == LPAIF_RDMACURR_REG(v, i))
 430                         return true;
 431                 if (reg == LPAIF_RDMAPER_REG(v, i))
 432                         return true;
 433         }
 434
 435         for (i = 0; i < v->wrdma_channels; ++i) {
 436                 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
 437                         return true;
 438                 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
 439                         return true;
 440                 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
 441                         return true;
 442                 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
 443                         return true;
 444                 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
 445                         return true;
 446         }
 447
 448         return false;
 449 }
 450
 451 static bool lpass_cpu_regmap_volatile(struct device *dev, unsigned int reg)
 452 {
 453         struct lpass_data *drvdata = dev_get_drvdata(dev);
 454         struct lpass_variant *v = drvdata->variant;
 455         int i;
 456
 457         for (i = 0; i < v->i2s_ports; ++i)
 458                 if (reg == LPAIF_I2SCTL_REG(v, i))
 459                         return true;
 460         for (i = 0; i < v->irq_ports; ++i)
 461                 if (reg == LPAIF_IRQSTAT_REG(v, i))
 462                         return true;
 463
 464         for (i = 0; i < v->rdma_channels; ++i)
 465                 if (reg == LPAIF_RDMACURR_REG(v, i) || reg == LPAIF_RDMACTL_REG(v, i))
 466                         return true;
 467
 468         for (i = 0; i < v->wrdma_channels; ++i)
 469                 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start) ||
 470                         reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
 471                         return true;
 472
 473         return false;
 474 }
 475
 476 static struct regmap_config lpass_cpu_regmap_config = {
 477         .reg_bits = 32,
 478         .reg_stride = 4,
 479         .val_bits = 32,
 480         .writeable_reg = lpass_cpu_regmap_writeable,
 481         .readable_reg = lpass_cpu_regmap_readable,
 482         .volatile_reg = lpass_cpu_regmap_volatile,
 483         .cache_type = REGCACHE_FLAT,
 484 };
 485
 486 static int lpass_hdmi_init_bitfields(struct device *dev, struct regmap *map)
 487 {
 488         struct lpass_data *drvdata = dev_get_drvdata(dev);
 489         struct lpass_variant *v = drvdata->variant;
 490         unsigned int i;
 491         struct lpass_hdmi_tx_ctl *tx_ctl;
 492         struct regmap_field *legacy_en;
 493         struct lpass_vbit_ctrl *vbit_ctl;
 494         struct regmap_field *tx_parity;
 495         struct lpass_dp_metadata_ctl *meta_ctl;
 496         struct lpass_sstream_ctl *sstream_ctl;
 497         struct regmap_field *ch_msb;
 498         struct regmap_field *ch_lsb;
 499         struct lpass_hdmitx_dmactl *tx_dmactl;
 500         int rval;
 501
 502         tx_ctl = devm_kzalloc(dev, sizeof(*tx_ctl), GFP_KERNEL);
 503         if (!tx_ctl)
 504                 return -ENOMEM;
 505
 506         QCOM_REGMAP_FIELD_ALLOC(dev, map, v->soft_reset, tx_ctl->soft_reset);
 507         QCOM_REGMAP_FIELD_ALLOC(dev, map, v->force_reset, tx_ctl->force_reset);
 508         drvdata->tx_ctl = tx_ctl;
 509
 510         QCOM_REGMAP_FIELD_ALLOC(dev, map, v->legacy_en, legacy_en);
 511         drvdata->hdmitx_legacy_en = legacy_en;
 512
 513         vbit_ctl = devm_kzalloc(dev, sizeof(*vbit_ctl), GFP_KERNEL);
 514         if (!vbit_ctl)
 515                 return -ENOMEM;
 516
 517         QCOM_REGMAP_FIELD_ALLOC(dev, map, v->replace_vbit, vbit_ctl->replace_vbit);
 518         QCOM_REGMAP_FIELD_ALLOC(dev, map, v->vbit_stream, vbit_ctl->vbit_stream);
 519         drvdata->vbit_ctl = vbit_ctl;
 520
 521
 522         QCOM_REGMAP_FIELD_ALLOC(dev, map, v->calc_en, tx_parity);
 523         drvdata->hdmitx_parity_calc_en = tx_parity;
 524
 525         meta_ctl = devm_kzalloc(dev, sizeof(*meta_ctl), GFP_KERNEL);
 526         if (!meta_ctl)
 527                 return -ENOMEM;
 528
 529         rval = devm_regmap_field_bulk_alloc(dev, map, &meta_ctl->mute, &v->mute, 7);
 530         if (rval)
 531                 return rval;
 532         drvdata->meta_ctl = meta_ctl;
 533
 534         sstream_ctl = devm_kzalloc(dev, sizeof(*sstream_ctl), GFP_KERNEL);
 535         if (!sstream_ctl)
 536                 return -ENOMEM;
 537
 538         rval = devm_regmap_field_bulk_alloc(dev, map, &sstream_ctl->sstream_en, &v->sstream_en, 9);
 539         if (rval)
 540                 return rval;
 541
 542         drvdata->sstream_ctl = sstream_ctl;
 543
 544         for (i = 0; i < LPASS_MAX_HDMI_DMA_CHANNELS; i++) {
 545                 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->msb_bits, ch_msb);
 546                 drvdata->hdmitx_ch_msb[i] = ch_msb;
 547
 548                 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->lsb_bits, ch_lsb);
 549                 drvdata->hdmitx_ch_lsb[i] = ch_lsb;
 550
 551                 tx_dmactl = devm_kzalloc(dev, sizeof(*tx_dmactl), GFP_KERNEL);
 552                 if (!tx_dmactl)
 553                         return -ENOMEM;
 554
 555                 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_chs, tx_dmactl->use_hw_chs);
 556                 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_usr, tx_dmactl->use_hw_usr);
 557                 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_chs_sel, tx_dmactl->hw_chs_sel);
 558                 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_usr_sel, tx_dmactl->hw_usr_sel);
 559                 drvdata->hdmi_tx_dmactl[i] = tx_dmactl;
 560         }
 561         return 0;
 562 }
 563
 564 static bool lpass_hdmi_regmap_writeable(struct device *dev, unsigned int reg)
 565 {
 566         struct lpass_data *drvdata = dev_get_drvdata(dev);
 567         struct lpass_variant *v = drvdata->variant;
 568         int i;
 569
 570         if (reg == LPASS_HDMI_TX_CTL_ADDR(v))
 571                 return true;
 572         if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
 573                 return true;
 574         if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v))
 575                 return true;
 576         if (reg == LPASS_HDMI_TX_PARITY_ADDR(v))
 577                 return true;
 578         if (reg == LPASS_HDMI_TX_DP_ADDR(v))
 579                 return true;
 580         if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v))
 581                 return true;
 582         if (reg == LPASS_HDMITX_APP_IRQEN_REG(v))
 583                 return true;
 584         if (reg == LPASS_HDMITX_APP_IRQCLEAR_REG(v))
 585                 return true;
 586
 587         for (i = 0; i < v->hdmi_rdma_channels; i++) {
 588                 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i))
 589                         return true;
 590                 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i))
 591                         return true;
 592                 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i))
 593                         return true;
 594         }
 595
 596         for (i = 0; i < v->rdma_channels; ++i) {
 597                 if (reg == LPAIF_HDMI_RDMACTL_REG(v, i))
 598                         return true;
 599                 if (reg == LPAIF_HDMI_RDMABASE_REG(v, i))
 600                         return true;
 601                 if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i))
 602                         return true;
 603                 if (reg == LPAIF_HDMI_RDMAPER_REG(v, i))
 604                         return true;
 605         }
 606         return false;
 607 }
 608
 609 static bool lpass_hdmi_regmap_readable(struct device *dev, unsigned int reg)
 610 {
 611         struct lpass_data *drvdata = dev_get_drvdata(dev);
 612         struct lpass_variant *v = drvdata->variant;
 613         int i;
 614
 615         if (reg == LPASS_HDMI_TX_CTL_ADDR(v))
 616                 return true;
 617         if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
 618                 return true;
 619         if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v))
 620                 return true;
 621
 622         for (i = 0; i < v->hdmi_rdma_channels; i++) {
 623                 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i))
 624                         return true;
 625                 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i))
 626                         return true;
 627                 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i))
 628                         return true;
 629         }
 630
 631         if (reg == LPASS_HDMI_TX_PARITY_ADDR(v))
 632                 return true;
 633         if (reg == LPASS_HDMI_TX_DP_ADDR(v))
 634                 return true;
 635         if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v))
 636                 return true;
 637         if (reg == LPASS_HDMITX_APP_IRQEN_REG(v))
 638                 return true;
 639         if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v))
 640                 return true;
 641
 642         for (i = 0; i < v->rdma_channels; ++i) {
 643                 if (reg == LPAIF_HDMI_RDMACTL_REG(v, i))
 644                         return true;
 645                 if (reg == LPAIF_HDMI_RDMABASE_REG(v, i))
 646                         return true;
 647                 if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i))
 648                         return true;
 649                 if (reg == LPAIF_HDMI_RDMAPER_REG(v, i))
 650                         return true;
 651                 if (reg == LPAIF_HDMI_RDMACURR_REG(v, i))
 652                         return true;
 653         }
 654
 655         return false;
 656 }
 657
 658 static bool lpass_hdmi_regmap_volatile(struct device *dev, unsigned int reg)
 659 {
 660         struct lpass_data *drvdata = dev_get_drvdata(dev);
 661         struct lpass_variant *v = drvdata->variant;
 662         int i;
 663
 664         if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v))
 665                 return true;
 666         if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
 667                 return true;
 668
 669         for (i = 0; i < v->rdma_channels; ++i) {
 670                 if (reg == LPAIF_HDMI_RDMACURR_REG(v, i))
 671                         return true;
 672         }
 673         return false;
 674 }
 675
 676 static struct regmap_config lpass_hdmi_regmap_config = {
 677         .reg_bits = 32,
 678         .reg_stride = 4,
 679         .val_bits = 32,
 680         .writeable_reg = lpass_hdmi_regmap_writeable,
 681         .readable_reg = lpass_hdmi_regmap_readable,
 682         .volatile_reg = lpass_hdmi_regmap_volatile,
 683         .cache_type = REGCACHE_FLAT,
 684 };
 685
 686 static unsigned int of_lpass_cpu_parse_sd_lines(struct device *dev,
 687                                                 struct device_node *node,
 688                                                 const char *name)
 689 {
 690         unsigned int lines[LPASS_CPU_MAX_MI2S_LINES];
 691         unsigned int sd_line_mask = 0;
 692         int num_lines, i;
 693
 694         num_lines = of_property_read_variable_u32_array(node, name, lines, 0,
 695                                                         LPASS_CPU_MAX_MI2S_LINES);
 696         if (num_lines < 0)
 697                 return LPAIF_I2SCTL_MODE_NONE;
 698
 699         for (i = 0; i < num_lines; i++)
 700                 sd_line_mask |= BIT(lines[i]);
 701
 702         switch (sd_line_mask) {
 703         case LPASS_CPU_I2S_SD0_MASK:
 704                 return LPAIF_I2SCTL_MODE_SD0;
 705         case LPASS_CPU_I2S_SD1_MASK:
 706                 return LPAIF_I2SCTL_MODE_SD1;
 707         case LPASS_CPU_I2S_SD2_MASK:
 708                 return LPAIF_I2SCTL_MODE_SD2;
 709         case LPASS_CPU_I2S_SD3_MASK:
 710                 return LPAIF_I2SCTL_MODE_SD3;
 711         case LPASS_CPU_I2S_SD0_1_MASK:
 712                 return LPAIF_I2SCTL_MODE_QUAD01;
 713         case LPASS_CPU_I2S_SD2_3_MASK:
 714                 return LPAIF_I2SCTL_MODE_QUAD23;
 715         case LPASS_CPU_I2S_SD0_1_2_MASK:
 716                 return LPAIF_I2SCTL_MODE_6CH;
 717         case LPASS_CPU_I2S_SD0_1_2_3_MASK:
 718                 return LPAIF_I2SCTL_MODE_8CH;
 719         default:
 720                 dev_err(dev, "Unsupported SD line mask: %#x\n", sd_line_mask);
 721                 return LPAIF_I2SCTL_MODE_NONE;
 722         }
 723 }
 724
 725 static void of_lpass_cpu_parse_dai_data(struct device *dev,
 726                                         struct lpass_data *data)
 727 {
 728         struct device_node *node;
 729         int ret, id;
 730
 731         /* Allow all channels by default for backwards compatibility */
 732         for (id = 0; id < data->variant->num_dai; id++) {
 733                 data->mi2s_playback_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH;
 734                 data->mi2s_capture_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH;
 735         }
 736
 737         for_each_child_of_node(dev->of_node, node) {
 738                 ret = of_property_read_u32(node, "reg", &id);
 739                 if (ret || id < 0 || id >= data->variant->num_dai) {
 740                         dev_err(dev, "valid dai id not found: %d\n", ret);
 741                         continue;
 742                 }
 743                 if (id == LPASS_DP_RX) {
 744                         data->hdmi_port_enable = 1;
 745                         dev_err(dev, "HDMI Port is enabled: %d\n", id);
 746                 } else {
 747                         data->mi2s_playback_sd_mode[id] =
 748                                 of_lpass_cpu_parse_sd_lines(dev, node,
 749                                                             "qcom,playback-sd-lines");
 750                         data->mi2s_capture_sd_mode[id] =
 751                                 of_lpass_cpu_parse_sd_lines(dev, node,
 752                                                     "qcom,capture-sd-lines");
 753                 }
 754         }
 755 }
 756
 757 int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev)
 758 {
 759         struct lpass_data *drvdata;
 760         struct device_node *dsp_of_node;
 761         struct resource *res;
 762         struct lpass_variant *variant;
 763         struct device *dev = &pdev->dev;
 764         const struct of_device_id *match;
 765         int ret, i, dai_id;
 766
 767         dsp_of_node = of_parse_phandle(pdev->dev.of_node, "qcom,adsp", 0);
 768         if (dsp_of_node) {
 769                 dev_err(dev, "DSP exists and holds audio resources\n");
 770                 return -EBUSY;
 771         }
 772
 773         drvdata = devm_kzalloc(dev, sizeof(struct lpass_data), GFP_KERNEL);
 774         if (!drvdata)
 775                 return -ENOMEM;
 776         platform_set_drvdata(pdev, drvdata);
 777
 778         match = of_match_device(dev->driver->of_match_table, dev);
 779         if (!match || !match->data)
 780                 return -EINVAL;
 781
 782         drvdata->variant = (struct lpass_variant *)match->data;
 783         variant = drvdata->variant;
 784
 785         of_lpass_cpu_parse_dai_data(dev, drvdata);
 786
 787         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-lpaif");
 788
 789         drvdata->lpaif = devm_ioremap_resource(dev, res);
 790         if (IS_ERR((void const __force *)drvdata->lpaif)) {
 791                 dev_err(dev, "error mapping reg resource: %ld\n",
 792                                 PTR_ERR((void const __force *)drvdata->lpaif));
 793                 return PTR_ERR((void const __force *)drvdata->lpaif);
 794         }
 795
 796         lpass_cpu_regmap_config.max_register = LPAIF_WRDMAPER_REG(variant,
 797                                                 variant->wrdma_channels +
 798                                                 variant->wrdma_channel_start);
 799
 800         drvdata->lpaif_map = devm_regmap_init_mmio(dev, drvdata->lpaif,
 801                         &lpass_cpu_regmap_config);
 802         if (IS_ERR(drvdata->lpaif_map)) {
 803                 dev_err(dev, "error initializing regmap: %ld\n",
 804                         PTR_ERR(drvdata->lpaif_map));
 805                 return PTR_ERR(drvdata->lpaif_map);
 806         }
 807
 808         if (drvdata->hdmi_port_enable) {
 809                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-hdmiif");
 810
 811                 drvdata->hdmiif = devm_ioremap_resource(dev, res);
 812                 if (IS_ERR((void const __force *)drvdata->hdmiif)) {
 813                         dev_err(dev, "error mapping reg resource: %ld\n",
 814                                         PTR_ERR((void const __force *)drvdata->hdmiif));
 815                         return PTR_ERR((void const __force *)drvdata->hdmiif);
 816                 }
 817
 818                 lpass_hdmi_regmap_config.max_register = LPAIF_HDMI_RDMAPER_REG(variant,
 819                                         variant->hdmi_rdma_channels);
 820                 drvdata->hdmiif_map = devm_regmap_init_mmio(dev, drvdata->hdmiif,
 821                                         &lpass_hdmi_regmap_config);
 822                 if (IS_ERR(drvdata->hdmiif_map)) {
 823                         dev_err(dev, "error initializing regmap: %ld\n",
 824                         PTR_ERR(drvdata->hdmiif_map));
 825                         return PTR_ERR(drvdata->hdmiif_map);
 826                 }
 827         }
 828
 829         if (variant->init) {
 830                 ret = variant->init(pdev);
 831                 if (ret) {
 832                         dev_err(dev, "error initializing variant: %d\n", ret);
 833                         return ret;
 834                 }
 835         }
 836
 837         for (i = 0; i < variant->num_dai; i++) {
 838                 dai_id = variant->dai_driver[i].id;
 839                 if (dai_id == LPASS_DP_RX)
 840                         continue;
 841
 842                 drvdata->mi2s_osr_clk[dai_id] = devm_clk_get(dev,
 843                                              variant->dai_osr_clk_names[i]);
 844                 if (IS_ERR(drvdata->mi2s_osr_clk[dai_id])) {
 845                         dev_warn(dev,
 846                                 "%s() error getting optional %s: %ld\n",
 847                                 __func__,
 848                                 variant->dai_osr_clk_names[i],
 849                                 PTR_ERR(drvdata->mi2s_osr_clk[dai_id]));
 850
 851                         drvdata->mi2s_osr_clk[dai_id] = NULL;
 852                 }
 853
 854                 drvdata->mi2s_bit_clk[dai_id] = devm_clk_get(dev,
 855                                                 variant->dai_bit_clk_names[i]);
 856                 if (IS_ERR(drvdata->mi2s_bit_clk[dai_id])) {
 857                         dev_err(dev,
 858                                 "error getting %s: %ld\n",
 859                                 variant->dai_bit_clk_names[i],
 860                                 PTR_ERR(drvdata->mi2s_bit_clk[dai_id]));
 861                         return PTR_ERR(drvdata->mi2s_bit_clk[dai_id]);
 862                 }
 863                 drvdata->bit_clk_state[dai_id] = LPAIF_BIT_CLK_DISABLE;
 864         }
 865
 866         /* Allocation for i2sctl regmap fields */
 867         drvdata->i2sctl = devm_kzalloc(&pdev->dev, sizeof(struct lpaif_i2sctl),
 868                                         GFP_KERNEL);
 869
 870         /* Initialize bitfields for dai I2SCTL register */
 871         ret = lpass_cpu_init_i2sctl_bitfields(dev, drvdata->i2sctl,
 872                                                 drvdata->lpaif_map);
 873         if (ret) {
 874                 dev_err(dev, "error init i2sctl field: %d\n", ret);
 875                 return ret;
 876         }
 877
 878         if (drvdata->hdmi_port_enable) {
 879                 ret = lpass_hdmi_init_bitfields(dev, drvdata->hdmiif_map);
 880                 if (ret) {
 881                         dev_err(dev, "%s error  hdmi init failed\n", __func__);
 882                         return ret;
 883                 }
 884         }
 885         ret = devm_snd_soc_register_component(dev,
 886                                               &lpass_cpu_comp_driver,
 887                                               variant->dai_driver,
 888                                               variant->num_dai);
 889         if (ret) {
 890                 dev_err(dev, "error registering cpu driver: %d\n", ret);
 891                 goto err;
 892         }
 893
 894         ret = asoc_qcom_lpass_platform_register(pdev);
 895         if (ret) {
 896                 dev_err(dev, "error registering platform driver: %d\n", ret);
 897                 goto err;
 898         }
 899
 900 err:
 901         return ret;
 902 }
 903 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_probe);
 904
 905 int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev)
 906 {
 907         struct lpass_data *drvdata = platform_get_drvdata(pdev);
 908
 909         if (drvdata->variant->exit)
 910                 drvdata->variant->exit(pdev);
 911
 912
 913         return 0;
 914 }
 915 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_remove);
 916
 917 void asoc_qcom_lpass_cpu_platform_shutdown(struct platform_device *pdev)
 918 {
 919         struct lpass_data *drvdata = platform_get_drvdata(pdev);
 920
 921         if (drvdata->variant->exit)
 922                 drvdata->variant->exit(pdev);
 923
 924 }
 925 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_shutdown);
 926
 927 MODULE_DESCRIPTION("QTi LPASS CPU Driver");
 928 MODULE_LICENSE("GPL v2");