sound/soc/qcom/lpass-cpu.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
   4  *
   5  * lpass-cpu.c -- ALSA SoC CPU DAI driver for QTi LPASS
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/platform_device.h>
  14 #include <sound/pcm.h>
  15 #include <sound/pcm_params.h>
  16 #include <linux/regmap.h>
  17 #include <sound/soc.h>
  18 #include <sound/soc-dai.h>
  19 #include "lpass-lpaif-reg.h"
  20 #include "lpass.h"
  21
  22 #define LPASS_CPU_MAX_MI2S_LINES        4
  23 #define LPASS_CPU_I2S_SD0_MASK          BIT(0)
  24 #define LPASS_CPU_I2S_SD1_MASK          BIT(1)
  25 #define LPASS_CPU_I2S_SD2_MASK          BIT(2)
  26 #define LPASS_CPU_I2S_SD3_MASK          BIT(3)
  27 #define LPASS_CPU_I2S_SD0_1_MASK        GENMASK(1, 0)
  28 #define LPASS_CPU_I2S_SD2_3_MASK        GENMASK(3, 2)
  29 #define LPASS_CPU_I2S_SD0_1_2_MASK      GENMASK(2, 0)
  30 #define LPASS_CPU_I2S_SD0_1_2_3_MASK    GENMASK(3, 0)
  31
  32 static int lpass_cpu_init_i2sctl_bitfields(struct device *dev,
  33                         struct lpaif_i2sctl *i2sctl, struct regmap *map)
  34 {
  35         struct lpass_data *drvdata = dev_get_drvdata(dev);
  36         struct lpass_variant *v = drvdata->variant;
  37
  38         i2sctl->loopback = devm_regmap_field_alloc(dev, map, v->loopback);
  39         i2sctl->spken = devm_regmap_field_alloc(dev, map, v->spken);
  40         i2sctl->spkmode = devm_regmap_field_alloc(dev, map, v->spkmode);
  41         i2sctl->spkmono = devm_regmap_field_alloc(dev, map, v->spkmono);
  42         i2sctl->micen = devm_regmap_field_alloc(dev, map, v->micen);
  43         i2sctl->micmode = devm_regmap_field_alloc(dev, map, v->micmode);
  44         i2sctl->micmono = devm_regmap_field_alloc(dev, map, v->micmono);
  45         i2sctl->wssrc = devm_regmap_field_alloc(dev, map, v->wssrc);
  46         i2sctl->bitwidth = devm_regmap_field_alloc(dev, map, v->bitwidth);
  47
  48         if (IS_ERR(i2sctl->loopback) || IS_ERR(i2sctl->spken) ||
  49             IS_ERR(i2sctl->spkmode) || IS_ERR(i2sctl->spkmono) ||
  50             IS_ERR(i2sctl->micen) || IS_ERR(i2sctl->micmode) ||
  51             IS_ERR(i2sctl->micmono) || IS_ERR(i2sctl->wssrc) ||
  52             IS_ERR(i2sctl->bitwidth))
  53                 return -EINVAL;
  54
  55         return 0;
  56 }
  57
  58 static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id,
  59                 unsigned int freq, int dir)
  60 {
  61         struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
  62         int ret;
  63
  64         ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->driver->id], freq);
  65         if (ret)
  66                 dev_err(dai->dev, "error setting mi2s osrclk to %u: %d\n",
  67                         freq, ret);
  68
  69         return ret;
  70 }
  71
  72 static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream,
  73                 struct snd_soc_dai *dai)
  74 {
  75         struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
  76         int ret;
  77
  78         ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->driver->id]);
  79         if (ret) {
  80                 dev_err(dai->dev, "error in enabling mi2s osr clk: %d\n", ret);
  81                 return ret;
  82         }
  83         ret = clk_prepare(drvdata->mi2s_bit_clk[dai->driver->id]);
  84         if (ret) {
  85                 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
  86                 clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
  87                 return ret;
  88         }
  89         return 0;
  90 }
  91
  92 static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream,
  93                 struct snd_soc_dai *dai)
  94 {
  95         struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
  96
  97         clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
  98         clk_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]);
  99 }
 100
 101 static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream,
 102                 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 103 {
 104         struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
 105         struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
 106         unsigned int id = dai->driver->id;
 107         snd_pcm_format_t format = params_format(params);
 108         unsigned int channels = params_channels(params);
 109         unsigned int rate = params_rate(params);
 110         unsigned int mode;
 111         unsigned int regval;
 112         int bitwidth, ret;
 113
 114         bitwidth = snd_pcm_format_width(format);
 115         if (bitwidth < 0) {
 116                 dev_err(dai->dev, "invalid bit width given: %d\n", bitwidth);
 117                 return bitwidth;
 118         }
 119
 120         ret = regmap_fields_write(i2sctl->loopback, id,
 121                                  LPAIF_I2SCTL_LOOPBACK_DISABLE);
 122         if (ret) {
 123                 dev_err(dai->dev, "error updating loopback field: %d\n", ret);
 124                 return ret;
 125         }
 126
 127         ret = regmap_fields_write(i2sctl->wssrc, id,
 128                                  LPAIF_I2SCTL_WSSRC_INTERNAL);
 129         if (ret) {
 130                 dev_err(dai->dev, "error updating wssrc field: %d\n", ret);
 131                 return ret;
 132         }
 133
 134         switch (bitwidth) {
 135         case 16:
 136                 regval = LPAIF_I2SCTL_BITWIDTH_16;
 137                 break;
 138         case 24:
 139                 regval = LPAIF_I2SCTL_BITWIDTH_24;
 140                 break;
 141         case 32:
 142                 regval = LPAIF_I2SCTL_BITWIDTH_32;
 143                 break;
 144         default:
 145                 dev_err(dai->dev, "invalid bitwidth given: %d\n", bitwidth);
 146                 return -EINVAL;
 147         }
 148
 149         ret = regmap_fields_write(i2sctl->bitwidth, id, regval);
 150         if (ret) {
 151                 dev_err(dai->dev, "error updating bitwidth field: %d\n", ret);
 152                 return ret;
 153         }
 154
 155         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 156                 mode = drvdata->mi2s_playback_sd_mode[id];
 157         else
 158                 mode = drvdata->mi2s_capture_sd_mode[id];
 159
 160         if (!mode) {
 161                 dev_err(dai->dev, "no line is assigned\n");
 162                 return -EINVAL;
 163         }
 164
 165         switch (channels) {
 166         case 1:
 167         case 2:
 168                 switch (mode) {
 169                 case LPAIF_I2SCTL_MODE_QUAD01:
 170                 case LPAIF_I2SCTL_MODE_6CH:
 171                 case LPAIF_I2SCTL_MODE_8CH:
 172                         mode = LPAIF_I2SCTL_MODE_SD0;
 173                         break;
 174                 case LPAIF_I2SCTL_MODE_QUAD23:
 175                         mode = LPAIF_I2SCTL_MODE_SD2;
 176                         break;
 177                 }
 178
 179                 break;
 180         case 4:
 181                 if (mode < LPAIF_I2SCTL_MODE_QUAD01) {
 182                         dev_err(dai->dev, "cannot configure 4 channels with mode %d\n",
 183                                 mode);
 184                         return -EINVAL;
 185                 }
 186
 187                 switch (mode) {
 188                 case LPAIF_I2SCTL_MODE_6CH:
 189                 case LPAIF_I2SCTL_MODE_8CH:
 190                         mode = LPAIF_I2SCTL_MODE_QUAD01;
 191                         break;
 192                 }
 193                 break;
 194         case 6:
 195                 if (mode < LPAIF_I2SCTL_MODE_6CH) {
 196                         dev_err(dai->dev, "cannot configure 6 channels with mode %d\n",
 197                                 mode);
 198                         return -EINVAL;
 199                 }
 200
 201                 switch (mode) {
 202                 case LPAIF_I2SCTL_MODE_8CH:
 203                         mode = LPAIF_I2SCTL_MODE_6CH;
 204                         break;
 205                 }
 206                 break;
 207         case 8:
 208                 if (mode < LPAIF_I2SCTL_MODE_8CH) {
 209                         dev_err(dai->dev, "cannot configure 8 channels with mode %d\n",
 210                                 mode);
 211                         return -EINVAL;
 212                 }
 213                 break;
 214         default:
 215                 dev_err(dai->dev, "invalid channels given: %u\n", channels);
 216                 return -EINVAL;
 217         }
 218
 219         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 220                 ret = regmap_fields_write(i2sctl->spkmode, id,
 221                                          LPAIF_I2SCTL_SPKMODE(mode));
 222                 if (ret) {
 223                         dev_err(dai->dev, "error writing to i2sctl spkr mode: %d\n",
 224                                 ret);
 225                         return ret;
 226                 }
 227                 if (channels >= 2)
 228                         ret = regmap_fields_write(i2sctl->spkmono, id,
 229                                                  LPAIF_I2SCTL_SPKMONO_STEREO);
 230                 else
 231                         ret = regmap_fields_write(i2sctl->spkmono, id,
 232                                                  LPAIF_I2SCTL_SPKMONO_MONO);
 233         } else {
 234                 ret = regmap_fields_write(i2sctl->micmode, id,
 235                                          LPAIF_I2SCTL_MICMODE(mode));
 236                 if (ret) {
 237                         dev_err(dai->dev, "error writing to i2sctl mic mode: %d\n",
 238                                 ret);
 239                         return ret;
 240                 }
 241                 if (channels >= 2)
 242                         ret = regmap_fields_write(i2sctl->micmono, id,
 243                                                  LPAIF_I2SCTL_MICMONO_STEREO);
 244                 else
 245                         ret = regmap_fields_write(i2sctl->micmono, id,
 246                                                  LPAIF_I2SCTL_MICMONO_MONO);
 247         }
 248
 249         if (ret) {
 250                 dev_err(dai->dev, "error writing to i2sctl channels mode: %d\n",
 251                         ret);
 252                 return ret;
 253         }
 254
 255         ret = clk_set_rate(drvdata->mi2s_bit_clk[id],
 256                            rate * bitwidth * 2);
 257         if (ret) {
 258                 dev_err(dai->dev, "error setting mi2s bitclk to %u: %d\n",
 259                         rate * bitwidth * 2, ret);
 260                 return ret;
 261         }
 262
 263         return 0;
 264 }
 265
 266 static int lpass_cpu_daiops_trigger(struct snd_pcm_substream *substream,
 267                 int cmd, struct snd_soc_dai *dai)
 268 {
 269         struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
 270         struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
 271         unsigned int id = dai->driver->id;
 272         int ret = -EINVAL;
 273
 274         switch (cmd) {
 275         case SNDRV_PCM_TRIGGER_START:
 276         case SNDRV_PCM_TRIGGER_RESUME:
 277         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 278                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 279                         ret = regmap_fields_write(i2sctl->spken, id,
 280                                                  LPAIF_I2SCTL_SPKEN_ENABLE);
 281                 } else  {
 282                         ret = regmap_fields_write(i2sctl->micen, id,
 283                                                  LPAIF_I2SCTL_MICEN_ENABLE);
 284                 }
 285                 if (ret)
 286                         dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
 287                                 ret);
 288
 289                 if (drvdata->bit_clk_state[id] == LPAIF_BIT_CLK_DISABLE) {
 290                         ret = clk_enable(drvdata->mi2s_bit_clk[id]);
 291                         if (ret) {
 292                                 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
 293                                 clk_disable(drvdata->mi2s_osr_clk[id]);
 294                                 return ret;
 295                         }
 296                         drvdata->bit_clk_state[id] = LPAIF_BIT_CLK_ENABLE;
 297                 }
 298
 299                 break;
 300         case SNDRV_PCM_TRIGGER_STOP:
 301         case SNDRV_PCM_TRIGGER_SUSPEND:
 302         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 303                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 304                         ret = regmap_fields_write(i2sctl->spken, id,
 305                                                  LPAIF_I2SCTL_SPKEN_DISABLE);
 306                 } else  {
 307                         ret = regmap_fields_write(i2sctl->micen, id,
 308                                                  LPAIF_I2SCTL_MICEN_DISABLE);
 309                 }
 310                 if (ret)
 311                         dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
 312                                 ret);
 313                 if (drvdata->bit_clk_state[id] == LPAIF_BIT_CLK_ENABLE) {
 314                         clk_disable(drvdata->mi2s_bit_clk[dai->driver->id]);
 315                         drvdata->bit_clk_state[id] = LPAIF_BIT_CLK_DISABLE;
 316                 }
 317                 break;
 318         }
 319
 320         return ret;
 321 }
 322
 323 const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops = {
 324         .set_sysclk     = lpass_cpu_daiops_set_sysclk,
 325         .startup        = lpass_cpu_daiops_startup,
 326         .shutdown       = lpass_cpu_daiops_shutdown,
 327         .hw_params      = lpass_cpu_daiops_hw_params,
 328         .trigger        = lpass_cpu_daiops_trigger,
 329 };
 330 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_ops);
 331
 332 int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai)
 333 {
 334         struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
 335         int ret;
 336
 337         /* ensure audio hardware is disabled */
 338         ret = regmap_write(drvdata->lpaif_map,
 339                         LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id), 0);
 340         if (ret)
 341                 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
 342
 343         return ret;
 344 }
 345 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_probe);
 346
 347 static const struct snd_soc_component_driver lpass_cpu_comp_driver = {
 348         .name = "lpass-cpu",
 349 };
 350
 351 static bool lpass_cpu_regmap_writeable(struct device *dev, unsigned int reg)
 352 {
 353         struct lpass_data *drvdata = dev_get_drvdata(dev);
 354         struct lpass_variant *v = drvdata->variant;
 355         int i;
 356
 357         for (i = 0; i < v->i2s_ports; ++i)
 358                 if (reg == LPAIF_I2SCTL_REG(v, i))
 359                         return true;
 360
 361         for (i = 0; i < v->irq_ports; ++i) {
 362                 if (reg == LPAIF_IRQEN_REG(v, i))
 363                         return true;
 364                 if (reg == LPAIF_IRQCLEAR_REG(v, i))
 365                         return true;
 366         }
 367
 368         for (i = 0; i < v->rdma_channels; ++i) {
 369                 if (reg == LPAIF_RDMACTL_REG(v, i))
 370                         return true;
 371                 if (reg == LPAIF_RDMABASE_REG(v, i))
 372                         return true;
 373                 if (reg == LPAIF_RDMABUFF_REG(v, i))
 374                         return true;
 375                 if (reg == LPAIF_RDMAPER_REG(v, i))
 376                         return true;
 377         }
 378
 379         for (i = 0; i < v->wrdma_channels; ++i) {
 380                 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
 381                         return true;
 382                 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
 383                         return true;
 384                 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
 385                         return true;
 386                 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
 387                         return true;
 388         }
 389
 390         return false;
 391 }
 392
 393 static bool lpass_cpu_regmap_readable(struct device *dev, unsigned int reg)
 394 {
 395         struct lpass_data *drvdata = dev_get_drvdata(dev);
 396         struct lpass_variant *v = drvdata->variant;
 397         int i;
 398
 399         for (i = 0; i < v->i2s_ports; ++i)
 400                 if (reg == LPAIF_I2SCTL_REG(v, i))
 401                         return true;
 402
 403         for (i = 0; i < v->irq_ports; ++i) {
 404                 if (reg == LPAIF_IRQEN_REG(v, i))
 405                         return true;
 406                 if (reg == LPAIF_IRQSTAT_REG(v, i))
 407                         return true;
 408         }
 409
 410         for (i = 0; i < v->rdma_channels; ++i) {
 411                 if (reg == LPAIF_RDMACTL_REG(v, i))
 412                         return true;
 413                 if (reg == LPAIF_RDMABASE_REG(v, i))
 414                         return true;
 415                 if (reg == LPAIF_RDMABUFF_REG(v, i))
 416                         return true;
 417                 if (reg == LPAIF_RDMACURR_REG(v, i))
 418                         return true;
 419                 if (reg == LPAIF_RDMAPER_REG(v, i))
 420                         return true;
 421         }
 422
 423         for (i = 0; i < v->wrdma_channels; ++i) {
 424                 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
 425                         return true;
 426                 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
 427                         return true;
 428                 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
 429                         return true;
 430                 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
 431                         return true;
 432                 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
 433                         return true;
 434         }
 435
 436         return false;
 437 }
 438
 439 static bool lpass_cpu_regmap_volatile(struct device *dev, unsigned int reg)
 440 {
 441         struct lpass_data *drvdata = dev_get_drvdata(dev);
 442         struct lpass_variant *v = drvdata->variant;
 443         int i;
 444
 445         for (i = 0; i < v->irq_ports; ++i)
 446                 if (reg == LPAIF_IRQSTAT_REG(v, i))
 447                         return true;
 448
 449         for (i = 0; i < v->rdma_channels; ++i)
 450                 if (reg == LPAIF_RDMACURR_REG(v, i))
 451                         return true;
 452
 453         for (i = 0; i < v->wrdma_channels; ++i)
 454                 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
 455                         return true;
 456
 457         return false;
 458 }
 459
 460 static struct regmap_config lpass_cpu_regmap_config = {
 461         .reg_bits = 32,
 462         .reg_stride = 4,
 463         .val_bits = 32,
 464         .writeable_reg = lpass_cpu_regmap_writeable,
 465         .readable_reg = lpass_cpu_regmap_readable,
 466         .volatile_reg = lpass_cpu_regmap_volatile,
 467         .cache_type = REGCACHE_FLAT,
 468 };
 469
 470 static int lpass_hdmi_init_bitfields(struct device *dev, struct regmap *map)
 471 {
 472         struct lpass_data *drvdata = dev_get_drvdata(dev);
 473         struct lpass_variant *v = drvdata->variant;
 474         unsigned int i;
 475         struct lpass_hdmi_tx_ctl *tx_ctl;
 476         struct regmap_field *legacy_en;
 477         struct lpass_vbit_ctrl *vbit_ctl;
 478         struct regmap_field *tx_parity;
 479         struct lpass_dp_metadata_ctl *meta_ctl;
 480         struct lpass_sstream_ctl *sstream_ctl;
 481         struct regmap_field *ch_msb;
 482         struct regmap_field *ch_lsb;
 483         struct lpass_hdmitx_dmactl *tx_dmactl;
 484         int rval;
 485
 486         tx_ctl = devm_kzalloc(dev, sizeof(*tx_ctl), GFP_KERNEL);
 487         if (!tx_ctl)
 488                 return -ENOMEM;
 489
 490         QCOM_REGMAP_FIELD_ALLOC(dev, map, v->soft_reset, tx_ctl->soft_reset);
 491         QCOM_REGMAP_FIELD_ALLOC(dev, map, v->force_reset, tx_ctl->force_reset);
 492         drvdata->tx_ctl = tx_ctl;
 493
 494         QCOM_REGMAP_FIELD_ALLOC(dev, map, v->legacy_en, legacy_en);
 495         drvdata->hdmitx_legacy_en = legacy_en;
 496
 497         vbit_ctl = devm_kzalloc(dev, sizeof(*vbit_ctl), GFP_KERNEL);
 498         if (!vbit_ctl)
 499                 return -ENOMEM;
 500
 501         QCOM_REGMAP_FIELD_ALLOC(dev, map, v->replace_vbit, vbit_ctl->replace_vbit);
 502         QCOM_REGMAP_FIELD_ALLOC(dev, map, v->vbit_stream, vbit_ctl->vbit_stream);
 503         drvdata->vbit_ctl = vbit_ctl;
 504
 505
 506         QCOM_REGMAP_FIELD_ALLOC(dev, map, v->calc_en, tx_parity);
 507         drvdata->hdmitx_parity_calc_en = tx_parity;
 508
 509         meta_ctl = devm_kzalloc(dev, sizeof(*meta_ctl), GFP_KERNEL);
 510         if (!meta_ctl)
 511                 return -ENOMEM;
 512
 513         rval = devm_regmap_field_bulk_alloc(dev, map, &meta_ctl->mute, &v->mute, 7);
 514         if (rval)
 515                 return rval;
 516         drvdata->meta_ctl = meta_ctl;
 517
 518         sstream_ctl = devm_kzalloc(dev, sizeof(*sstream_ctl), GFP_KERNEL);
 519         if (!sstream_ctl)
 520                 return -ENOMEM;
 521
 522         rval = devm_regmap_field_bulk_alloc(dev, map, &sstream_ctl->sstream_en, &v->sstream_en, 9);
 523         if (rval)
 524                 return rval;
 525
 526         drvdata->sstream_ctl = sstream_ctl;
 527
 528         for (i = 0; i < LPASS_MAX_HDMI_DMA_CHANNELS; i++) {
 529                 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->msb_bits, ch_msb);
 530                 drvdata->hdmitx_ch_msb[i] = ch_msb;
 531
 532                 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->lsb_bits, ch_lsb);
 533                 drvdata->hdmitx_ch_lsb[i] = ch_lsb;
 534
 535                 tx_dmactl = devm_kzalloc(dev, sizeof(*tx_dmactl), GFP_KERNEL);
 536                 if (!tx_dmactl)
 537                         return -ENOMEM;
 538
 539                 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_chs, tx_dmactl->use_hw_chs);
 540                 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_usr, tx_dmactl->use_hw_usr);
 541                 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_chs_sel, tx_dmactl->hw_chs_sel);
 542                 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_usr_sel, tx_dmactl->hw_usr_sel);
 543                 drvdata->hdmi_tx_dmactl[i] = tx_dmactl;
 544         }
 545         return 0;
 546 }
 547
 548 static bool lpass_hdmi_regmap_writeable(struct device *dev, unsigned int reg)
 549 {
 550         struct lpass_data *drvdata = dev_get_drvdata(dev);
 551         struct lpass_variant *v = drvdata->variant;
 552         int i;
 553
 554         if (reg == LPASS_HDMI_TX_CTL_ADDR(v))
 555                 return true;
 556         if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
 557                 return true;
 558         if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v))
 559                 return true;
 560         if (reg == LPASS_HDMI_TX_PARITY_ADDR(v))
 561                 return true;
 562         if (reg == LPASS_HDMI_TX_DP_ADDR(v))
 563                 return true;
 564         if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v))
 565                 return true;
 566         if (reg == LPASS_HDMITX_APP_IRQEN_REG(v))
 567                 return true;
 568         if (reg == LPASS_HDMITX_APP_IRQCLEAR_REG(v))
 569                 return true;
 570
 571         for (i = 0; i < v->hdmi_rdma_channels; i++) {
 572                 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i))
 573                         return true;
 574                 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i))
 575                         return true;
 576                 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i))
 577                         return true;
 578         }
 579
 580         for (i = 0; i < v->rdma_channels; ++i) {
 581                 if (reg == LPAIF_HDMI_RDMACTL_REG(v, i))
 582                         return true;
 583                 if (reg == LPAIF_HDMI_RDMABASE_REG(v, i))
 584                         return true;
 585                 if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i))
 586                         return true;
 587                 if (reg == LPAIF_HDMI_RDMAPER_REG(v, i))
 588                         return true;
 589         }
 590         return false;
 591 }
 592
 593 static bool lpass_hdmi_regmap_readable(struct device *dev, unsigned int reg)
 594 {
 595         struct lpass_data *drvdata = dev_get_drvdata(dev);
 596         struct lpass_variant *v = drvdata->variant;
 597         int i;
 598
 599         if (reg == LPASS_HDMI_TX_CTL_ADDR(v))
 600                 return true;
 601         if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
 602                 return true;
 603         if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v))
 604                 return true;
 605
 606         for (i = 0; i < v->hdmi_rdma_channels; i++) {
 607                 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i))
 608                         return true;
 609                 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i))
 610                         return true;
 611                 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i))
 612                         return true;
 613         }
 614
 615         if (reg == LPASS_HDMI_TX_PARITY_ADDR(v))
 616                 return true;
 617         if (reg == LPASS_HDMI_TX_DP_ADDR(v))
 618                 return true;
 619         if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v))
 620                 return true;
 621         if (reg == LPASS_HDMITX_APP_IRQEN_REG(v))
 622                 return true;
 623         if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v))
 624                 return true;
 625
 626         for (i = 0; i < v->rdma_channels; ++i) {
 627                 if (reg == LPAIF_HDMI_RDMACTL_REG(v, i))
 628                         return true;
 629                 if (reg == LPAIF_HDMI_RDMABASE_REG(v, i))
 630                         return true;
 631                 if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i))
 632                         return true;
 633                 if (reg == LPAIF_HDMI_RDMAPER_REG(v, i))
 634                         return true;
 635                 if (reg == LPAIF_HDMI_RDMACURR_REG(v, i))
 636                         return true;
 637         }
 638
 639         return false;
 640 }
 641
 642 static bool lpass_hdmi_regmap_volatile(struct device *dev, unsigned int reg)
 643 {
 644         struct lpass_data *drvdata = dev_get_drvdata(dev);
 645         struct lpass_variant *v = drvdata->variant;
 646         int i;
 647
 648         if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v))
 649                 return true;
 650         if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
 651                 return true;
 652
 653         for (i = 0; i < v->rdma_channels; ++i) {
 654                 if (reg == LPAIF_HDMI_RDMACURR_REG(v, i))
 655                         return true;
 656         }
 657         return false;
 658 }
 659
 660 static struct regmap_config lpass_hdmi_regmap_config = {
 661         .reg_bits = 32,
 662         .reg_stride = 4,
 663         .val_bits = 32,
 664         .writeable_reg = lpass_hdmi_regmap_writeable,
 665         .readable_reg = lpass_hdmi_regmap_readable,
 666         .volatile_reg = lpass_hdmi_regmap_volatile,
 667         .cache_type = REGCACHE_FLAT,
 668 };
 669
 670 static unsigned int of_lpass_cpu_parse_sd_lines(struct device *dev,
 671                                                 struct device_node *node,
 672                                                 const char *name)
 673 {
 674         unsigned int lines[LPASS_CPU_MAX_MI2S_LINES];
 675         unsigned int sd_line_mask = 0;
 676         int num_lines, i;
 677
 678         num_lines = of_property_read_variable_u32_array(node, name, lines, 0,
 679                                                         LPASS_CPU_MAX_MI2S_LINES);
 680         if (num_lines < 0)
 681                 return LPAIF_I2SCTL_MODE_NONE;
 682
 683         for (i = 0; i < num_lines; i++)
 684                 sd_line_mask |= BIT(lines[i]);
 685
 686         switch (sd_line_mask) {
 687         case LPASS_CPU_I2S_SD0_MASK:
 688                 return LPAIF_I2SCTL_MODE_SD0;
 689         case LPASS_CPU_I2S_SD1_MASK:
 690                 return LPAIF_I2SCTL_MODE_SD1;
 691         case LPASS_CPU_I2S_SD2_MASK:
 692                 return LPAIF_I2SCTL_MODE_SD2;
 693         case LPASS_CPU_I2S_SD3_MASK:
 694                 return LPAIF_I2SCTL_MODE_SD3;
 695         case LPASS_CPU_I2S_SD0_1_MASK:
 696                 return LPAIF_I2SCTL_MODE_QUAD01;
 697         case LPASS_CPU_I2S_SD2_3_MASK:
 698                 return LPAIF_I2SCTL_MODE_QUAD23;
 699         case LPASS_CPU_I2S_SD0_1_2_MASK:
 700                 return LPAIF_I2SCTL_MODE_6CH;
 701         case LPASS_CPU_I2S_SD0_1_2_3_MASK:
 702                 return LPAIF_I2SCTL_MODE_8CH;
 703         default:
 704                 dev_err(dev, "Unsupported SD line mask: %#x\n", sd_line_mask);
 705                 return LPAIF_I2SCTL_MODE_NONE;
 706         }
 707 }
 708
 709 static void of_lpass_cpu_parse_dai_data(struct device *dev,
 710                                         struct lpass_data *data)
 711 {
 712         struct device_node *node;
 713         int ret, id;
 714
 715         /* Allow all channels by default for backwards compatibility */
 716         for (id = 0; id < data->variant->num_dai; id++) {
 717                 data->mi2s_playback_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH;
 718                 data->mi2s_capture_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH;
 719         }
 720
 721         for_each_child_of_node(dev->of_node, node) {
 722                 ret = of_property_read_u32(node, "reg", &id);
 723                 if (ret || id < 0 || id >= data->variant->num_dai) {
 724                         dev_err(dev, "valid dai id not found: %d\n", ret);
 725                         continue;
 726                 }
 727                 if (id == LPASS_DP_RX) {
 728                         data->hdmi_port_enable = 1;
 729                         dev_err(dev, "HDMI Port is enabled: %d\n", id);
 730                 } else {
 731                         data->mi2s_playback_sd_mode[id] =
 732                                 of_lpass_cpu_parse_sd_lines(dev, node,
 733                                                             "qcom,playback-sd-lines");
 734                         data->mi2s_capture_sd_mode[id] =
 735                                 of_lpass_cpu_parse_sd_lines(dev, node,
 736                                                     "qcom,capture-sd-lines");
 737                 }
 738         }
 739 }
 740
 741 int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev)
 742 {
 743         struct lpass_data *drvdata;
 744         struct device_node *dsp_of_node;
 745         struct resource *res;
 746         struct lpass_variant *variant;
 747         struct device *dev = &pdev->dev;
 748         const struct of_device_id *match;
 749         int ret, i, dai_id;
 750
 751         dsp_of_node = of_parse_phandle(pdev->dev.of_node, "qcom,adsp", 0);
 752         if (dsp_of_node) {
 753                 dev_err(dev, "DSP exists and holds audio resources\n");
 754                 return -EBUSY;
 755         }
 756
 757         drvdata = devm_kzalloc(dev, sizeof(struct lpass_data), GFP_KERNEL);
 758         if (!drvdata)
 759                 return -ENOMEM;
 760         platform_set_drvdata(pdev, drvdata);
 761
 762         match = of_match_device(dev->driver->of_match_table, dev);
 763         if (!match || !match->data)
 764                 return -EINVAL;
 765
 766         drvdata->variant = (struct lpass_variant *)match->data;
 767         variant = drvdata->variant;
 768
 769         of_lpass_cpu_parse_dai_data(dev, drvdata);
 770
 771         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-lpaif");
 772
 773         drvdata->lpaif = devm_ioremap_resource(dev, res);
 774         if (IS_ERR((void const __force *)drvdata->lpaif)) {
 775                 dev_err(dev, "error mapping reg resource: %ld\n",
 776                                 PTR_ERR((void const __force *)drvdata->lpaif));
 777                 return PTR_ERR((void const __force *)drvdata->lpaif);
 778         }
 779
 780         lpass_cpu_regmap_config.max_register = LPAIF_WRDMAPER_REG(variant,
 781                                                 variant->wrdma_channels +
 782                                                 variant->wrdma_channel_start);
 783
 784         drvdata->lpaif_map = devm_regmap_init_mmio(dev, drvdata->lpaif,
 785                         &lpass_cpu_regmap_config);
 786         if (IS_ERR(drvdata->lpaif_map)) {
 787                 dev_err(dev, "error initializing regmap: %ld\n",
 788                         PTR_ERR(drvdata->lpaif_map));
 789                 return PTR_ERR(drvdata->lpaif_map);
 790         }
 791
 792         if (drvdata->hdmi_port_enable) {
 793                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-hdmiif");
 794
 795                 drvdata->hdmiif = devm_ioremap_resource(dev, res);
 796                 if (IS_ERR((void const __force *)drvdata->hdmiif)) {
 797                         dev_err(dev, "error mapping reg resource: %ld\n",
 798                                         PTR_ERR((void const __force *)drvdata->hdmiif));
 799                         return PTR_ERR((void const __force *)drvdata->hdmiif);
 800                 }
 801
 802                 lpass_hdmi_regmap_config.max_register = LPAIF_HDMI_RDMAPER_REG(variant,
 803                                         variant->hdmi_rdma_channels);
 804                 drvdata->hdmiif_map = devm_regmap_init_mmio(dev, drvdata->hdmiif,
 805                                         &lpass_hdmi_regmap_config);
 806                 if (IS_ERR(drvdata->hdmiif_map)) {
 807                         dev_err(dev, "error initializing regmap: %ld\n",
 808                         PTR_ERR(drvdata->hdmiif_map));
 809                         return PTR_ERR(drvdata->hdmiif_map);
 810                 }
 811         }
 812
 813         if (variant->init) {
 814                 ret = variant->init(pdev);
 815                 if (ret) {
 816                         dev_err(dev, "error initializing variant: %d\n", ret);
 817                         return ret;
 818                 }
 819         }
 820
 821         for (i = 0; i < variant->num_dai; i++) {
 822                 dai_id = variant->dai_driver[i].id;
 823                 if (dai_id == LPASS_DP_RX)
 824                         continue;
 825
 826                 drvdata->mi2s_osr_clk[dai_id] = devm_clk_get(dev,
 827                                              variant->dai_osr_clk_names[i]);
 828                 if (IS_ERR(drvdata->mi2s_osr_clk[dai_id])) {
 829                         dev_warn(dev,
 830                                 "%s() error getting optional %s: %ld\n",
 831                                 __func__,
 832                                 variant->dai_osr_clk_names[i],
 833                                 PTR_ERR(drvdata->mi2s_osr_clk[dai_id]));
 834
 835                         drvdata->mi2s_osr_clk[dai_id] = NULL;
 836                 }
 837
 838                 drvdata->mi2s_bit_clk[dai_id] = devm_clk_get(dev,
 839                                                 variant->dai_bit_clk_names[i]);
 840                 if (IS_ERR(drvdata->mi2s_bit_clk[dai_id])) {
 841                         dev_err(dev,
 842                                 "error getting %s: %ld\n",
 843                                 variant->dai_bit_clk_names[i],
 844                                 PTR_ERR(drvdata->mi2s_bit_clk[dai_id]));
 845                         return PTR_ERR(drvdata->mi2s_bit_clk[dai_id]);
 846                 }
 847                 drvdata->bit_clk_state[dai_id] = LPAIF_BIT_CLK_DISABLE;
 848         }
 849
 850         /* Allocation for i2sctl regmap fields */
 851         drvdata->i2sctl = devm_kzalloc(&pdev->dev, sizeof(struct lpaif_i2sctl),
 852                                         GFP_KERNEL);
 853
 854         /* Initialize bitfields for dai I2SCTL register */
 855         ret = lpass_cpu_init_i2sctl_bitfields(dev, drvdata->i2sctl,
 856                                                 drvdata->lpaif_map);
 857         if (ret) {
 858                 dev_err(dev, "error init i2sctl field: %d\n", ret);
 859                 return ret;
 860         }
 861
 862         if (drvdata->hdmi_port_enable) {
 863                 ret = lpass_hdmi_init_bitfields(dev, drvdata->hdmiif_map);
 864                 if (ret) {
 865                         dev_err(dev, "%s error  hdmi init failed\n", __func__);
 866                         return ret;
 867                 }
 868         }
 869         ret = devm_snd_soc_register_component(dev,
 870                                               &lpass_cpu_comp_driver,
 871                                               variant->dai_driver,
 872                                               variant->num_dai);
 873         if (ret) {
 874                 dev_err(dev, "error registering cpu driver: %d\n", ret);
 875                 goto err;
 876         }
 877
 878         ret = asoc_qcom_lpass_platform_register(pdev);
 879         if (ret) {
 880                 dev_err(dev, "error registering platform driver: %d\n", ret);
 881                 goto err;
 882         }
 883
 884 err:
 885         return ret;
 886 }
 887 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_probe);
 888
 889 int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev)
 890 {
 891         struct lpass_data *drvdata = platform_get_drvdata(pdev);
 892
 893         if (drvdata->variant->exit)
 894                 drvdata->variant->exit(pdev);
 895
 896
 897         return 0;
 898 }
 899 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_remove);
 900
 901 void asoc_qcom_lpass_cpu_platform_shutdown(struct platform_device *pdev)
 902 {
 903         struct lpass_data *drvdata = platform_get_drvdata(pdev);
 904
 905         if (drvdata->variant->exit)
 906                 drvdata->variant->exit(pdev);
 907
 908 }
 909 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_shutdown);
 910
 911 MODULE_DESCRIPTION("QTi LPASS CPU Driver");
 912 MODULE_LICENSE("GPL v2");