1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
5 * lpass-cpu.c -- ALSA SoC CPU DAI driver for QTi LPASS
9 #include <linux/kernel.h>
10 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <sound/pcm.h>
15 #include <sound/pcm_params.h>
16 #include <linux/regmap.h>
17 #include <sound/soc.h>
18 #include <sound/soc-dai.h>
19 #include "lpass-lpaif-reg.h"
22 #define LPASS_CPU_MAX_MI2S_LINES 4
23 #define LPASS_CPU_I2S_SD0_MASK BIT(0)
24 #define LPASS_CPU_I2S_SD1_MASK BIT(1)
25 #define LPASS_CPU_I2S_SD2_MASK BIT(2)
26 #define LPASS_CPU_I2S_SD3_MASK BIT(3)
27 #define LPASS_CPU_I2S_SD0_1_MASK GENMASK(1, 0)
28 #define LPASS_CPU_I2S_SD2_3_MASK GENMASK(3, 2)
29 #define LPASS_CPU_I2S_SD0_1_2_MASK GENMASK(2, 0)
30 #define LPASS_CPU_I2S_SD0_1_2_3_MASK GENMASK(3, 0)
32 static int lpass_cpu_init_i2sctl_bitfields(struct device *dev,
33 struct lpaif_i2sctl *i2sctl, struct regmap *map)
35 struct lpass_data *drvdata = dev_get_drvdata(dev);
36 struct lpass_variant *v = drvdata->variant;
38 i2sctl->loopback = devm_regmap_field_alloc(dev, map, v->loopback);
39 i2sctl->spken = devm_regmap_field_alloc(dev, map, v->spken);
40 i2sctl->spkmode = devm_regmap_field_alloc(dev, map, v->spkmode);
41 i2sctl->spkmono = devm_regmap_field_alloc(dev, map, v->spkmono);
42 i2sctl->micen = devm_regmap_field_alloc(dev, map, v->micen);
43 i2sctl->micmode = devm_regmap_field_alloc(dev, map, v->micmode);
44 i2sctl->micmono = devm_regmap_field_alloc(dev, map, v->micmono);
45 i2sctl->wssrc = devm_regmap_field_alloc(dev, map, v->wssrc);
46 i2sctl->bitwidth = devm_regmap_field_alloc(dev, map, v->bitwidth);
48 if (IS_ERR(i2sctl->loopback) || IS_ERR(i2sctl->spken) ||
49 IS_ERR(i2sctl->spkmode) || IS_ERR(i2sctl->spkmono) ||
50 IS_ERR(i2sctl->micen) || IS_ERR(i2sctl->micmode) ||
51 IS_ERR(i2sctl->micmono) || IS_ERR(i2sctl->wssrc) ||
52 IS_ERR(i2sctl->bitwidth))
58 static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id,
59 unsigned int freq, int dir)
61 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
64 ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->driver->id], freq);
66 dev_err(dai->dev, "error setting mi2s osrclk to %u: %d\n",
72 static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream,
73 struct snd_soc_dai *dai)
75 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
78 ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->driver->id]);
80 dev_err(dai->dev, "error in enabling mi2s osr clk: %d\n", ret);
86 static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream,
87 struct snd_soc_dai *dai)
89 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
91 clk_disable_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]);
93 clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
96 static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream,
97 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
99 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
100 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
101 unsigned int id = dai->driver->id;
102 snd_pcm_format_t format = params_format(params);
103 unsigned int channels = params_channels(params);
104 unsigned int rate = params_rate(params);
109 bitwidth = snd_pcm_format_width(format);
111 dev_err(dai->dev, "invalid bit width given: %d\n", bitwidth);
115 ret = regmap_fields_write(i2sctl->loopback, id,
116 LPAIF_I2SCTL_LOOPBACK_DISABLE);
118 dev_err(dai->dev, "error updating loopback field: %d\n", ret);
122 ret = regmap_fields_write(i2sctl->wssrc, id,
123 LPAIF_I2SCTL_WSSRC_INTERNAL);
125 dev_err(dai->dev, "error updating wssrc field: %d\n", ret);
131 regval = LPAIF_I2SCTL_BITWIDTH_16;
134 regval = LPAIF_I2SCTL_BITWIDTH_24;
137 regval = LPAIF_I2SCTL_BITWIDTH_32;
140 dev_err(dai->dev, "invalid bitwidth given: %d\n", bitwidth);
144 ret = regmap_fields_write(i2sctl->bitwidth, id, regval);
146 dev_err(dai->dev, "error updating bitwidth field: %d\n", ret);
150 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
151 mode = drvdata->mi2s_playback_sd_mode[id];
153 mode = drvdata->mi2s_capture_sd_mode[id];
156 dev_err(dai->dev, "no line is assigned\n");
164 case LPAIF_I2SCTL_MODE_QUAD01:
165 case LPAIF_I2SCTL_MODE_6CH:
166 case LPAIF_I2SCTL_MODE_8CH:
167 mode = LPAIF_I2SCTL_MODE_SD0;
169 case LPAIF_I2SCTL_MODE_QUAD23:
170 mode = LPAIF_I2SCTL_MODE_SD2;
176 if (mode < LPAIF_I2SCTL_MODE_QUAD01) {
177 dev_err(dai->dev, "cannot configure 4 channels with mode %d\n",
183 case LPAIF_I2SCTL_MODE_6CH:
184 case LPAIF_I2SCTL_MODE_8CH:
185 mode = LPAIF_I2SCTL_MODE_QUAD01;
190 if (mode < LPAIF_I2SCTL_MODE_6CH) {
191 dev_err(dai->dev, "cannot configure 6 channels with mode %d\n",
197 case LPAIF_I2SCTL_MODE_8CH:
198 mode = LPAIF_I2SCTL_MODE_6CH;
203 if (mode < LPAIF_I2SCTL_MODE_8CH) {
204 dev_err(dai->dev, "cannot configure 8 channels with mode %d\n",
210 dev_err(dai->dev, "invalid channels given: %u\n", channels);
214 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
215 ret = regmap_fields_write(i2sctl->spkmode, id,
216 LPAIF_I2SCTL_SPKMODE(mode));
218 dev_err(dai->dev, "error writing to i2sctl spkr mode: %d\n",
223 ret = regmap_fields_write(i2sctl->spkmono, id,
224 LPAIF_I2SCTL_SPKMONO_STEREO);
226 ret = regmap_fields_write(i2sctl->spkmono, id,
227 LPAIF_I2SCTL_SPKMONO_MONO);
229 ret = regmap_fields_write(i2sctl->micmode, id,
230 LPAIF_I2SCTL_MICMODE(mode));
232 dev_err(dai->dev, "error writing to i2sctl mic mode: %d\n",
237 ret = regmap_fields_write(i2sctl->micmono, id,
238 LPAIF_I2SCTL_MICMONO_STEREO);
240 ret = regmap_fields_write(i2sctl->micmono, id,
241 LPAIF_I2SCTL_MICMONO_MONO);
245 dev_err(dai->dev, "error writing to i2sctl channels mode: %d\n",
250 ret = clk_set_rate(drvdata->mi2s_bit_clk[id],
251 rate * bitwidth * 2);
253 dev_err(dai->dev, "error setting mi2s bitclk to %u: %d\n",
254 rate * bitwidth * 2, ret);
261 static int lpass_cpu_daiops_prepare(struct snd_pcm_substream *substream,
262 struct snd_soc_dai *dai)
264 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
265 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
266 unsigned int id = dai->driver->id;
269 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
270 ret = regmap_fields_write(i2sctl->spken, id,
271 LPAIF_I2SCTL_SPKEN_ENABLE);
273 ret = regmap_fields_write(i2sctl->micen, id,
274 LPAIF_I2SCTL_MICEN_ENABLE);
278 dev_err(dai->dev, "error writing to i2sctl enable: %d\n", ret);
283 static int lpass_cpu_daiops_trigger(struct snd_pcm_substream *substream,
284 int cmd, struct snd_soc_dai *dai)
286 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
287 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
288 unsigned int id = dai->driver->id;
292 case SNDRV_PCM_TRIGGER_START:
293 case SNDRV_PCM_TRIGGER_RESUME:
294 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
295 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
296 ret = regmap_fields_write(i2sctl->spken, id,
297 LPAIF_I2SCTL_SPKEN_ENABLE);
299 ret = regmap_fields_write(i2sctl->micen, id,
300 LPAIF_I2SCTL_MICEN_ENABLE);
303 dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
306 ret = clk_prepare_enable(drvdata->mi2s_bit_clk[id]);
308 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
309 clk_disable_unprepare(drvdata->mi2s_osr_clk[id]);
314 case SNDRV_PCM_TRIGGER_STOP:
315 case SNDRV_PCM_TRIGGER_SUSPEND:
316 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
317 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
318 ret = regmap_fields_write(i2sctl->spken, id,
319 LPAIF_I2SCTL_SPKEN_DISABLE);
321 ret = regmap_fields_write(i2sctl->micen, id,
322 LPAIF_I2SCTL_MICEN_DISABLE);
325 dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
333 const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops = {
334 .set_sysclk = lpass_cpu_daiops_set_sysclk,
335 .startup = lpass_cpu_daiops_startup,
336 .shutdown = lpass_cpu_daiops_shutdown,
337 .hw_params = lpass_cpu_daiops_hw_params,
338 .prepare = lpass_cpu_daiops_prepare,
339 .trigger = lpass_cpu_daiops_trigger,
341 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_ops);
343 int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai)
345 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
348 /* ensure audio hardware is disabled */
349 ret = regmap_write(drvdata->lpaif_map,
350 LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id), 0);
352 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
356 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_probe);
358 static const struct snd_soc_component_driver lpass_cpu_comp_driver = {
362 static bool lpass_cpu_regmap_writeable(struct device *dev, unsigned int reg)
364 struct lpass_data *drvdata = dev_get_drvdata(dev);
365 struct lpass_variant *v = drvdata->variant;
368 for (i = 0; i < v->i2s_ports; ++i)
369 if (reg == LPAIF_I2SCTL_REG(v, i))
372 for (i = 0; i < v->irq_ports; ++i) {
373 if (reg == LPAIF_IRQEN_REG(v, i))
375 if (reg == LPAIF_IRQCLEAR_REG(v, i))
379 for (i = 0; i < v->rdma_channels; ++i) {
380 if (reg == LPAIF_RDMACTL_REG(v, i))
382 if (reg == LPAIF_RDMABASE_REG(v, i))
384 if (reg == LPAIF_RDMABUFF_REG(v, i))
386 if (reg == LPAIF_RDMAPER_REG(v, i))
390 for (i = 0; i < v->wrdma_channels; ++i) {
391 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
393 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
395 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
397 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
404 static bool lpass_cpu_regmap_readable(struct device *dev, unsigned int reg)
406 struct lpass_data *drvdata = dev_get_drvdata(dev);
407 struct lpass_variant *v = drvdata->variant;
410 for (i = 0; i < v->i2s_ports; ++i)
411 if (reg == LPAIF_I2SCTL_REG(v, i))
414 for (i = 0; i < v->irq_ports; ++i) {
415 if (reg == LPAIF_IRQEN_REG(v, i))
417 if (reg == LPAIF_IRQSTAT_REG(v, i))
421 for (i = 0; i < v->rdma_channels; ++i) {
422 if (reg == LPAIF_RDMACTL_REG(v, i))
424 if (reg == LPAIF_RDMABASE_REG(v, i))
426 if (reg == LPAIF_RDMABUFF_REG(v, i))
428 if (reg == LPAIF_RDMACURR_REG(v, i))
430 if (reg == LPAIF_RDMAPER_REG(v, i))
434 for (i = 0; i < v->wrdma_channels; ++i) {
435 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
437 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
439 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
441 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
443 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
450 static bool lpass_cpu_regmap_volatile(struct device *dev, unsigned int reg)
452 struct lpass_data *drvdata = dev_get_drvdata(dev);
453 struct lpass_variant *v = drvdata->variant;
456 for (i = 0; i < v->irq_ports; ++i)
457 if (reg == LPAIF_IRQSTAT_REG(v, i))
460 for (i = 0; i < v->rdma_channels; ++i)
461 if (reg == LPAIF_RDMACURR_REG(v, i))
464 for (i = 0; i < v->wrdma_channels; ++i)
465 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
471 static struct regmap_config lpass_cpu_regmap_config = {
475 .writeable_reg = lpass_cpu_regmap_writeable,
476 .readable_reg = lpass_cpu_regmap_readable,
477 .volatile_reg = lpass_cpu_regmap_volatile,
478 .cache_type = REGCACHE_FLAT,
481 static int lpass_hdmi_init_bitfields(struct device *dev, struct regmap *map)
483 struct lpass_data *drvdata = dev_get_drvdata(dev);
484 struct lpass_variant *v = drvdata->variant;
486 struct lpass_hdmi_tx_ctl *tx_ctl;
487 struct regmap_field *legacy_en;
488 struct lpass_vbit_ctrl *vbit_ctl;
489 struct regmap_field *tx_parity;
490 struct lpass_dp_metadata_ctl *meta_ctl;
491 struct lpass_sstream_ctl *sstream_ctl;
492 struct regmap_field *ch_msb;
493 struct regmap_field *ch_lsb;
494 struct lpass_hdmitx_dmactl *tx_dmactl;
497 tx_ctl = devm_kzalloc(dev, sizeof(*tx_ctl), GFP_KERNEL);
501 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->soft_reset, tx_ctl->soft_reset);
502 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->force_reset, tx_ctl->force_reset);
503 drvdata->tx_ctl = tx_ctl;
505 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->legacy_en, legacy_en);
506 drvdata->hdmitx_legacy_en = legacy_en;
508 vbit_ctl = devm_kzalloc(dev, sizeof(*vbit_ctl), GFP_KERNEL);
512 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->replace_vbit, vbit_ctl->replace_vbit);
513 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->vbit_stream, vbit_ctl->vbit_stream);
514 drvdata->vbit_ctl = vbit_ctl;
517 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->calc_en, tx_parity);
518 drvdata->hdmitx_parity_calc_en = tx_parity;
520 meta_ctl = devm_kzalloc(dev, sizeof(*meta_ctl), GFP_KERNEL);
524 rval = devm_regmap_field_bulk_alloc(dev, map, &meta_ctl->mute, &v->mute, 7);
527 drvdata->meta_ctl = meta_ctl;
529 sstream_ctl = devm_kzalloc(dev, sizeof(*sstream_ctl), GFP_KERNEL);
533 rval = devm_regmap_field_bulk_alloc(dev, map, &sstream_ctl->sstream_en, &v->sstream_en, 9);
537 drvdata->sstream_ctl = sstream_ctl;
539 for (i = 0; i < LPASS_MAX_HDMI_DMA_CHANNELS; i++) {
540 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->msb_bits, ch_msb);
541 drvdata->hdmitx_ch_msb[i] = ch_msb;
543 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->lsb_bits, ch_lsb);
544 drvdata->hdmitx_ch_lsb[i] = ch_lsb;
546 tx_dmactl = devm_kzalloc(dev, sizeof(*tx_dmactl), GFP_KERNEL);
550 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_chs, tx_dmactl->use_hw_chs);
551 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_usr, tx_dmactl->use_hw_usr);
552 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_chs_sel, tx_dmactl->hw_chs_sel);
553 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_usr_sel, tx_dmactl->hw_usr_sel);
554 drvdata->hdmi_tx_dmactl[i] = tx_dmactl;
559 static bool lpass_hdmi_regmap_writeable(struct device *dev, unsigned int reg)
561 struct lpass_data *drvdata = dev_get_drvdata(dev);
562 struct lpass_variant *v = drvdata->variant;
565 if (reg == LPASS_HDMI_TX_CTL_ADDR(v))
567 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
569 if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v))
571 if (reg == LPASS_HDMI_TX_PARITY_ADDR(v))
573 if (reg == LPASS_HDMI_TX_DP_ADDR(v))
575 if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v))
577 if (reg == LPASS_HDMITX_APP_IRQEN_REG(v))
579 if (reg == LPASS_HDMITX_APP_IRQCLEAR_REG(v))
582 for (i = 0; i < v->hdmi_rdma_channels; i++) {
583 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i))
585 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i))
587 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i))
591 for (i = 0; i < v->rdma_channels; ++i) {
592 if (reg == LPAIF_HDMI_RDMACTL_REG(v, i))
594 if (reg == LPAIF_HDMI_RDMABASE_REG(v, i))
596 if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i))
598 if (reg == LPAIF_HDMI_RDMAPER_REG(v, i))
604 static bool lpass_hdmi_regmap_readable(struct device *dev, unsigned int reg)
606 struct lpass_data *drvdata = dev_get_drvdata(dev);
607 struct lpass_variant *v = drvdata->variant;
610 if (reg == LPASS_HDMI_TX_CTL_ADDR(v))
612 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
614 if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v))
617 for (i = 0; i < v->hdmi_rdma_channels; i++) {
618 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i))
620 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i))
622 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i))
626 if (reg == LPASS_HDMI_TX_PARITY_ADDR(v))
628 if (reg == LPASS_HDMI_TX_DP_ADDR(v))
630 if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v))
632 if (reg == LPASS_HDMITX_APP_IRQEN_REG(v))
634 if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v))
637 for (i = 0; i < v->rdma_channels; ++i) {
638 if (reg == LPAIF_HDMI_RDMACTL_REG(v, i))
640 if (reg == LPAIF_HDMI_RDMABASE_REG(v, i))
642 if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i))
644 if (reg == LPAIF_HDMI_RDMAPER_REG(v, i))
646 if (reg == LPAIF_HDMI_RDMACURR_REG(v, i))
653 static bool lpass_hdmi_regmap_volatile(struct device *dev, unsigned int reg)
655 struct lpass_data *drvdata = dev_get_drvdata(dev);
656 struct lpass_variant *v = drvdata->variant;
659 if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v))
661 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
664 for (i = 0; i < v->rdma_channels; ++i) {
665 if (reg == LPAIF_HDMI_RDMACURR_REG(v, i))
671 static struct regmap_config lpass_hdmi_regmap_config = {
675 .writeable_reg = lpass_hdmi_regmap_writeable,
676 .readable_reg = lpass_hdmi_regmap_readable,
677 .volatile_reg = lpass_hdmi_regmap_volatile,
678 .cache_type = REGCACHE_FLAT,
681 static unsigned int of_lpass_cpu_parse_sd_lines(struct device *dev,
682 struct device_node *node,
685 unsigned int lines[LPASS_CPU_MAX_MI2S_LINES];
686 unsigned int sd_line_mask = 0;
689 num_lines = of_property_read_variable_u32_array(node, name, lines, 0,
690 LPASS_CPU_MAX_MI2S_LINES);
692 return LPAIF_I2SCTL_MODE_NONE;
694 for (i = 0; i < num_lines; i++)
695 sd_line_mask |= BIT(lines[i]);
697 switch (sd_line_mask) {
698 case LPASS_CPU_I2S_SD0_MASK:
699 return LPAIF_I2SCTL_MODE_SD0;
700 case LPASS_CPU_I2S_SD1_MASK:
701 return LPAIF_I2SCTL_MODE_SD1;
702 case LPASS_CPU_I2S_SD2_MASK:
703 return LPAIF_I2SCTL_MODE_SD2;
704 case LPASS_CPU_I2S_SD3_MASK:
705 return LPAIF_I2SCTL_MODE_SD3;
706 case LPASS_CPU_I2S_SD0_1_MASK:
707 return LPAIF_I2SCTL_MODE_QUAD01;
708 case LPASS_CPU_I2S_SD2_3_MASK:
709 return LPAIF_I2SCTL_MODE_QUAD23;
710 case LPASS_CPU_I2S_SD0_1_2_MASK:
711 return LPAIF_I2SCTL_MODE_6CH;
712 case LPASS_CPU_I2S_SD0_1_2_3_MASK:
713 return LPAIF_I2SCTL_MODE_8CH;
715 dev_err(dev, "Unsupported SD line mask: %#x\n", sd_line_mask);
716 return LPAIF_I2SCTL_MODE_NONE;
720 static void of_lpass_cpu_parse_dai_data(struct device *dev,
721 struct lpass_data *data)
723 struct device_node *node;
726 /* Allow all channels by default for backwards compatibility */
727 for (id = 0; id < data->variant->num_dai; id++) {
728 data->mi2s_playback_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH;
729 data->mi2s_capture_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH;
732 for_each_child_of_node(dev->of_node, node) {
733 ret = of_property_read_u32(node, "reg", &id);
734 if (ret || id < 0 || id >= data->variant->num_dai) {
735 dev_err(dev, "valid dai id not found: %d\n", ret);
738 if (id == LPASS_DP_RX) {
739 data->hdmi_port_enable = 1;
740 dev_err(dev, "HDMI Port is enabled: %d\n", id);
742 data->mi2s_playback_sd_mode[id] =
743 of_lpass_cpu_parse_sd_lines(dev, node,
744 "qcom,playback-sd-lines");
745 data->mi2s_capture_sd_mode[id] =
746 of_lpass_cpu_parse_sd_lines(dev, node,
747 "qcom,capture-sd-lines");
752 int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev)
754 struct lpass_data *drvdata;
755 struct device_node *dsp_of_node;
756 struct resource *res;
757 struct lpass_variant *variant;
758 struct device *dev = &pdev->dev;
759 const struct of_device_id *match;
762 dsp_of_node = of_parse_phandle(pdev->dev.of_node, "qcom,adsp", 0);
764 dev_err(dev, "DSP exists and holds audio resources\n");
768 drvdata = devm_kzalloc(dev, sizeof(struct lpass_data), GFP_KERNEL);
771 platform_set_drvdata(pdev, drvdata);
773 match = of_match_device(dev->driver->of_match_table, dev);
774 if (!match || !match->data)
777 drvdata->variant = (struct lpass_variant *)match->data;
778 variant = drvdata->variant;
780 of_lpass_cpu_parse_dai_data(dev, drvdata);
782 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-lpaif");
784 drvdata->lpaif = devm_ioremap_resource(dev, res);
785 if (IS_ERR((void const __force *)drvdata->lpaif)) {
786 dev_err(dev, "error mapping reg resource: %ld\n",
787 PTR_ERR((void const __force *)drvdata->lpaif));
788 return PTR_ERR((void const __force *)drvdata->lpaif);
791 lpass_cpu_regmap_config.max_register = LPAIF_WRDMAPER_REG(variant,
792 variant->wrdma_channels +
793 variant->wrdma_channel_start);
795 drvdata->lpaif_map = devm_regmap_init_mmio(dev, drvdata->lpaif,
796 &lpass_cpu_regmap_config);
797 if (IS_ERR(drvdata->lpaif_map)) {
798 dev_err(dev, "error initializing regmap: %ld\n",
799 PTR_ERR(drvdata->lpaif_map));
800 return PTR_ERR(drvdata->lpaif_map);
803 if (drvdata->hdmi_port_enable) {
804 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-hdmiif");
806 drvdata->hdmiif = devm_ioremap_resource(dev, res);
807 if (IS_ERR((void const __force *)drvdata->hdmiif)) {
808 dev_err(dev, "error mapping reg resource: %ld\n",
809 PTR_ERR((void const __force *)drvdata->hdmiif));
810 return PTR_ERR((void const __force *)drvdata->hdmiif);
813 lpass_hdmi_regmap_config.max_register = LPAIF_HDMI_RDMAPER_REG(variant,
814 variant->hdmi_rdma_channels);
815 drvdata->hdmiif_map = devm_regmap_init_mmio(dev, drvdata->hdmiif,
816 &lpass_hdmi_regmap_config);
817 if (IS_ERR(drvdata->hdmiif_map)) {
818 dev_err(dev, "error initializing regmap: %ld\n",
819 PTR_ERR(drvdata->hdmiif_map));
820 return PTR_ERR(drvdata->hdmiif_map);
825 ret = variant->init(pdev);
827 dev_err(dev, "error initializing variant: %d\n", ret);
832 for (i = 0; i < variant->num_dai; i++) {
833 dai_id = variant->dai_driver[i].id;
834 if (dai_id == LPASS_DP_RX)
837 drvdata->mi2s_osr_clk[dai_id] = devm_clk_get(dev,
838 variant->dai_osr_clk_names[i]);
839 if (IS_ERR(drvdata->mi2s_osr_clk[dai_id])) {
841 "%s() error getting optional %s: %ld\n",
843 variant->dai_osr_clk_names[i],
844 PTR_ERR(drvdata->mi2s_osr_clk[dai_id]));
846 drvdata->mi2s_osr_clk[dai_id] = NULL;
849 drvdata->mi2s_bit_clk[dai_id] = devm_clk_get(dev,
850 variant->dai_bit_clk_names[i]);
851 if (IS_ERR(drvdata->mi2s_bit_clk[dai_id])) {
853 "error getting %s: %ld\n",
854 variant->dai_bit_clk_names[i],
855 PTR_ERR(drvdata->mi2s_bit_clk[dai_id]));
856 return PTR_ERR(drvdata->mi2s_bit_clk[dai_id]);
860 /* Allocation for i2sctl regmap fields */
861 drvdata->i2sctl = devm_kzalloc(&pdev->dev, sizeof(struct lpaif_i2sctl),
864 /* Initialize bitfields for dai I2SCTL register */
865 ret = lpass_cpu_init_i2sctl_bitfields(dev, drvdata->i2sctl,
868 dev_err(dev, "error init i2sctl field: %d\n", ret);
872 if (drvdata->hdmi_port_enable) {
873 ret = lpass_hdmi_init_bitfields(dev, drvdata->hdmiif_map);
875 dev_err(dev, "%s error hdmi init failed\n", __func__);
879 ret = devm_snd_soc_register_component(dev,
880 &lpass_cpu_comp_driver,
884 dev_err(dev, "error registering cpu driver: %d\n", ret);
888 ret = asoc_qcom_lpass_platform_register(pdev);
890 dev_err(dev, "error registering platform driver: %d\n", ret);
897 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_probe);
899 int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev)
901 struct lpass_data *drvdata = platform_get_drvdata(pdev);
903 if (drvdata->variant->exit)
904 drvdata->variant->exit(pdev);
909 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_remove);
911 MODULE_DESCRIPTION("QTi LPASS CPU Driver");
912 MODULE_LICENSE("GPL v2");