1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * pxa-ssp.c -- ALSA Soc Audio Layer
5 * Copyright 2005,2008 Wolfson Microelectronics PLC.
6 * Author: Liam Girdwood
7 * Mark Brown <broonie@opensource.wolfsonmicro.com>
10 * o Test network mode for > 16bit sample size
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/platform_device.h>
17 #include <linux/clk.h>
19 #include <linux/pxa2xx_ssp.h>
21 #include <linux/dmaengine.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/initval.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/pxa2xx-lib.h>
31 #include <sound/dmaengine_pcm.h>
36 * SSP audio private data
39 struct ssp_device *ssp;
41 unsigned long ssp_clk;
44 unsigned int configured_dai_fmt;
53 static void dump_registers(struct ssp_device *ssp)
55 dev_dbg(ssp->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
56 pxa_ssp_read_reg(ssp, SSCR0), pxa_ssp_read_reg(ssp, SSCR1),
57 pxa_ssp_read_reg(ssp, SSTO));
59 dev_dbg(ssp->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
60 pxa_ssp_read_reg(ssp, SSPSP), pxa_ssp_read_reg(ssp, SSSR),
61 pxa_ssp_read_reg(ssp, SSACD));
64 static void pxa_ssp_enable(struct ssp_device *ssp)
68 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) | SSCR0_SSE;
69 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
72 static void pxa_ssp_disable(struct ssp_device *ssp)
76 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) & ~SSCR0_SSE;
77 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
80 static void pxa_ssp_set_dma_params(struct ssp_device *ssp, int width4,
81 int out, struct snd_dmaengine_dai_dma_data *dma)
83 dma->addr_width = width4 ? DMA_SLAVE_BUSWIDTH_4_BYTES :
84 DMA_SLAVE_BUSWIDTH_2_BYTES;
86 dma->addr = ssp->phys_base + SSDR;
89 static int pxa_ssp_startup(struct snd_pcm_substream *substream,
90 struct snd_soc_dai *cpu_dai)
92 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
93 struct ssp_device *ssp = priv->ssp;
94 struct snd_dmaengine_dai_dma_data *dma;
97 if (!cpu_dai->active) {
98 clk_prepare_enable(ssp->clk);
103 clk_prepare_enable(priv->extclk);
105 dma = kzalloc(sizeof(struct snd_dmaengine_dai_dma_data), GFP_KERNEL);
108 dma->chan_name = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
111 snd_soc_dai_set_dma_data(cpu_dai, substream, dma);
116 static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
117 struct snd_soc_dai *cpu_dai)
119 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
120 struct ssp_device *ssp = priv->ssp;
122 if (!cpu_dai->active) {
123 pxa_ssp_disable(ssp);
124 clk_disable_unprepare(ssp->clk);
128 clk_disable_unprepare(priv->extclk);
130 kfree(snd_soc_dai_get_dma_data(cpu_dai, substream));
131 snd_soc_dai_set_dma_data(cpu_dai, substream, NULL);
136 static int pxa_ssp_suspend(struct snd_soc_component *component)
138 struct ssp_priv *priv = snd_soc_component_get_drvdata(component);
139 struct ssp_device *ssp = priv->ssp;
141 if (!component->active)
142 clk_prepare_enable(ssp->clk);
144 priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
145 priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
146 priv->to = __raw_readl(ssp->mmio_base + SSTO);
147 priv->psp = __raw_readl(ssp->mmio_base + SSPSP);
149 pxa_ssp_disable(ssp);
150 clk_disable_unprepare(ssp->clk);
154 static int pxa_ssp_resume(struct snd_soc_component *component)
156 struct ssp_priv *priv = snd_soc_component_get_drvdata(component);
157 struct ssp_device *ssp = priv->ssp;
158 uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
160 clk_prepare_enable(ssp->clk);
162 __raw_writel(sssr, ssp->mmio_base + SSSR);
163 __raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
164 __raw_writel(priv->cr1, ssp->mmio_base + SSCR1);
165 __raw_writel(priv->to, ssp->mmio_base + SSTO);
166 __raw_writel(priv->psp, ssp->mmio_base + SSPSP);
168 if (component->active)
171 clk_disable_unprepare(ssp->clk);
177 #define pxa_ssp_suspend NULL
178 #define pxa_ssp_resume NULL
182 * ssp_set_clkdiv - set SSP clock divider
183 * @div: serial clock rate divider
185 static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div)
187 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
189 if (ssp->type == PXA25x_SSP) {
190 sscr0 &= ~0x0000ff00;
191 sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
193 sscr0 &= ~0x000fff00;
194 sscr0 |= (div - 1) << 8; /* 1..4096 */
196 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
200 * Set the SSP ports SYSCLK.
202 static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
203 int clk_id, unsigned int freq, int dir)
205 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
206 struct ssp_device *ssp = priv->ssp;
208 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
209 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
215 * For DT based boards, if an extclk is given, use it
216 * here and configure PXA_SSP_CLK_EXT.
219 ret = clk_set_rate(priv->extclk, freq);
223 clk_id = PXA_SSP_CLK_EXT;
227 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n",
228 cpu_dai->id, clk_id, freq);
231 case PXA_SSP_CLK_NET_PLL:
234 case PXA_SSP_CLK_PLL:
235 /* Internal PLL is fixed */
236 if (ssp->type == PXA25x_SSP)
237 priv->sysclk = 1843200;
239 priv->sysclk = 13000000;
241 case PXA_SSP_CLK_EXT:
245 case PXA_SSP_CLK_NET:
247 sscr0 |= SSCR0_NCS | SSCR0_MOD;
249 case PXA_SSP_CLK_AUDIO:
251 pxa_ssp_set_scr(ssp, 1);
258 /* The SSP clock must be disabled when changing SSP clock mode
259 * on PXA2xx. On PXA3xx it must be enabled when doing so. */
260 if (ssp->type != PXA3xx_SSP)
261 clk_disable_unprepare(ssp->clk);
262 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
263 if (ssp->type != PXA3xx_SSP)
264 clk_prepare_enable(ssp->clk);
270 * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
272 static int pxa_ssp_set_pll(struct ssp_priv *priv, unsigned int freq)
274 struct ssp_device *ssp = priv->ssp;
275 u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70;
277 if (ssp->type == PXA3xx_SSP)
278 pxa_ssp_write_reg(ssp, SSACDD, 0);
303 /* PXA3xx has a clock ditherer which can be used to generate
304 * a wider range of frequencies - calculate a value for it.
306 if (ssp->type == PXA3xx_SSP) {
314 val = (val << 16) | 64;
315 pxa_ssp_write_reg(ssp, SSACDD, val);
320 "Using SSACDD %x to supply %uHz\n",
328 pxa_ssp_write_reg(ssp, SSACD, ssacd);
334 * Set the active slots in TDM/Network mode
336 static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
337 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
339 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
340 struct ssp_device *ssp = priv->ssp;
343 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
344 sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS);
348 sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16);
350 sscr0 |= SSCR0_DataSize(slot_width);
353 /* enable network mode */
356 /* set number of active slots */
357 sscr0 |= SSCR0_SlotsPerFrm(slots);
359 /* set active slot mask */
360 pxa_ssp_write_reg(ssp, SSTSA, tx_mask);
361 pxa_ssp_write_reg(ssp, SSRSA, rx_mask);
363 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
369 * Tristate the SSP DAI lines
371 static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
374 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
375 struct ssp_device *ssp = priv->ssp;
378 sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
383 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
388 static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
391 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
393 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
394 case SND_SOC_DAIFMT_CBM_CFM:
395 case SND_SOC_DAIFMT_CBM_CFS:
396 case SND_SOC_DAIFMT_CBS_CFS:
402 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
403 case SND_SOC_DAIFMT_NB_NF:
404 case SND_SOC_DAIFMT_NB_IF:
405 case SND_SOC_DAIFMT_IB_IF:
406 case SND_SOC_DAIFMT_IB_NF:
412 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
413 case SND_SOC_DAIFMT_I2S:
414 case SND_SOC_DAIFMT_DSP_A:
415 case SND_SOC_DAIFMT_DSP_B:
422 /* Settings will be applied in hw_params() */
429 * Set up the SSP DAI format.
430 * The SSP Port must be inactive before calling this function as the
431 * physical interface format is changed.
433 static int pxa_ssp_configure_dai_fmt(struct ssp_priv *priv)
435 struct ssp_device *ssp = priv->ssp;
436 u32 sscr0, sscr1, sspsp, scfr;
438 /* check if we need to change anything at all */
439 if (priv->configured_dai_fmt == priv->dai_fmt)
442 /* reset port settings */
443 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
444 ~(SSCR0_PSP | SSCR0_MOD);
445 sscr1 = pxa_ssp_read_reg(ssp, SSCR1) &
446 ~(SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR |
447 SSCR1_RWOT | SSCR1_TRAIL | SSCR1_TFT | SSCR1_RFT);
448 sspsp = pxa_ssp_read_reg(ssp, SSPSP) &
449 ~(SSPSP_SFRMP | SSPSP_SCMODE(3));
451 sscr1 |= SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
453 switch (priv->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) {
454 case SND_SOC_DAIFMT_CBM_CFM:
455 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR;
457 case SND_SOC_DAIFMT_CBM_CFS:
458 sscr1 |= SSCR1_SCLKDIR | SSCR1_SCFR;
460 case SND_SOC_DAIFMT_CBS_CFS:
466 switch (priv->dai_fmt & SND_SOC_DAIFMT_INV_MASK) {
467 case SND_SOC_DAIFMT_NB_NF:
468 sspsp |= SSPSP_SFRMP;
470 case SND_SOC_DAIFMT_NB_IF:
472 case SND_SOC_DAIFMT_IB_IF:
473 sspsp |= SSPSP_SCMODE(2);
475 case SND_SOC_DAIFMT_IB_NF:
476 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
482 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
483 case SND_SOC_DAIFMT_I2S:
485 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
486 /* See hw_params() */
489 case SND_SOC_DAIFMT_DSP_A:
492 case SND_SOC_DAIFMT_DSP_B:
493 sscr0 |= SSCR0_MOD | SSCR0_PSP;
494 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
501 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
502 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
503 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
505 switch (priv->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) {
506 case SND_SOC_DAIFMT_CBM_CFM:
507 case SND_SOC_DAIFMT_CBM_CFS:
508 scfr = pxa_ssp_read_reg(ssp, SSCR1) | SSCR1_SCFR;
509 pxa_ssp_write_reg(ssp, SSCR1, scfr);
511 while (pxa_ssp_read_reg(ssp, SSSR) & SSSR_BSY)
518 /* Since we are configuring the timings for the format by hand
519 * we have to defer some things until hw_params() where we
520 * know parameters like the sample size.
522 priv->configured_dai_fmt = priv->dai_fmt;
527 struct pxa_ssp_clock_mode {
534 static const struct pxa_ssp_clock_mode pxa_ssp_clock_modes[] = {
535 { .rate = 8000, .pll = 32842000, .acds = SSACD_ACDS_32, .scdb = SSACD_SCDB_4X },
536 { .rate = 11025, .pll = 5622000, .acds = SSACD_ACDS_4, .scdb = SSACD_SCDB_4X },
537 { .rate = 16000, .pll = 32842000, .acds = SSACD_ACDS_16, .scdb = SSACD_SCDB_4X },
538 { .rate = 22050, .pll = 5622000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X },
539 { .rate = 44100, .pll = 11345000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X },
540 { .rate = 48000, .pll = 12235000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X },
541 { .rate = 96000, .pll = 12235000, .acds = SSACD_ACDS_4, .scdb = SSACD_SCDB_1X },
546 * Set the SSP audio DMA parameters and sample size.
547 * Can be called multiple times by oss emulation.
549 static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
550 struct snd_pcm_hw_params *params,
551 struct snd_soc_dai *cpu_dai)
553 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
554 struct ssp_device *ssp = priv->ssp;
555 int chn = params_channels(params);
557 int width = snd_pcm_format_physical_width(params_format(params));
558 int ttsa = pxa_ssp_read_reg(ssp, SSTSA) & 0xf;
559 struct snd_dmaengine_dai_dma_data *dma_data;
560 int rate = params_rate(params);
561 int bclk = rate * chn * (width / 8);
564 dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
566 /* Network mode with one active slot (ttsa == 1) can be used
567 * to force 16-bit frame width on the wire (for S16_LE), even
568 * with two channels. Use 16-bit DMA transfers for this case.
570 pxa_ssp_set_dma_params(ssp,
571 ((chn == 2) && (ttsa != 1)) || (width == 32),
572 substream->stream == SNDRV_PCM_STREAM_PLAYBACK, dma_data);
574 /* we can only change the settings if the port is not in use */
575 if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
578 ret = pxa_ssp_configure_dai_fmt(priv);
582 /* clear selected SSP bits */
583 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
586 switch (params_format(params)) {
587 case SNDRV_PCM_FORMAT_S16_LE:
588 if (ssp->type == PXA3xx_SSP)
589 sscr0 |= SSCR0_FPCKE;
590 sscr0 |= SSCR0_DataSize(16);
592 case SNDRV_PCM_FORMAT_S24_LE:
593 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
595 case SNDRV_PCM_FORMAT_S32_LE:
596 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
599 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
601 if (sscr0 & SSCR0_ACS) {
602 ret = pxa_ssp_set_pll(priv, bclk);
605 * If we were able to generate the bclk directly,
606 * all is fine. Otherwise, look up the closest rate
607 * from the table and also set the dividers.
611 const struct pxa_ssp_clock_mode *m;
614 for (m = pxa_ssp_clock_modes; m->rate; m++) {
624 /* The values in the table are for 16 bits */
628 ret = pxa_ssp_set_pll(priv, bclk);
632 ssacd = pxa_ssp_read_reg(ssp, SSACD);
633 ssacd &= ~(SSACD_ACDS(7) | SSACD_SCDB_1X);
634 ssacd |= SSACD_ACDS(m->acds);
636 pxa_ssp_write_reg(ssp, SSACD, ssacd);
638 } else if (sscr0 & SSCR0_ECS) {
640 * For setups with external clocking, the PLL and its diviers
641 * are not active. Instead, the SCR bits in SSCR0 can be used
642 * to divide the clock.
644 pxa_ssp_set_scr(ssp, bclk / rate);
647 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
648 case SND_SOC_DAIFMT_I2S:
649 sspsp = pxa_ssp_read_reg(ssp, SSPSP);
651 if (((priv->sysclk / bclk) == 64) && (width == 16)) {
652 /* This is a special case where the bitclk is 64fs
653 * and we're not dealing with 2*32 bits of audio
656 * The SSP values used for that are all found out by
657 * trying and failing a lot; some of the registers
658 * needed for that mode are only available on PXA3xx.
660 if (ssp->type != PXA3xx_SSP)
663 sspsp |= SSPSP_SFRMWDTH(width * 2);
664 sspsp |= SSPSP_SFRMDLY(width * 4);
665 sspsp |= SSPSP_EDMYSTOP(3);
666 sspsp |= SSPSP_DMYSTOP(3);
667 sspsp |= SSPSP_DMYSTRT(1);
669 /* The frame width is the width the LRCLK is
670 * asserted for; the delay is expressed in
671 * half cycle units. We need the extra cycle
672 * because the data starts clocking out one BCLK
673 * after LRCLK changes polarity.
675 sspsp |= SSPSP_SFRMWDTH(width + 1);
676 sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
677 sspsp |= SSPSP_DMYSTRT(1);
680 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
686 /* When we use a network mode, we always require TDM slots
687 * - complain loudly and fail if they've not been set up yet.
689 if ((sscr0 & SSCR0_MOD) && !ttsa) {
690 dev_err(ssp->dev, "No TDM timeslot configured\n");
699 static void pxa_ssp_set_running_bit(struct snd_pcm_substream *substream,
700 struct ssp_device *ssp, int value)
702 uint32_t sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
703 uint32_t sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
704 uint32_t sspsp = pxa_ssp_read_reg(ssp, SSPSP);
705 uint32_t sssr = pxa_ssp_read_reg(ssp, SSSR);
707 if (value && (sscr0 & SSCR0_SSE))
708 pxa_ssp_write_reg(ssp, SSCR0, sscr0 & ~SSCR0_SSE);
710 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
714 sscr1 &= ~SSCR1_TSRE;
719 sscr1 &= ~SSCR1_RSRE;
722 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
725 pxa_ssp_write_reg(ssp, SSSR, sssr);
726 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
727 pxa_ssp_write_reg(ssp, SSCR0, sscr0 | SSCR0_SSE);
731 static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
732 struct snd_soc_dai *cpu_dai)
735 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
736 struct ssp_device *ssp = priv->ssp;
740 case SNDRV_PCM_TRIGGER_RESUME:
743 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
744 pxa_ssp_set_running_bit(substream, ssp, 1);
745 val = pxa_ssp_read_reg(ssp, SSSR);
746 pxa_ssp_write_reg(ssp, SSSR, val);
748 case SNDRV_PCM_TRIGGER_START:
749 pxa_ssp_set_running_bit(substream, ssp, 1);
751 case SNDRV_PCM_TRIGGER_STOP:
752 pxa_ssp_set_running_bit(substream, ssp, 0);
754 case SNDRV_PCM_TRIGGER_SUSPEND:
755 pxa_ssp_disable(ssp);
757 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
758 pxa_ssp_set_running_bit(substream, ssp, 0);
770 static int pxa_ssp_probe(struct snd_soc_dai *dai)
772 struct device *dev = dai->dev;
773 struct ssp_priv *priv;
776 priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
781 struct device_node *ssp_handle;
783 ssp_handle = of_parse_phandle(dev->of_node, "port", 0);
785 dev_err(dev, "unable to get 'port' phandle\n");
790 priv->ssp = pxa_ssp_request_of(ssp_handle, "SoC audio");
791 if (priv->ssp == NULL) {
796 priv->extclk = devm_clk_get(dev, "extclk");
797 if (IS_ERR(priv->extclk)) {
798 ret = PTR_ERR(priv->extclk);
799 if (ret == -EPROBE_DEFER)
805 priv->ssp = pxa_ssp_request(dai->id + 1, "SoC audio");
806 if (priv->ssp == NULL) {
812 priv->dai_fmt = (unsigned int) -1;
813 snd_soc_dai_set_drvdata(dai, priv);
822 static int pxa_ssp_remove(struct snd_soc_dai *dai)
824 struct ssp_priv *priv = snd_soc_dai_get_drvdata(dai);
826 pxa_ssp_free(priv->ssp);
831 #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
832 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
833 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
834 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
835 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
837 #define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
839 static const struct snd_soc_dai_ops pxa_ssp_dai_ops = {
840 .startup = pxa_ssp_startup,
841 .shutdown = pxa_ssp_shutdown,
842 .trigger = pxa_ssp_trigger,
843 .hw_params = pxa_ssp_hw_params,
844 .set_sysclk = pxa_ssp_set_dai_sysclk,
845 .set_fmt = pxa_ssp_set_dai_fmt,
846 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
847 .set_tristate = pxa_ssp_set_dai_tristate,
850 static struct snd_soc_dai_driver pxa_ssp_dai = {
851 .probe = pxa_ssp_probe,
852 .remove = pxa_ssp_remove,
856 .rates = PXA_SSP_RATES,
857 .formats = PXA_SSP_FORMATS,
862 .rates = PXA_SSP_RATES,
863 .formats = PXA_SSP_FORMATS,
865 .ops = &pxa_ssp_dai_ops,
868 static const struct snd_soc_component_driver pxa_ssp_component = {
870 .pcm_construct = pxa2xx_soc_pcm_new,
871 .pcm_destruct = pxa2xx_soc_pcm_free,
872 .open = pxa2xx_soc_pcm_open,
873 .close = pxa2xx_soc_pcm_close,
874 .hw_params = pxa2xx_soc_pcm_hw_params,
875 .hw_free = pxa2xx_soc_pcm_hw_free,
876 .prepare = pxa2xx_soc_pcm_prepare,
877 .trigger = pxa2xx_soc_pcm_trigger,
878 .pointer = pxa2xx_soc_pcm_pointer,
879 .mmap = pxa2xx_soc_pcm_mmap,
880 .suspend = pxa_ssp_suspend,
881 .resume = pxa_ssp_resume,
885 static const struct of_device_id pxa_ssp_of_ids[] = {
886 { .compatible = "mrvl,pxa-ssp-dai" },
889 MODULE_DEVICE_TABLE(of, pxa_ssp_of_ids);
892 static int asoc_ssp_probe(struct platform_device *pdev)
894 return devm_snd_soc_register_component(&pdev->dev, &pxa_ssp_component,
898 static struct platform_driver asoc_ssp_driver = {
900 .name = "pxa-ssp-dai",
901 .of_match_table = of_match_ptr(pxa_ssp_of_ids),
904 .probe = asoc_ssp_probe,
907 module_platform_driver(asoc_ssp_driver);
909 /* Module information */
910 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
911 MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
912 MODULE_LICENSE("GPL");
913 MODULE_ALIAS("platform:pxa-ssp-dai");