1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Copyright (c) 2018 BayLibre, SAS.
4 // Author: Jerome Brunet <jbrunet@baylibre.com>
7 #include <linux/module.h>
8 #include <linux/of_platform.h>
9 #include <sound/pcm_params.h>
10 #include <sound/soc.h>
11 #include <sound/soc-dai.h>
20 static unsigned int axg_tdm_slots_total(u32 *mask)
22 unsigned int slots = 0;
28 /* Count the total number of slots provided by all 4 lanes */
29 for (i = 0; i < AXG_TDM_NUM_LANES; i++)
30 slots += hweight32(mask[i]);
35 int axg_tdm_set_tdm_slots(struct snd_soc_dai *dai, u32 *tx_mask,
36 u32 *rx_mask, unsigned int slots,
37 unsigned int slot_width)
39 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
40 struct axg_tdm_stream *tx = (struct axg_tdm_stream *)
41 dai->playback_dma_data;
42 struct axg_tdm_stream *rx = (struct axg_tdm_stream *)
43 dai->capture_dma_data;
44 unsigned int tx_slots, rx_slots;
47 tx_slots = axg_tdm_slots_total(tx_mask);
48 rx_slots = axg_tdm_slots_total(rx_mask);
50 /* We should at least have a slot for a valid interface */
51 if (!tx_slots && !rx_slots) {
52 dev_err(dai->dev, "interface has no slot\n");
63 fmt |= SNDRV_PCM_FMTBIT_S32_LE;
66 fmt |= SNDRV_PCM_FMTBIT_S24_LE;
67 fmt |= SNDRV_PCM_FMTBIT_S20_LE;
70 fmt |= SNDRV_PCM_FMTBIT_S16_LE;
73 fmt |= SNDRV_PCM_FMTBIT_S8;
76 dev_err(dai->dev, "unsupported slot width: %d\n", slot_width);
80 iface->slot_width = slot_width;
82 /* Amend the dai driver and let dpcm merge do its job */
85 dai->driver->playback.channels_max = tx_slots;
86 dai->driver->playback.formats = fmt;
91 dai->driver->capture.channels_max = rx_slots;
92 dai->driver->capture.formats = fmt;
97 EXPORT_SYMBOL_GPL(axg_tdm_set_tdm_slots);
99 static int axg_tdm_iface_set_sysclk(struct snd_soc_dai *dai, int clk_id,
100 unsigned int freq, int dir)
102 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
105 if (dir == SND_SOC_CLOCK_OUT && clk_id == 0) {
107 dev_warn(dai->dev, "master clock not provided\n");
109 ret = clk_set_rate(iface->mclk, freq);
111 iface->mclk_rate = freq;
118 static int axg_tdm_iface_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
120 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
122 /* These modes are not supported */
123 if (fmt & (SND_SOC_DAIFMT_CBS_CFM | SND_SOC_DAIFMT_CBM_CFS)) {
124 dev_err(dai->dev, "only CBS_CFS and CBM_CFM are supported\n");
128 /* If the TDM interface is the clock master, it requires mclk */
129 if (!iface->mclk && (fmt & SND_SOC_DAIFMT_CBS_CFS)) {
130 dev_err(dai->dev, "cpu clock master: mclk missing\n");
138 static int axg_tdm_iface_startup(struct snd_pcm_substream *substream,
139 struct snd_soc_dai *dai)
141 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
142 struct axg_tdm_stream *ts =
143 snd_soc_dai_get_dma_data(dai, substream);
146 if (!axg_tdm_slots_total(ts->mask)) {
147 dev_err(dai->dev, "interface has not slots\n");
151 /* Apply component wide rate symmetry */
152 if (dai->component->active) {
153 ret = snd_pcm_hw_constraint_single(substream->runtime,
154 SNDRV_PCM_HW_PARAM_RATE,
158 "can't set iface rate constraint\n");
166 static int axg_tdm_iface_set_stream(struct snd_pcm_substream *substream,
167 struct snd_pcm_hw_params *params,
168 struct snd_soc_dai *dai)
170 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
171 struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
172 unsigned int channels = params_channels(params);
173 unsigned int width = params_width(params);
175 /* Save rate and sample_bits for component symmetry */
176 iface->rate = params_rate(params);
178 /* Make sure this interface can cope with the stream */
179 if (axg_tdm_slots_total(ts->mask) < channels) {
180 dev_err(dai->dev, "not enough slots for channels\n");
184 if (iface->slot_width < width) {
185 dev_err(dai->dev, "incompatible slots width for stream\n");
189 /* Save the parameter for tdmout/tdmin widgets */
190 ts->physical_width = params_physical_width(params);
191 ts->width = params_width(params);
192 ts->channels = params_channels(params);
197 static int axg_tdm_iface_set_lrclk(struct snd_soc_dai *dai,
198 struct snd_pcm_hw_params *params)
200 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
201 unsigned int ratio_num;
204 ret = clk_set_rate(iface->lrclk, params_rate(params));
206 dev_err(dai->dev, "setting sample clock failed: %d\n", ret);
210 switch (iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
211 case SND_SOC_DAIFMT_I2S:
212 case SND_SOC_DAIFMT_LEFT_J:
213 case SND_SOC_DAIFMT_RIGHT_J:
214 /* 50% duty cycle ratio */
218 case SND_SOC_DAIFMT_DSP_A:
219 case SND_SOC_DAIFMT_DSP_B:
221 * A zero duty cycle ratio will result in setting the mininum
222 * ratio possible which, for this clock, is 1 cycle of the
223 * parent bclk clock high and the rest low, This is exactly
233 ret = clk_set_duty_cycle(iface->lrclk, ratio_num, 2);
236 "setting sample clock duty cycle failed: %d\n", ret);
240 /* Set sample clock inversion */
241 ret = clk_set_phase(iface->lrclk,
242 axg_tdm_lrclk_invert(iface->fmt) ? 180 : 0);
245 "setting sample clock phase failed: %d\n", ret);
252 static int axg_tdm_iface_set_sclk(struct snd_soc_dai *dai,
253 struct snd_pcm_hw_params *params)
255 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
259 srate = iface->slots * iface->slot_width * params_rate(params);
261 if (!iface->mclk_rate) {
262 /* If no specific mclk is requested, default to bit clock * 4 */
263 clk_set_rate(iface->mclk, 4 * srate);
265 /* Check if we can actually get the bit clock from mclk */
266 if (iface->mclk_rate % srate) {
268 "can't derive sclk %lu from mclk %lu\n",
269 srate, iface->mclk_rate);
274 ret = clk_set_rate(iface->sclk, srate);
276 dev_err(dai->dev, "setting bit clock failed: %d\n", ret);
280 /* Set the bit clock inversion */
281 ret = clk_set_phase(iface->sclk,
282 axg_tdm_sclk_invert(iface->fmt) ? 0 : 180);
284 dev_err(dai->dev, "setting bit clock phase failed: %d\n", ret);
291 static int axg_tdm_iface_hw_params(struct snd_pcm_substream *substream,
292 struct snd_pcm_hw_params *params,
293 struct snd_soc_dai *dai)
295 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
298 switch (iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
299 case SND_SOC_DAIFMT_I2S:
300 case SND_SOC_DAIFMT_LEFT_J:
301 case SND_SOC_DAIFMT_RIGHT_J:
302 if (iface->slots > 2) {
303 dev_err(dai->dev, "bad slot number for format: %d\n",
309 case SND_SOC_DAI_FORMAT_DSP_A:
310 case SND_SOC_DAI_FORMAT_DSP_B:
314 dev_err(dai->dev, "unsupported dai format\n");
318 ret = axg_tdm_iface_set_stream(substream, params, dai);
322 if (iface->fmt & SND_SOC_DAIFMT_CBS_CFS) {
323 ret = axg_tdm_iface_set_sclk(dai, params);
327 ret = axg_tdm_iface_set_lrclk(dai, params);
335 static int axg_tdm_iface_hw_free(struct snd_pcm_substream *substream,
336 struct snd_soc_dai *dai)
338 struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
340 /* Stop all attached formatters */
341 axg_tdm_stream_stop(ts);
346 static int axg_tdm_iface_prepare(struct snd_pcm_substream *substream,
347 struct snd_soc_dai *dai)
349 struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
351 /* Force all attached formatters to update */
352 return axg_tdm_stream_reset(ts);
355 static int axg_tdm_iface_remove_dai(struct snd_soc_dai *dai)
357 if (dai->capture_dma_data)
358 axg_tdm_stream_free(dai->capture_dma_data);
360 if (dai->playback_dma_data)
361 axg_tdm_stream_free(dai->playback_dma_data);
366 static int axg_tdm_iface_probe_dai(struct snd_soc_dai *dai)
368 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
370 if (dai->capture_widget) {
371 dai->capture_dma_data = axg_tdm_stream_alloc(iface);
372 if (!dai->capture_dma_data)
376 if (dai->playback_widget) {
377 dai->playback_dma_data = axg_tdm_stream_alloc(iface);
378 if (!dai->playback_dma_data) {
379 axg_tdm_iface_remove_dai(dai);
387 static const struct snd_soc_dai_ops axg_tdm_iface_ops = {
388 .set_sysclk = axg_tdm_iface_set_sysclk,
389 .set_fmt = axg_tdm_iface_set_fmt,
390 .startup = axg_tdm_iface_startup,
391 .hw_params = axg_tdm_iface_hw_params,
392 .prepare = axg_tdm_iface_prepare,
393 .hw_free = axg_tdm_iface_hw_free,
396 /* TDM Backend DAIs */
397 static const struct snd_soc_dai_driver axg_tdm_iface_dai_drv[] = {
401 .stream_name = "Playback",
403 .channels_max = AXG_TDM_CHANNEL_MAX,
404 .rates = AXG_TDM_RATES,
405 .formats = AXG_TDM_FORMATS,
408 .stream_name = "Capture",
410 .channels_max = AXG_TDM_CHANNEL_MAX,
411 .rates = AXG_TDM_RATES,
412 .formats = AXG_TDM_FORMATS,
415 .ops = &axg_tdm_iface_ops,
416 .probe = axg_tdm_iface_probe_dai,
417 .remove = axg_tdm_iface_remove_dai,
419 [TDM_IFACE_LOOPBACK] = {
420 .name = "TDM Loopback",
422 .stream_name = "Loopback",
424 .channels_max = AXG_TDM_CHANNEL_MAX,
425 .rates = AXG_TDM_RATES,
426 .formats = AXG_TDM_FORMATS,
428 .id = TDM_IFACE_LOOPBACK,
429 .ops = &axg_tdm_iface_ops,
430 .probe = axg_tdm_iface_probe_dai,
431 .remove = axg_tdm_iface_remove_dai,
435 static int axg_tdm_iface_set_bias_level(struct snd_soc_component *component,
436 enum snd_soc_bias_level level)
438 struct axg_tdm_iface *iface = snd_soc_component_get_drvdata(component);
439 enum snd_soc_bias_level now =
440 snd_soc_component_get_bias_level(component);
444 case SND_SOC_BIAS_PREPARE:
445 if (now == SND_SOC_BIAS_STANDBY)
446 ret = clk_prepare_enable(iface->mclk);
449 case SND_SOC_BIAS_STANDBY:
450 if (now == SND_SOC_BIAS_PREPARE)
451 clk_disable_unprepare(iface->mclk);
454 case SND_SOC_BIAS_OFF:
455 case SND_SOC_BIAS_ON:
462 static const struct snd_soc_component_driver axg_tdm_iface_component_drv = {
463 .set_bias_level = axg_tdm_iface_set_bias_level,
466 static const struct of_device_id axg_tdm_iface_of_match[] = {
467 { .compatible = "amlogic,axg-tdm-iface", },
470 MODULE_DEVICE_TABLE(of, axg_tdm_iface_of_match);
472 static int axg_tdm_iface_probe(struct platform_device *pdev)
474 struct device *dev = &pdev->dev;
475 struct snd_soc_dai_driver *dai_drv;
476 struct axg_tdm_iface *iface;
479 iface = devm_kzalloc(dev, sizeof(*iface), GFP_KERNEL);
482 platform_set_drvdata(pdev, iface);
485 * Duplicate dai driver: depending on the slot masks configuration
486 * We'll change the number of channel provided by DAI stream, so dpcm
487 * channel merge can be done properly
489 dai_drv = devm_kcalloc(dev, ARRAY_SIZE(axg_tdm_iface_dai_drv),
490 sizeof(*dai_drv), GFP_KERNEL);
494 for (i = 0; i < ARRAY_SIZE(axg_tdm_iface_dai_drv); i++)
495 memcpy(&dai_drv[i], &axg_tdm_iface_dai_drv[i],
498 /* Bit clock provided on the pad */
499 iface->sclk = devm_clk_get(dev, "sclk");
500 if (IS_ERR(iface->sclk)) {
501 ret = PTR_ERR(iface->sclk);
502 if (ret != -EPROBE_DEFER)
503 dev_err(dev, "failed to get sclk: %d\n", ret);
507 /* Sample clock provided on the pad */
508 iface->lrclk = devm_clk_get(dev, "lrclk");
509 if (IS_ERR(iface->lrclk)) {
510 ret = PTR_ERR(iface->lrclk);
511 if (ret != -EPROBE_DEFER)
512 dev_err(dev, "failed to get lrclk: %d\n", ret);
517 * mclk maybe be missing when the cpu dai is in slave mode and
518 * the codec does not require it to provide a master clock.
519 * At this point, ignore the error if mclk is missing. We'll
520 * throw an error if the cpu dai is master and mclk is missing
522 iface->mclk = devm_clk_get(dev, "mclk");
523 if (IS_ERR(iface->mclk)) {
524 ret = PTR_ERR(iface->mclk);
525 if (ret == -ENOENT) {
528 if (ret != -EPROBE_DEFER)
529 dev_err(dev, "failed to get mclk: %d\n", ret);
534 return devm_snd_soc_register_component(dev,
535 &axg_tdm_iface_component_drv, dai_drv,
536 ARRAY_SIZE(axg_tdm_iface_dai_drv));
539 static struct platform_driver axg_tdm_iface_pdrv = {
540 .probe = axg_tdm_iface_probe,
542 .name = "axg-tdm-iface",
543 .of_match_table = axg_tdm_iface_of_match,
546 module_platform_driver(axg_tdm_iface_pdrv);
548 MODULE_DESCRIPTION("Amlogic AXG TDM interface driver");
549 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
550 MODULE_LICENSE("GPL v2");