1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Copyright (c) 2018 BayLibre, SAS.
4 // Author: Jerome Brunet <jbrunet@baylibre.com>
7 #include <linux/module.h>
8 #include <linux/of_platform.h>
9 #include <sound/pcm_params.h>
10 #include <sound/soc.h>
11 #include <sound/soc-dai.h>
20 static unsigned int axg_tdm_slots_total(u32 *mask)
22 unsigned int slots = 0;
28 /* Count the total number of slots provided by all 4 lanes */
29 for (i = 0; i < AXG_TDM_NUM_LANES; i++)
30 slots += hweight32(mask[i]);
35 int axg_tdm_set_tdm_slots(struct snd_soc_dai *dai, u32 *tx_mask,
36 u32 *rx_mask, unsigned int slots,
37 unsigned int slot_width)
39 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
40 struct axg_tdm_stream *tx = snd_soc_dai_dma_data_get_playback(dai);
41 struct axg_tdm_stream *rx = snd_soc_dai_dma_data_get_capture(dai);
42 unsigned int tx_slots, rx_slots;
45 tx_slots = axg_tdm_slots_total(tx_mask);
46 rx_slots = axg_tdm_slots_total(rx_mask);
48 /* We should at least have a slot for a valid interface */
49 if (!tx_slots && !rx_slots) {
50 dev_err(dai->dev, "interface has no slot\n");
61 fmt |= SNDRV_PCM_FMTBIT_S32_LE;
64 fmt |= SNDRV_PCM_FMTBIT_S24_LE;
65 fmt |= SNDRV_PCM_FMTBIT_S20_LE;
68 fmt |= SNDRV_PCM_FMTBIT_S16_LE;
71 fmt |= SNDRV_PCM_FMTBIT_S8;
74 dev_err(dai->dev, "unsupported slot width: %d\n", slot_width);
78 iface->slot_width = slot_width;
80 /* Amend the dai driver and let dpcm merge do its job */
83 dai->driver->playback.channels_max = tx_slots;
84 dai->driver->playback.formats = fmt;
89 dai->driver->capture.channels_max = rx_slots;
90 dai->driver->capture.formats = fmt;
95 EXPORT_SYMBOL_GPL(axg_tdm_set_tdm_slots);
97 static int axg_tdm_iface_set_sysclk(struct snd_soc_dai *dai, int clk_id,
98 unsigned int freq, int dir)
100 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
103 if (dir == SND_SOC_CLOCK_OUT && clk_id == 0) {
105 dev_warn(dai->dev, "master clock not provided\n");
107 ret = clk_set_rate(iface->mclk, freq);
109 iface->mclk_rate = freq;
116 static int axg_tdm_iface_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
118 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
120 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
121 case SND_SOC_DAIFMT_BP_FP:
123 dev_err(dai->dev, "cpu clock master: mclk missing\n");
128 case SND_SOC_DAIFMT_BC_FC:
131 case SND_SOC_DAIFMT_BP_FC:
132 case SND_SOC_DAIFMT_BC_FP:
133 dev_err(dai->dev, "only CBS_CFS and CBM_CFM are supported\n");
143 static int axg_tdm_iface_startup(struct snd_pcm_substream *substream,
144 struct snd_soc_dai *dai)
146 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
147 struct axg_tdm_stream *ts =
148 snd_soc_dai_get_dma_data(dai, substream);
151 if (!axg_tdm_slots_total(ts->mask)) {
152 dev_err(dai->dev, "interface has not slots\n");
156 /* Apply component wide rate symmetry */
157 if (snd_soc_component_active(dai->component)) {
158 ret = snd_pcm_hw_constraint_single(substream->runtime,
159 SNDRV_PCM_HW_PARAM_RATE,
163 "can't set iface rate constraint\n");
171 static int axg_tdm_iface_set_stream(struct snd_pcm_substream *substream,
172 struct snd_pcm_hw_params *params,
173 struct snd_soc_dai *dai)
175 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
176 struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
177 unsigned int channels = params_channels(params);
178 unsigned int width = params_width(params);
180 /* Save rate and sample_bits for component symmetry */
181 iface->rate = params_rate(params);
183 /* Make sure this interface can cope with the stream */
184 if (axg_tdm_slots_total(ts->mask) < channels) {
185 dev_err(dai->dev, "not enough slots for channels\n");
189 if (iface->slot_width < width) {
190 dev_err(dai->dev, "incompatible slots width for stream\n");
194 /* Save the parameter for tdmout/tdmin widgets */
195 ts->physical_width = params_physical_width(params);
196 ts->width = params_width(params);
197 ts->channels = params_channels(params);
202 static int axg_tdm_iface_set_lrclk(struct snd_soc_dai *dai,
203 struct snd_pcm_hw_params *params)
205 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
206 unsigned int ratio_num;
209 ret = clk_set_rate(iface->lrclk, params_rate(params));
211 dev_err(dai->dev, "setting sample clock failed: %d\n", ret);
215 switch (iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
216 case SND_SOC_DAIFMT_I2S:
217 case SND_SOC_DAIFMT_LEFT_J:
218 case SND_SOC_DAIFMT_RIGHT_J:
219 /* 50% duty cycle ratio */
223 case SND_SOC_DAIFMT_DSP_A:
224 case SND_SOC_DAIFMT_DSP_B:
226 * A zero duty cycle ratio will result in setting the mininum
227 * ratio possible which, for this clock, is 1 cycle of the
228 * parent bclk clock high and the rest low, This is exactly
238 ret = clk_set_duty_cycle(iface->lrclk, ratio_num, 2);
241 "setting sample clock duty cycle failed: %d\n", ret);
245 /* Set sample clock inversion */
246 ret = clk_set_phase(iface->lrclk,
247 axg_tdm_lrclk_invert(iface->fmt) ? 180 : 0);
250 "setting sample clock phase failed: %d\n", ret);
257 static int axg_tdm_iface_set_sclk(struct snd_soc_dai *dai,
258 struct snd_pcm_hw_params *params)
260 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
264 srate = iface->slots * iface->slot_width * params_rate(params);
266 if (!iface->mclk_rate) {
267 /* If no specific mclk is requested, default to bit clock * 4 */
268 clk_set_rate(iface->mclk, 4 * srate);
270 /* Check if we can actually get the bit clock from mclk */
271 if (iface->mclk_rate % srate) {
273 "can't derive sclk %lu from mclk %lu\n",
274 srate, iface->mclk_rate);
279 ret = clk_set_rate(iface->sclk, srate);
281 dev_err(dai->dev, "setting bit clock failed: %d\n", ret);
285 /* Set the bit clock inversion */
286 ret = clk_set_phase(iface->sclk,
287 axg_tdm_sclk_invert(iface->fmt) ? 0 : 180);
289 dev_err(dai->dev, "setting bit clock phase failed: %d\n", ret);
296 static int axg_tdm_iface_hw_params(struct snd_pcm_substream *substream,
297 struct snd_pcm_hw_params *params,
298 struct snd_soc_dai *dai)
300 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
303 switch (iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
304 case SND_SOC_DAIFMT_I2S:
305 case SND_SOC_DAIFMT_LEFT_J:
306 case SND_SOC_DAIFMT_RIGHT_J:
307 if (iface->slots > 2) {
308 dev_err(dai->dev, "bad slot number for format: %d\n",
314 case SND_SOC_DAIFMT_DSP_A:
315 case SND_SOC_DAIFMT_DSP_B:
319 dev_err(dai->dev, "unsupported dai format\n");
323 ret = axg_tdm_iface_set_stream(substream, params, dai);
327 if ((iface->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) ==
328 SND_SOC_DAIFMT_BP_FP) {
329 ret = axg_tdm_iface_set_sclk(dai, params);
333 ret = axg_tdm_iface_set_lrclk(dai, params);
341 static int axg_tdm_iface_hw_free(struct snd_pcm_substream *substream,
342 struct snd_soc_dai *dai)
344 struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
346 /* Stop all attached formatters */
347 axg_tdm_stream_stop(ts);
352 static int axg_tdm_iface_prepare(struct snd_pcm_substream *substream,
353 struct snd_soc_dai *dai)
355 struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
357 /* Force all attached formatters to update */
358 return axg_tdm_stream_reset(ts);
361 static int axg_tdm_iface_remove_dai(struct snd_soc_dai *dai)
365 for_each_pcm_streams(stream) {
366 struct axg_tdm_stream *ts = snd_soc_dai_dma_data_get(dai, stream);
369 axg_tdm_stream_free(ts);
375 static int axg_tdm_iface_probe_dai(struct snd_soc_dai *dai)
377 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
380 for_each_pcm_streams(stream) {
381 struct axg_tdm_stream *ts;
383 if (!snd_soc_dai_get_widget(dai, stream))
386 ts = axg_tdm_stream_alloc(iface);
388 axg_tdm_iface_remove_dai(dai);
391 snd_soc_dai_dma_data_set(dai, stream, ts);
397 static const struct snd_soc_dai_ops axg_tdm_iface_ops = {
398 .set_sysclk = axg_tdm_iface_set_sysclk,
399 .set_fmt = axg_tdm_iface_set_fmt,
400 .startup = axg_tdm_iface_startup,
401 .hw_params = axg_tdm_iface_hw_params,
402 .prepare = axg_tdm_iface_prepare,
403 .hw_free = axg_tdm_iface_hw_free,
406 /* TDM Backend DAIs */
407 static const struct snd_soc_dai_driver axg_tdm_iface_dai_drv[] = {
411 .stream_name = "Playback",
413 .channels_max = AXG_TDM_CHANNEL_MAX,
414 .rates = AXG_TDM_RATES,
415 .formats = AXG_TDM_FORMATS,
418 .stream_name = "Capture",
420 .channels_max = AXG_TDM_CHANNEL_MAX,
421 .rates = AXG_TDM_RATES,
422 .formats = AXG_TDM_FORMATS,
425 .ops = &axg_tdm_iface_ops,
426 .probe = axg_tdm_iface_probe_dai,
427 .remove = axg_tdm_iface_remove_dai,
429 [TDM_IFACE_LOOPBACK] = {
430 .name = "TDM Loopback",
432 .stream_name = "Loopback",
434 .channels_max = AXG_TDM_CHANNEL_MAX,
435 .rates = AXG_TDM_RATES,
436 .formats = AXG_TDM_FORMATS,
438 .id = TDM_IFACE_LOOPBACK,
439 .ops = &axg_tdm_iface_ops,
440 .probe = axg_tdm_iface_probe_dai,
441 .remove = axg_tdm_iface_remove_dai,
445 static int axg_tdm_iface_set_bias_level(struct snd_soc_component *component,
446 enum snd_soc_bias_level level)
448 struct axg_tdm_iface *iface = snd_soc_component_get_drvdata(component);
449 enum snd_soc_bias_level now =
450 snd_soc_component_get_bias_level(component);
454 case SND_SOC_BIAS_PREPARE:
455 if (now == SND_SOC_BIAS_STANDBY)
456 ret = clk_prepare_enable(iface->mclk);
459 case SND_SOC_BIAS_STANDBY:
460 if (now == SND_SOC_BIAS_PREPARE)
461 clk_disable_unprepare(iface->mclk);
464 case SND_SOC_BIAS_OFF:
465 case SND_SOC_BIAS_ON:
472 static const struct snd_soc_dapm_widget axg_tdm_iface_dapm_widgets[] = {
473 SND_SOC_DAPM_SIGGEN("Playback Signal"),
476 static const struct snd_soc_dapm_route axg_tdm_iface_dapm_routes[] = {
477 { "Loopback", NULL, "Playback Signal" },
480 static const struct snd_soc_component_driver axg_tdm_iface_component_drv = {
481 .dapm_widgets = axg_tdm_iface_dapm_widgets,
482 .num_dapm_widgets = ARRAY_SIZE(axg_tdm_iface_dapm_widgets),
483 .dapm_routes = axg_tdm_iface_dapm_routes,
484 .num_dapm_routes = ARRAY_SIZE(axg_tdm_iface_dapm_routes),
485 .set_bias_level = axg_tdm_iface_set_bias_level,
488 static const struct of_device_id axg_tdm_iface_of_match[] = {
489 { .compatible = "amlogic,axg-tdm-iface", },
492 MODULE_DEVICE_TABLE(of, axg_tdm_iface_of_match);
494 static int axg_tdm_iface_probe(struct platform_device *pdev)
496 struct device *dev = &pdev->dev;
497 struct snd_soc_dai_driver *dai_drv;
498 struct axg_tdm_iface *iface;
501 iface = devm_kzalloc(dev, sizeof(*iface), GFP_KERNEL);
504 platform_set_drvdata(pdev, iface);
507 * Duplicate dai driver: depending on the slot masks configuration
508 * We'll change the number of channel provided by DAI stream, so dpcm
509 * channel merge can be done properly
511 dai_drv = devm_kcalloc(dev, ARRAY_SIZE(axg_tdm_iface_dai_drv),
512 sizeof(*dai_drv), GFP_KERNEL);
516 for (i = 0; i < ARRAY_SIZE(axg_tdm_iface_dai_drv); i++)
517 memcpy(&dai_drv[i], &axg_tdm_iface_dai_drv[i],
520 /* Bit clock provided on the pad */
521 iface->sclk = devm_clk_get(dev, "sclk");
522 if (IS_ERR(iface->sclk))
523 return dev_err_probe(dev, PTR_ERR(iface->sclk), "failed to get sclk\n");
525 /* Sample clock provided on the pad */
526 iface->lrclk = devm_clk_get(dev, "lrclk");
527 if (IS_ERR(iface->lrclk))
528 return dev_err_probe(dev, PTR_ERR(iface->lrclk), "failed to get lrclk\n");
531 * mclk maybe be missing when the cpu dai is in slave mode and
532 * the codec does not require it to provide a master clock.
533 * At this point, ignore the error if mclk is missing. We'll
534 * throw an error if the cpu dai is master and mclk is missing
536 iface->mclk = devm_clk_get_optional(dev, "mclk");
537 if (IS_ERR(iface->mclk))
538 return dev_err_probe(dev, PTR_ERR(iface->mclk), "failed to get mclk\n");
540 return devm_snd_soc_register_component(dev,
541 &axg_tdm_iface_component_drv, dai_drv,
542 ARRAY_SIZE(axg_tdm_iface_dai_drv));
545 static struct platform_driver axg_tdm_iface_pdrv = {
546 .probe = axg_tdm_iface_probe,
548 .name = "axg-tdm-iface",
549 .of_match_table = axg_tdm_iface_of_match,
552 module_platform_driver(axg_tdm_iface_pdrv);
554 MODULE_DESCRIPTION("Amlogic AXG TDM interface driver");
555 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
556 MODULE_LICENSE("GPL v2");