1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Copyright (c) 2018 BayLibre, SAS.
4 // Author: Jerome Brunet <jbrunet@baylibre.com>
7 #include <linux/module.h>
8 #include <linux/of_platform.h>
9 #include <sound/pcm_params.h>
10 #include <sound/soc.h>
11 #include <sound/soc-dai.h>
20 static unsigned int axg_tdm_slots_total(u32 *mask)
22 unsigned int slots = 0;
28 /* Count the total number of slots provided by all 4 lanes */
29 for (i = 0; i < AXG_TDM_NUM_LANES; i++)
30 slots += hweight32(mask[i]);
35 int axg_tdm_set_tdm_slots(struct snd_soc_dai *dai, u32 *tx_mask,
36 u32 *rx_mask, unsigned int slots,
37 unsigned int slot_width)
39 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
40 struct axg_tdm_stream *tx = (struct axg_tdm_stream *)
41 dai->playback_dma_data;
42 struct axg_tdm_stream *rx = (struct axg_tdm_stream *)
43 dai->capture_dma_data;
44 unsigned int tx_slots, rx_slots;
47 tx_slots = axg_tdm_slots_total(tx_mask);
48 rx_slots = axg_tdm_slots_total(rx_mask);
50 /* We should at least have a slot for a valid interface */
51 if (!tx_slots && !rx_slots) {
52 dev_err(dai->dev, "interface has no slot\n");
63 fmt |= SNDRV_PCM_FMTBIT_S32_LE;
66 fmt |= SNDRV_PCM_FMTBIT_S24_LE;
67 fmt |= SNDRV_PCM_FMTBIT_S20_LE;
70 fmt |= SNDRV_PCM_FMTBIT_S16_LE;
73 fmt |= SNDRV_PCM_FMTBIT_S8;
76 dev_err(dai->dev, "unsupported slot width: %d\n", slot_width);
80 iface->slot_width = slot_width;
82 /* Amend the dai driver and let dpcm merge do its job */
85 dai->driver->playback.channels_max = tx_slots;
86 dai->driver->playback.formats = fmt;
91 dai->driver->capture.channels_max = rx_slots;
92 dai->driver->capture.formats = fmt;
97 EXPORT_SYMBOL_GPL(axg_tdm_set_tdm_slots);
99 static int axg_tdm_iface_set_sysclk(struct snd_soc_dai *dai, int clk_id,
100 unsigned int freq, int dir)
102 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
105 if (dir == SND_SOC_CLOCK_OUT && clk_id == 0) {
107 dev_warn(dai->dev, "master clock not provided\n");
109 ret = clk_set_rate(iface->mclk, freq);
111 iface->mclk_rate = freq;
118 static int axg_tdm_iface_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
120 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
122 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
123 case SND_SOC_DAIFMT_CBS_CFS:
125 dev_err(dai->dev, "cpu clock master: mclk missing\n");
130 case SND_SOC_DAIFMT_CBM_CFM:
133 case SND_SOC_DAIFMT_CBS_CFM:
134 case SND_SOC_DAIFMT_CBM_CFS:
135 dev_err(dai->dev, "only CBS_CFS and CBM_CFM are supported\n");
145 static int axg_tdm_iface_startup(struct snd_pcm_substream *substream,
146 struct snd_soc_dai *dai)
148 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
149 struct axg_tdm_stream *ts =
150 snd_soc_dai_get_dma_data(dai, substream);
153 if (!axg_tdm_slots_total(ts->mask)) {
154 dev_err(dai->dev, "interface has not slots\n");
158 /* Apply component wide rate symmetry */
159 if (snd_soc_component_active(dai->component)) {
160 ret = snd_pcm_hw_constraint_single(substream->runtime,
161 SNDRV_PCM_HW_PARAM_RATE,
165 "can't set iface rate constraint\n");
173 static int axg_tdm_iface_set_stream(struct snd_pcm_substream *substream,
174 struct snd_pcm_hw_params *params,
175 struct snd_soc_dai *dai)
177 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
178 struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
179 unsigned int channels = params_channels(params);
180 unsigned int width = params_width(params);
182 /* Save rate and sample_bits for component symmetry */
183 iface->rate = params_rate(params);
185 /* Make sure this interface can cope with the stream */
186 if (axg_tdm_slots_total(ts->mask) < channels) {
187 dev_err(dai->dev, "not enough slots for channels\n");
191 if (iface->slot_width < width) {
192 dev_err(dai->dev, "incompatible slots width for stream\n");
196 /* Save the parameter for tdmout/tdmin widgets */
197 ts->physical_width = params_physical_width(params);
198 ts->width = params_width(params);
199 ts->channels = params_channels(params);
204 static int axg_tdm_iface_set_lrclk(struct snd_soc_dai *dai,
205 struct snd_pcm_hw_params *params)
207 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
208 unsigned int ratio_num;
211 ret = clk_set_rate(iface->lrclk, params_rate(params));
213 dev_err(dai->dev, "setting sample clock failed: %d\n", ret);
217 switch (iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
218 case SND_SOC_DAIFMT_I2S:
219 case SND_SOC_DAIFMT_LEFT_J:
220 case SND_SOC_DAIFMT_RIGHT_J:
221 /* 50% duty cycle ratio */
225 case SND_SOC_DAIFMT_DSP_A:
226 case SND_SOC_DAIFMT_DSP_B:
228 * A zero duty cycle ratio will result in setting the mininum
229 * ratio possible which, for this clock, is 1 cycle of the
230 * parent bclk clock high and the rest low, This is exactly
240 ret = clk_set_duty_cycle(iface->lrclk, ratio_num, 2);
243 "setting sample clock duty cycle failed: %d\n", ret);
247 /* Set sample clock inversion */
248 ret = clk_set_phase(iface->lrclk,
249 axg_tdm_lrclk_invert(iface->fmt) ? 180 : 0);
252 "setting sample clock phase failed: %d\n", ret);
259 static int axg_tdm_iface_set_sclk(struct snd_soc_dai *dai,
260 struct snd_pcm_hw_params *params)
262 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
266 srate = iface->slots * iface->slot_width * params_rate(params);
268 if (!iface->mclk_rate) {
269 /* If no specific mclk is requested, default to bit clock * 4 */
270 clk_set_rate(iface->mclk, 4 * srate);
272 /* Check if we can actually get the bit clock from mclk */
273 if (iface->mclk_rate % srate) {
275 "can't derive sclk %lu from mclk %lu\n",
276 srate, iface->mclk_rate);
281 ret = clk_set_rate(iface->sclk, srate);
283 dev_err(dai->dev, "setting bit clock failed: %d\n", ret);
287 /* Set the bit clock inversion */
288 ret = clk_set_phase(iface->sclk,
289 axg_tdm_sclk_invert(iface->fmt) ? 0 : 180);
291 dev_err(dai->dev, "setting bit clock phase failed: %d\n", ret);
298 static int axg_tdm_iface_hw_params(struct snd_pcm_substream *substream,
299 struct snd_pcm_hw_params *params,
300 struct snd_soc_dai *dai)
302 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
305 switch (iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
306 case SND_SOC_DAIFMT_I2S:
307 case SND_SOC_DAIFMT_LEFT_J:
308 case SND_SOC_DAIFMT_RIGHT_J:
309 if (iface->slots > 2) {
310 dev_err(dai->dev, "bad slot number for format: %d\n",
316 case SND_SOC_DAIFMT_DSP_A:
317 case SND_SOC_DAIFMT_DSP_B:
321 dev_err(dai->dev, "unsupported dai format\n");
325 ret = axg_tdm_iface_set_stream(substream, params, dai);
329 if ((iface->fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
330 SND_SOC_DAIFMT_CBS_CFS) {
331 ret = axg_tdm_iface_set_sclk(dai, params);
335 ret = axg_tdm_iface_set_lrclk(dai, params);
343 static int axg_tdm_iface_hw_free(struct snd_pcm_substream *substream,
344 struct snd_soc_dai *dai)
346 struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
348 /* Stop all attached formatters */
349 axg_tdm_stream_stop(ts);
354 static int axg_tdm_iface_trigger(struct snd_pcm_substream *substream,
356 struct snd_soc_dai *dai)
358 struct axg_tdm_stream *ts =
359 snd_soc_dai_get_dma_data(dai, substream);
362 case SNDRV_PCM_TRIGGER_START:
363 case SNDRV_PCM_TRIGGER_RESUME:
364 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
365 axg_tdm_stream_start(ts);
367 case SNDRV_PCM_TRIGGER_SUSPEND:
368 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
369 case SNDRV_PCM_TRIGGER_STOP:
370 axg_tdm_stream_stop(ts);
379 static int axg_tdm_iface_remove_dai(struct snd_soc_dai *dai)
381 if (dai->capture_dma_data)
382 axg_tdm_stream_free(dai->capture_dma_data);
384 if (dai->playback_dma_data)
385 axg_tdm_stream_free(dai->playback_dma_data);
390 static int axg_tdm_iface_probe_dai(struct snd_soc_dai *dai)
392 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
394 if (dai->capture_widget) {
395 dai->capture_dma_data = axg_tdm_stream_alloc(iface);
396 if (!dai->capture_dma_data)
400 if (dai->playback_widget) {
401 dai->playback_dma_data = axg_tdm_stream_alloc(iface);
402 if (!dai->playback_dma_data) {
403 axg_tdm_iface_remove_dai(dai);
411 static const struct snd_soc_dai_ops axg_tdm_iface_ops = {
412 .set_sysclk = axg_tdm_iface_set_sysclk,
413 .set_fmt = axg_tdm_iface_set_fmt,
414 .startup = axg_tdm_iface_startup,
415 .hw_params = axg_tdm_iface_hw_params,
416 .hw_free = axg_tdm_iface_hw_free,
417 .trigger = axg_tdm_iface_trigger,
420 /* TDM Backend DAIs */
421 static const struct snd_soc_dai_driver axg_tdm_iface_dai_drv[] = {
425 .stream_name = "Playback",
427 .channels_max = AXG_TDM_CHANNEL_MAX,
428 .rates = AXG_TDM_RATES,
429 .formats = AXG_TDM_FORMATS,
432 .stream_name = "Capture",
434 .channels_max = AXG_TDM_CHANNEL_MAX,
435 .rates = AXG_TDM_RATES,
436 .formats = AXG_TDM_FORMATS,
439 .ops = &axg_tdm_iface_ops,
440 .probe = axg_tdm_iface_probe_dai,
441 .remove = axg_tdm_iface_remove_dai,
443 [TDM_IFACE_LOOPBACK] = {
444 .name = "TDM Loopback",
446 .stream_name = "Loopback",
448 .channels_max = AXG_TDM_CHANNEL_MAX,
449 .rates = AXG_TDM_RATES,
450 .formats = AXG_TDM_FORMATS,
452 .id = TDM_IFACE_LOOPBACK,
453 .ops = &axg_tdm_iface_ops,
454 .probe = axg_tdm_iface_probe_dai,
455 .remove = axg_tdm_iface_remove_dai,
459 static int axg_tdm_iface_set_bias_level(struct snd_soc_component *component,
460 enum snd_soc_bias_level level)
462 struct axg_tdm_iface *iface = snd_soc_component_get_drvdata(component);
463 enum snd_soc_bias_level now =
464 snd_soc_component_get_bias_level(component);
468 case SND_SOC_BIAS_PREPARE:
469 if (now == SND_SOC_BIAS_STANDBY)
470 ret = clk_prepare_enable(iface->mclk);
473 case SND_SOC_BIAS_STANDBY:
474 if (now == SND_SOC_BIAS_PREPARE)
475 clk_disable_unprepare(iface->mclk);
478 case SND_SOC_BIAS_OFF:
479 case SND_SOC_BIAS_ON:
486 static const struct snd_soc_dapm_widget axg_tdm_iface_dapm_widgets[] = {
487 SND_SOC_DAPM_SIGGEN("Playback Signal"),
490 static const struct snd_soc_dapm_route axg_tdm_iface_dapm_routes[] = {
491 { "Loopback", NULL, "Playback Signal" },
494 static const struct snd_soc_component_driver axg_tdm_iface_component_drv = {
495 .dapm_widgets = axg_tdm_iface_dapm_widgets,
496 .num_dapm_widgets = ARRAY_SIZE(axg_tdm_iface_dapm_widgets),
497 .dapm_routes = axg_tdm_iface_dapm_routes,
498 .num_dapm_routes = ARRAY_SIZE(axg_tdm_iface_dapm_routes),
499 .set_bias_level = axg_tdm_iface_set_bias_level,
502 static const struct of_device_id axg_tdm_iface_of_match[] = {
503 { .compatible = "amlogic,axg-tdm-iface", },
506 MODULE_DEVICE_TABLE(of, axg_tdm_iface_of_match);
508 static int axg_tdm_iface_probe(struct platform_device *pdev)
510 struct device *dev = &pdev->dev;
511 struct snd_soc_dai_driver *dai_drv;
512 struct axg_tdm_iface *iface;
515 iface = devm_kzalloc(dev, sizeof(*iface), GFP_KERNEL);
518 platform_set_drvdata(pdev, iface);
521 * Duplicate dai driver: depending on the slot masks configuration
522 * We'll change the number of channel provided by DAI stream, so dpcm
523 * channel merge can be done properly
525 dai_drv = devm_kcalloc(dev, ARRAY_SIZE(axg_tdm_iface_dai_drv),
526 sizeof(*dai_drv), GFP_KERNEL);
530 for (i = 0; i < ARRAY_SIZE(axg_tdm_iface_dai_drv); i++)
531 memcpy(&dai_drv[i], &axg_tdm_iface_dai_drv[i],
534 /* Bit clock provided on the pad */
535 iface->sclk = devm_clk_get(dev, "sclk");
536 if (IS_ERR(iface->sclk))
537 return dev_err_probe(dev, PTR_ERR(iface->sclk), "failed to get sclk\n");
539 /* Sample clock provided on the pad */
540 iface->lrclk = devm_clk_get(dev, "lrclk");
541 if (IS_ERR(iface->lrclk))
542 return dev_err_probe(dev, PTR_ERR(iface->lrclk), "failed to get lrclk\n");
545 * mclk maybe be missing when the cpu dai is in slave mode and
546 * the codec does not require it to provide a master clock.
547 * At this point, ignore the error if mclk is missing. We'll
548 * throw an error if the cpu dai is master and mclk is missing
550 iface->mclk = devm_clk_get(dev, "mclk");
551 if (IS_ERR(iface->mclk)) {
552 ret = PTR_ERR(iface->mclk);
556 return dev_err_probe(dev, ret, "failed to get mclk\n");
559 return devm_snd_soc_register_component(dev,
560 &axg_tdm_iface_component_drv, dai_drv,
561 ARRAY_SIZE(axg_tdm_iface_dai_drv));
564 static struct platform_driver axg_tdm_iface_pdrv = {
565 .probe = axg_tdm_iface_probe,
567 .name = "axg-tdm-iface",
568 .of_match_table = axg_tdm_iface_of_match,
571 module_platform_driver(axg_tdm_iface_pdrv);
573 MODULE_DESCRIPTION("Amlogic AXG TDM interface driver");
574 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
575 MODULE_LICENSE("GPL v2");