1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Copyright (c) 2018 BayLibre, SAS.
4 // Author: Jerome Brunet <jbrunet@baylibre.com>
7 #include <linux/of_irq.h>
8 #include <linux/of_platform.h>
9 #include <linux/module.h>
10 #include <linux/regmap.h>
11 #include <linux/reset.h>
12 #include <sound/pcm_params.h>
13 #include <sound/soc.h>
14 #include <sound/soc-dai.h>
19 * This file implements the platform operations common to the playback and
20 * capture frontend DAI. The logic behind this two types of fifo is very
21 * similar but some difference exist.
22 * These differences the respective DAI drivers
25 static struct snd_pcm_hardware axg_fifo_hw = {
26 .info = (SNDRV_PCM_INFO_INTERLEAVED |
28 SNDRV_PCM_INFO_MMAP_VALID |
29 SNDRV_PCM_INFO_BLOCK_TRANSFER |
30 SNDRV_PCM_INFO_PAUSE),
32 .formats = AXG_FIFO_FORMATS,
36 .channels_max = AXG_FIFO_CH_MAX,
37 .period_bytes_min = AXG_FIFO_MIN_DEPTH,
38 .period_bytes_max = UINT_MAX,
40 .periods_max = UINT_MAX,
42 /* No real justification for this */
43 .buffer_bytes_max = 1 * 1024 * 1024,
46 static struct snd_soc_dai *axg_fifo_dai(struct snd_pcm_substream *ss)
48 struct snd_soc_pcm_runtime *rtd = ss->private_data;
53 static struct axg_fifo *axg_fifo_data(struct snd_pcm_substream *ss)
55 struct snd_soc_dai *dai = axg_fifo_dai(ss);
57 return snd_soc_dai_get_drvdata(dai);
60 static struct device *axg_fifo_dev(struct snd_pcm_substream *ss)
62 struct snd_soc_dai *dai = axg_fifo_dai(ss);
67 static void __dma_enable(struct axg_fifo *fifo, bool enable)
69 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_DMA_EN,
70 enable ? CTRL0_DMA_EN : 0);
73 static int axg_fifo_pcm_trigger(struct snd_pcm_substream *ss, int cmd)
75 struct axg_fifo *fifo = axg_fifo_data(ss);
78 case SNDRV_PCM_TRIGGER_START:
79 case SNDRV_PCM_TRIGGER_RESUME:
80 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
81 __dma_enable(fifo, true);
83 case SNDRV_PCM_TRIGGER_SUSPEND:
84 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
85 case SNDRV_PCM_TRIGGER_STOP:
86 __dma_enable(fifo, false);
95 static snd_pcm_uframes_t axg_fifo_pcm_pointer(struct snd_pcm_substream *ss)
97 struct axg_fifo *fifo = axg_fifo_data(ss);
98 struct snd_pcm_runtime *runtime = ss->runtime;
101 regmap_read(fifo->map, FIFO_STATUS2, &addr);
103 return bytes_to_frames(runtime, addr - (unsigned int)runtime->dma_addr);
106 static int axg_fifo_pcm_hw_params(struct snd_pcm_substream *ss,
107 struct snd_pcm_hw_params *params)
109 struct snd_pcm_runtime *runtime = ss->runtime;
110 struct axg_fifo *fifo = axg_fifo_data(ss);
112 unsigned int burst_num;
115 ret = snd_pcm_lib_malloc_pages(ss, params_buffer_bytes(params));
119 /* Setup dma memory pointers */
120 end_ptr = runtime->dma_addr + runtime->dma_bytes - AXG_FIFO_BURST;
121 regmap_write(fifo->map, FIFO_START_ADDR, runtime->dma_addr);
122 regmap_write(fifo->map, FIFO_FINISH_ADDR, end_ptr);
124 /* Setup interrupt periodicity */
125 burst_num = params_period_bytes(params) / AXG_FIFO_BURST;
126 regmap_write(fifo->map, FIFO_INT_ADDR, burst_num);
128 /* Enable block count irq */
129 regmap_update_bits(fifo->map, FIFO_CTRL0,
130 CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT),
131 CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT));
136 static int axg_fifo_pcm_hw_free(struct snd_pcm_substream *ss)
138 struct axg_fifo *fifo = axg_fifo_data(ss);
140 /* Disable the block count irq */
141 regmap_update_bits(fifo->map, FIFO_CTRL0,
142 CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT), 0);
144 return snd_pcm_lib_free_pages(ss);
147 static void axg_fifo_ack_irq(struct axg_fifo *fifo, u8 mask)
149 regmap_update_bits(fifo->map, FIFO_CTRL1,
150 CTRL1_INT_CLR(FIFO_INT_MASK),
151 CTRL1_INT_CLR(mask));
153 /* Clear must also be cleared */
154 regmap_update_bits(fifo->map, FIFO_CTRL1,
155 CTRL1_INT_CLR(FIFO_INT_MASK),
159 static irqreturn_t axg_fifo_pcm_irq_block(int irq, void *dev_id)
161 struct snd_pcm_substream *ss = dev_id;
162 struct axg_fifo *fifo = axg_fifo_data(ss);
165 regmap_read(fifo->map, FIFO_STATUS1, &status);
167 status = STATUS1_INT_STS(status) & FIFO_INT_MASK;
168 if (status & FIFO_INT_COUNT_REPEAT)
169 snd_pcm_period_elapsed(ss);
171 dev_dbg(axg_fifo_dev(ss), "unexpected irq - STS 0x%02x\n",
175 axg_fifo_ack_irq(fifo, status);
177 return IRQ_RETVAL(status);
180 static int axg_fifo_pcm_open(struct snd_pcm_substream *ss)
182 struct axg_fifo *fifo = axg_fifo_data(ss);
183 struct device *dev = axg_fifo_dev(ss);
186 snd_soc_set_runtime_hwparams(ss, &axg_fifo_hw);
189 * Make sure the buffer and period size are multiple of the FIFO
192 ret = snd_pcm_hw_constraint_step(ss->runtime, 0,
193 SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
198 ret = snd_pcm_hw_constraint_step(ss->runtime, 0,
199 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
204 ret = request_irq(fifo->irq, axg_fifo_pcm_irq_block, 0,
209 /* Enable pclk to access registers and clock the fifo ip */
210 ret = clk_prepare_enable(fifo->pclk);
214 /* Setup status2 so it reports the memory pointer */
215 regmap_update_bits(fifo->map, FIFO_CTRL1,
216 CTRL1_STATUS2_SEL_MASK,
217 CTRL1_STATUS2_SEL(STATUS2_SEL_DDR_READ));
219 /* Make sure the dma is initially disabled */
220 __dma_enable(fifo, false);
222 /* Disable irqs until params are ready */
223 regmap_update_bits(fifo->map, FIFO_CTRL0,
224 CTRL0_INT_EN(FIFO_INT_MASK), 0);
226 /* Clear any pending interrupt */
227 axg_fifo_ack_irq(fifo, FIFO_INT_MASK);
229 /* Take memory arbitror out of reset */
230 ret = reset_control_deassert(fifo->arb);
232 clk_disable_unprepare(fifo->pclk);
237 static int axg_fifo_pcm_close(struct snd_pcm_substream *ss)
239 struct axg_fifo *fifo = axg_fifo_data(ss);
242 /* Put the memory arbitror back in reset */
243 ret = reset_control_assert(fifo->arb);
245 /* Disable fifo ip and register access */
246 clk_disable_unprepare(fifo->pclk);
249 free_irq(fifo->irq, ss);
254 const struct snd_pcm_ops axg_fifo_pcm_ops = {
255 .open = axg_fifo_pcm_open,
256 .close = axg_fifo_pcm_close,
257 .ioctl = snd_pcm_lib_ioctl,
258 .hw_params = axg_fifo_pcm_hw_params,
259 .hw_free = axg_fifo_pcm_hw_free,
260 .pointer = axg_fifo_pcm_pointer,
261 .trigger = axg_fifo_pcm_trigger,
263 EXPORT_SYMBOL_GPL(axg_fifo_pcm_ops);
265 int axg_fifo_pcm_new(struct snd_soc_pcm_runtime *rtd, unsigned int type)
267 struct snd_card *card = rtd->card->snd_card;
268 size_t size = axg_fifo_hw.buffer_bytes_max;
270 return snd_pcm_lib_preallocate_pages(rtd->pcm->streams[type].substream,
271 SNDRV_DMA_TYPE_DEV, card->dev,
274 EXPORT_SYMBOL_GPL(axg_fifo_pcm_new);
276 static const struct regmap_config axg_fifo_regmap_cfg = {
280 .max_register = FIFO_STATUS2,
283 int axg_fifo_probe(struct platform_device *pdev)
285 struct device *dev = &pdev->dev;
286 const struct axg_fifo_match_data *data;
287 struct axg_fifo *fifo;
288 struct resource *res;
291 data = of_device_get_match_data(dev);
293 dev_err(dev, "failed to match device\n");
297 fifo = devm_kzalloc(dev, sizeof(*fifo), GFP_KERNEL);
300 platform_set_drvdata(pdev, fifo);
302 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
303 regs = devm_ioremap_resource(dev, res);
305 return PTR_ERR(regs);
307 fifo->map = devm_regmap_init_mmio(dev, regs, &axg_fifo_regmap_cfg);
308 if (IS_ERR(fifo->map)) {
309 dev_err(dev, "failed to init regmap: %ld\n",
311 return PTR_ERR(fifo->map);
314 fifo->pclk = devm_clk_get(dev, NULL);
315 if (IS_ERR(fifo->pclk)) {
316 if (PTR_ERR(fifo->pclk) != -EPROBE_DEFER)
317 dev_err(dev, "failed to get pclk: %ld\n",
318 PTR_ERR(fifo->pclk));
319 return PTR_ERR(fifo->pclk);
322 fifo->arb = devm_reset_control_get_exclusive(dev, NULL);
323 if (IS_ERR(fifo->arb)) {
324 if (PTR_ERR(fifo->arb) != -EPROBE_DEFER)
325 dev_err(dev, "failed to get arb reset: %ld\n",
327 return PTR_ERR(fifo->arb);
330 fifo->irq = of_irq_get(dev->of_node, 0);
331 if (fifo->irq <= 0) {
332 dev_err(dev, "failed to get irq: %d\n", fifo->irq);
336 return devm_snd_soc_register_component(dev, data->component_drv,
339 EXPORT_SYMBOL_GPL(axg_fifo_probe);
341 MODULE_DESCRIPTION("Amlogic AXG fifo driver");
342 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
343 MODULE_LICENSE("GPL v2");