sound/soc/meson/aiu-fifo-i2s.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright (c) 2020 BayLibre, SAS.
   4 // Author: Jerome Brunet <jbrunet@baylibre.com>
   5
   6 #include <linux/bitfield.h>
   7 #include <linux/clk.h>
   8 #include <sound/pcm_params.h>
   9 #include <sound/soc.h>
  10 #include <sound/soc-dai.h>
  11
  12 #include "aiu.h"
  13 #include "aiu-fifo.h"
  14
  15 #define AIU_I2S_SOURCE_DESC_MODE_8CH    BIT(0)
  16 #define AIU_I2S_SOURCE_DESC_MODE_24BIT  BIT(5)
  17 #define AIU_I2S_SOURCE_DESC_MODE_32BIT  BIT(9)
  18 #define AIU_I2S_SOURCE_DESC_MODE_SPLIT  BIT(11)
  19 #define AIU_MEM_I2S_MASKS_IRQ_BLOCK     GENMASK(31, 16)
  20 #define AIU_MEM_I2S_CONTROL_MODE_16BIT  BIT(6)
  21 #define AIU_MEM_I2S_BUF_CNTL_INIT       BIT(0)
  22 #define AIU_RST_SOFT_I2S_FAST           BIT(0)
  23
  24 #define AIU_FIFO_I2S_BLOCK              256
  25
  26 static struct snd_pcm_hardware fifo_i2s_pcm = {
  27         .info = (SNDRV_PCM_INFO_INTERLEAVED |
  28                  SNDRV_PCM_INFO_MMAP |
  29                  SNDRV_PCM_INFO_MMAP_VALID |
  30                  SNDRV_PCM_INFO_PAUSE),
  31         .formats = AIU_FORMATS,
  32         .rate_min = 5512,
  33         .rate_max = 192000,
  34         .channels_min = 2,
  35         .channels_max = 8,
  36         .period_bytes_min = AIU_FIFO_I2S_BLOCK,
  37         .period_bytes_max = AIU_FIFO_I2S_BLOCK * USHRT_MAX,
  38         .periods_min = 2,
  39         .periods_max = UINT_MAX,
  40
  41         /* No real justification for this */
  42         .buffer_bytes_max = 1 * 1024 * 1024,
  43 };
  44
  45 static int aiu_fifo_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
  46                                 struct snd_soc_dai *dai)
  47 {
  48         struct snd_soc_component *component = dai->component;
  49         unsigned int val;
  50
  51         switch (cmd) {
  52         case SNDRV_PCM_TRIGGER_START:
  53         case SNDRV_PCM_TRIGGER_RESUME:
  54         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  55                 snd_soc_component_write(component, AIU_RST_SOFT,
  56                                         AIU_RST_SOFT_I2S_FAST);
  57                 snd_soc_component_read(component, AIU_I2S_SYNC, &val);
  58                 break;
  59         }
  60
  61         return aiu_fifo_trigger(substream, cmd, dai);
  62 }
  63
  64 static int aiu_fifo_i2s_prepare(struct snd_pcm_substream *substream,
  65                                 struct snd_soc_dai *dai)
  66 {
  67         struct snd_soc_component *component = dai->component;
  68         int ret;
  69
  70         ret = aiu_fifo_prepare(substream, dai);
  71         if (ret)
  72                 return ret;
  73
  74         snd_soc_component_update_bits(component,
  75                                       AIU_MEM_I2S_BUF_CNTL,
  76                                       AIU_MEM_I2S_BUF_CNTL_INIT,
  77                                       AIU_MEM_I2S_BUF_CNTL_INIT);
  78         snd_soc_component_update_bits(component,
  79                                       AIU_MEM_I2S_BUF_CNTL,
  80                                       AIU_MEM_I2S_BUF_CNTL_INIT, 0);
  81
  82         return 0;
  83 }
  84
  85 static int aiu_fifo_i2s_hw_params(struct snd_pcm_substream *substream,
  86                                   struct snd_pcm_hw_params *params,
  87                                   struct snd_soc_dai *dai)
  88 {
  89         struct snd_soc_component *component = dai->component;
  90         struct aiu_fifo *fifo = dai->playback_dma_data;
  91         unsigned int val;
  92         int ret;
  93
  94         ret = aiu_fifo_hw_params(substream, params, dai);
  95         if (ret)
  96                 return ret;
  97
  98         switch (params_physical_width(params)) {
  99         case 16:
 100                 val = AIU_MEM_I2S_CONTROL_MODE_16BIT;
 101                 break;
 102         case 32:
 103                 val = 0;
 104                 break;
 105         default:
 106                 dev_err(dai->dev, "Unsupported physical width %u\n",
 107                         params_physical_width(params));
 108                 return -EINVAL;
 109         }
 110
 111         snd_soc_component_update_bits(component, AIU_MEM_I2S_CONTROL,
 112                                       AIU_MEM_I2S_CONTROL_MODE_16BIT,
 113                                       val);
 114
 115         /* Setup the irq periodicity */
 116         val = params_period_bytes(params) / fifo->fifo_block;
 117         val = FIELD_PREP(AIU_MEM_I2S_MASKS_IRQ_BLOCK, val);
 118         snd_soc_component_update_bits(component, AIU_MEM_I2S_MASKS,
 119                                       AIU_MEM_I2S_MASKS_IRQ_BLOCK, val);
 120
 121         return 0;
 122 }
 123
 124 const struct snd_soc_dai_ops aiu_fifo_i2s_dai_ops = {
 125         .trigger        = aiu_fifo_i2s_trigger,
 126         .prepare        = aiu_fifo_i2s_prepare,
 127         .hw_params      = aiu_fifo_i2s_hw_params,
 128         .hw_free        = aiu_fifo_hw_free,
 129         .startup        = aiu_fifo_startup,
 130         .shutdown       = aiu_fifo_shutdown,
 131 };
 132
 133 int aiu_fifo_i2s_dai_probe(struct snd_soc_dai *dai)
 134 {
 135         struct snd_soc_component *component = dai->component;
 136         struct aiu *aiu = snd_soc_component_get_drvdata(component);
 137         struct aiu_fifo *fifo;
 138         int ret;
 139
 140         ret = aiu_fifo_dai_probe(dai);
 141         if (ret)
 142                 return ret;
 143
 144         fifo = dai->playback_dma_data;
 145
 146         fifo->pcm = &fifo_i2s_pcm;
 147         fifo->mem_offset = AIU_MEM_I2S_START;
 148         fifo->fifo_block = AIU_FIFO_I2S_BLOCK;
 149         fifo->pclk = aiu->i2s.clks[PCLK].clk;
 150         fifo->irq = aiu->i2s.irq;
 151
 152         return 0;
 153 }