1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek ALSA SoC Audio DAI ADDA Control
5 * Copyright (c) 2021 MediaTek Inc.
6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
7 * Trevor Wu <trevor.wu@mediatek.com>
10 #include <linux/delay.h>
11 #include <linux/regmap.h>
12 #include "mt8195-afe-clk.h"
13 #include "mt8195-afe-common.h"
14 #include "mt8195-reg.h"
16 #define ADDA_DL_GAIN_LOOPBACK 0x1800
17 #define ADDA_HIRES_THRES 48000
22 SUPPLY_SEQ_ADDA_DL_ON,
23 SUPPLY_SEQ_ADDA_MTKAIF_CFG,
24 SUPPLY_SEQ_ADDA_UL_ON,
25 SUPPLY_SEQ_ADDA_AFE_ON,
29 MTK_AFE_ADDA_DL_RATE_8K = 0,
30 MTK_AFE_ADDA_DL_RATE_11K = 1,
31 MTK_AFE_ADDA_DL_RATE_12K = 2,
32 MTK_AFE_ADDA_DL_RATE_16K = 3,
33 MTK_AFE_ADDA_DL_RATE_22K = 4,
34 MTK_AFE_ADDA_DL_RATE_24K = 5,
35 MTK_AFE_ADDA_DL_RATE_32K = 6,
36 MTK_AFE_ADDA_DL_RATE_44K = 7,
37 MTK_AFE_ADDA_DL_RATE_48K = 8,
38 MTK_AFE_ADDA_DL_RATE_96K = 9,
39 MTK_AFE_ADDA_DL_RATE_192K = 10,
43 MTK_AFE_ADDA_UL_RATE_8K = 0,
44 MTK_AFE_ADDA_UL_RATE_16K = 1,
45 MTK_AFE_ADDA_UL_RATE_32K = 2,
46 MTK_AFE_ADDA_UL_RATE_48K = 3,
47 MTK_AFE_ADDA_UL_RATE_96K = 4,
48 MTK_AFE_ADDA_UL_RATE_192K = 5,
62 struct mtk_dai_adda_priv {
66 static unsigned int afe_adda_dl_rate_transform(struct mtk_base_afe *afe,
71 return MTK_AFE_ADDA_DL_RATE_8K;
73 return MTK_AFE_ADDA_DL_RATE_11K;
75 return MTK_AFE_ADDA_DL_RATE_12K;
77 return MTK_AFE_ADDA_DL_RATE_16K;
79 return MTK_AFE_ADDA_DL_RATE_22K;
81 return MTK_AFE_ADDA_DL_RATE_24K;
83 return MTK_AFE_ADDA_DL_RATE_32K;
85 return MTK_AFE_ADDA_DL_RATE_44K;
87 return MTK_AFE_ADDA_DL_RATE_48K;
89 return MTK_AFE_ADDA_DL_RATE_96K;
91 return MTK_AFE_ADDA_DL_RATE_192K;
93 dev_info(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
95 return MTK_AFE_ADDA_DL_RATE_48K;
99 static unsigned int afe_adda_ul_rate_transform(struct mtk_base_afe *afe,
104 return MTK_AFE_ADDA_UL_RATE_8K;
106 return MTK_AFE_ADDA_UL_RATE_16K;
108 return MTK_AFE_ADDA_UL_RATE_32K;
110 return MTK_AFE_ADDA_UL_RATE_48K;
112 return MTK_AFE_ADDA_UL_RATE_96K;
114 return MTK_AFE_ADDA_UL_RATE_192K;
116 dev_info(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
118 return MTK_AFE_ADDA_UL_RATE_48K;
122 static int mt8195_adda_mtkaif_init(struct mtk_base_afe *afe)
124 struct mt8195_afe_private *afe_priv = afe->platform_priv;
125 struct mtkaif_param *param = &afe_priv->mtkaif_params;
128 unsigned int mask = 0;
129 unsigned int val = 0;
131 /* set rx protocol 2 & mtkaif_rxif_clkinv_adc inverse */
132 mask = (MTKAIF_RXIF_CLKINV_ADC | MTKAIF_RXIF_PROTOCOL2);
133 val = (MTKAIF_RXIF_CLKINV_ADC | MTKAIF_RXIF_PROTOCOL2);
135 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0, mask, val);
136 regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIF_CFG0, mask, val);
138 mask = RG_RX_PROTOCOL2;
139 val = RG_RX_PROTOCOL2;
140 regmap_update_bits(afe->regmap, AFE_AUD_PAD_TOP, mask, val);
142 if (!param->mtkaif_calibration_ok) {
143 dev_info(afe->dev, "%s(), calibration fail\n", __func__);
147 /* set delay for ch1, ch2 */
148 if (param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_0] >=
149 param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1]) {
150 delay_data = DELAY_DATA_MISO1;
152 param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_0] -
153 param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1];
155 delay_data = DELAY_DATA_MISO0;
157 param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1] -
158 param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_0];
162 mask = (MTKAIF_RXIF_DELAY_DATA | MTKAIF_RXIF_DELAY_CYCLE_MASK);
163 val |= MTKAIF_RXIF_DELAY_CYCLE(delay_cycle) &
164 MTKAIF_RXIF_DELAY_CYCLE_MASK;
165 val |= delay_data << MTKAIF_RXIF_DELAY_DATA_SHIFT;
166 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG2, mask, val);
168 /* set delay between ch3 and ch2 */
169 if (param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_2] >=
170 param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1]) {
171 delay_data = DELAY_DATA_MISO1;
173 param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_2] -
174 param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1];
176 delay_data = DELAY_DATA_MISO2;
178 param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1] -
179 param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_2];
183 mask = (MTKAIF_RXIF_DELAY_DATA | MTKAIF_RXIF_DELAY_CYCLE_MASK);
184 val |= MTKAIF_RXIF_DELAY_CYCLE(delay_cycle) &
185 MTKAIF_RXIF_DELAY_CYCLE_MASK;
186 val |= delay_data << MTKAIF_RXIF_DELAY_DATA_SHIFT;
187 regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIF_RX_CFG2, mask, val);
192 static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w,
193 struct snd_kcontrol *kcontrol,
196 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
197 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
199 dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
200 __func__, w->name, event);
203 case SND_SOC_DAPM_PRE_PMU:
204 mt8195_adda_mtkaif_init(afe);
213 static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w,
214 struct snd_kcontrol *kcontrol,
217 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
218 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
220 dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
221 __func__, w->name, event);
224 case SND_SOC_DAPM_POST_PMD:
225 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
226 usleep_range(125, 135);
235 static void mtk_adda_ul_mictype(struct mtk_base_afe *afe, int adda, bool dmic)
237 unsigned int reg = 0;
238 unsigned int mask = 0;
239 unsigned int val = 0;
243 reg = AFE_ADDA_UL_SRC_CON0;
246 reg = AFE_ADDA6_UL_SRC_CON0;
249 dev_info(afe->dev, "%s(), wrong parameter\n", __func__);
253 mask = (UL_SDM3_LEVEL_CTL | UL_MODE_3P25M_CH1_CTL |
254 UL_MODE_3P25M_CH2_CTL);
256 /* turn on dmic, ch1, ch2 */
260 regmap_update_bits(afe->regmap, reg, mask, val);
263 static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
264 struct snd_kcontrol *kcontrol,
267 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
268 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
269 struct mt8195_afe_private *afe_priv = afe->platform_priv;
270 struct mtkaif_param *param = &afe_priv->mtkaif_params;
272 dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
273 __func__, w->name, event);
276 case SND_SOC_DAPM_PRE_PMU:
277 mtk_adda_ul_mictype(afe, MTK_AFE_ADDA, param->mtkaif_dmic_on);
279 case SND_SOC_DAPM_POST_PMD:
280 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
281 usleep_range(125, 135);
290 static int mtk_adda6_ul_event(struct snd_soc_dapm_widget *w,
291 struct snd_kcontrol *kcontrol,
294 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
295 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
296 struct mt8195_afe_private *afe_priv = afe->platform_priv;
297 struct mtkaif_param *param = &afe_priv->mtkaif_params;
300 dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
301 __func__, w->name, event);
304 case SND_SOC_DAPM_PRE_PMU:
305 mtk_adda_ul_mictype(afe, MTK_AFE_ADDA6, param->mtkaif_dmic_on);
307 val = (param->mtkaif_adda6_only ?
308 ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE : 0);
310 regmap_update_bits(afe->regmap,
311 AFE_ADDA_MTKAIF_SYNCWORD_CFG,
312 ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE,
315 case SND_SOC_DAPM_POST_PMD:
316 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
317 usleep_range(125, 135);
326 static int mtk_audio_hires_event(struct snd_soc_dapm_widget *w,
327 struct snd_kcontrol *kcontrol,
330 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
331 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
332 struct mt8195_afe_private *afe_priv = afe->platform_priv;
333 struct clk *clk = afe_priv->clk[MT8195_CLK_TOP_AUDIO_H_SEL];
334 struct clk *clk_parent;
336 dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
337 __func__, w->name, event);
340 case SND_SOC_DAPM_PRE_PMU:
341 clk_parent = afe_priv->clk[MT8195_CLK_TOP_APLL1];
343 case SND_SOC_DAPM_POST_PMD:
344 clk_parent = afe_priv->clk[MT8195_CLK_XTAL_26M];
349 mt8195_afe_set_clk_parent(afe, clk, clk_parent);
354 static struct mtk_dai_adda_priv *get_adda_priv_by_name(struct mtk_base_afe *afe,
357 struct mt8195_afe_private *afe_priv = afe->platform_priv;
360 if (strstr(name, "aud_adc_hires"))
361 dai_id = MT8195_AFE_IO_UL_SRC1;
362 else if (strstr(name, "aud_adda6_adc_hires"))
363 dai_id = MT8195_AFE_IO_UL_SRC2;
364 else if (strstr(name, "aud_dac_hires"))
365 dai_id = MT8195_AFE_IO_DL_SRC;
369 return afe_priv->dai_priv[dai_id];
372 static int mtk_afe_adda_hires_connect(struct snd_soc_dapm_widget *source,
373 struct snd_soc_dapm_widget *sink)
375 struct snd_soc_dapm_widget *w = source;
376 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
377 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
378 struct mtk_dai_adda_priv *adda_priv;
380 adda_priv = get_adda_priv_by_name(afe, w->name);
383 dev_info(afe->dev, "adda_priv == NULL");
387 return (adda_priv->hires_required) ? 1 : 0;
390 static const struct snd_kcontrol_new mtk_dai_adda_o176_mix[] = {
391 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN176, 0, 1, 0),
392 SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN176, 2, 1, 0),
393 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN176, 20, 1, 0),
394 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN176, 22, 1, 0),
395 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN176_2, 6, 1, 0),
398 static const struct snd_kcontrol_new mtk_dai_adda_o177_mix[] = {
399 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN177, 1, 1, 0),
400 SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN177, 3, 1, 0),
401 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN177, 21, 1, 0),
402 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN177, 23, 1, 0),
403 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN177_2, 7, 1, 0),
406 static const char * const adda_dlgain_mux_map[] = {
410 static SOC_ENUM_SINGLE_DECL(adda_dlgain_mux_map_enum,
412 adda_dlgain_mux_map);
414 static const struct snd_kcontrol_new adda_dlgain_mux_control =
415 SOC_DAPM_ENUM("DL_GAIN_MUX", adda_dlgain_mux_map_enum);
417 static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
418 SND_SOC_DAPM_MIXER("I168", SND_SOC_NOPM, 0, 0, NULL, 0),
419 SND_SOC_DAPM_MIXER("I169", SND_SOC_NOPM, 0, 0, NULL, 0),
420 SND_SOC_DAPM_MIXER("I170", SND_SOC_NOPM, 0, 0, NULL, 0),
421 SND_SOC_DAPM_MIXER("I171", SND_SOC_NOPM, 0, 0, NULL, 0),
423 SND_SOC_DAPM_MIXER("O176", SND_SOC_NOPM, 0, 0,
424 mtk_dai_adda_o176_mix,
425 ARRAY_SIZE(mtk_dai_adda_o176_mix)),
426 SND_SOC_DAPM_MIXER("O177", SND_SOC_NOPM, 0, 0,
427 mtk_dai_adda_o177_mix,
428 ARRAY_SIZE(mtk_dai_adda_o177_mix)),
430 SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
432 ADDA_AFE_ON_SHIFT, 0,
436 SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
437 AFE_ADDA_DL_SRC2_CON0,
438 DL_2_SRC_ON_TMP_CTRL_PRE_SHIFT, 0,
440 SND_SOC_DAPM_POST_PMD),
442 SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
443 AFE_ADDA_UL_SRC_CON0,
444 UL_SRC_ON_TMP_CTL_SHIFT, 0,
446 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
448 SND_SOC_DAPM_SUPPLY_S("ADDA6 Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
449 AFE_ADDA6_UL_SRC_CON0,
450 UL_SRC_ON_TMP_CTL_SHIFT, 0,
452 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
454 SND_SOC_DAPM_SUPPLY_S("AUDIO_HIRES", SUPPLY_SEQ_CLOCK_SEL,
457 mtk_audio_hires_event,
458 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
460 SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG,
463 mtk_adda_mtkaif_cfg_event,
464 SND_SOC_DAPM_PRE_PMU),
466 SND_SOC_DAPM_MUX("DL_GAIN_MUX", SND_SOC_NOPM, 0, 0,
467 &adda_dlgain_mux_control),
469 SND_SOC_DAPM_PGA("DL_GAIN", AFE_ADDA_DL_SRC2_CON0,
470 DL_2_GAIN_ON_CTL_PRE_SHIFT, 0, NULL, 0),
472 SND_SOC_DAPM_INPUT("ADDA_INPUT"),
473 SND_SOC_DAPM_OUTPUT("ADDA_OUTPUT"),
475 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac"),
476 SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc"),
477 SND_SOC_DAPM_CLOCK_SUPPLY("aud_adda6_adc"),
478 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_hires"),
479 SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_hires"),
480 SND_SOC_DAPM_CLOCK_SUPPLY("aud_adda6_adc_hires"),
483 static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
484 {"ADDA Capture", NULL, "ADDA Enable"},
485 {"ADDA Capture", NULL, "ADDA Capture Enable"},
486 {"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"},
487 {"ADDA Capture", NULL, "aud_adc"},
488 {"ADDA Capture", NULL, "aud_adc_hires", mtk_afe_adda_hires_connect},
489 {"aud_adc_hires", NULL, "AUDIO_HIRES"},
491 {"ADDA6 Capture", NULL, "ADDA Enable"},
492 {"ADDA6 Capture", NULL, "ADDA6 Capture Enable"},
493 {"ADDA6 Capture", NULL, "ADDA_MTKAIF_CFG"},
494 {"ADDA6 Capture", NULL, "aud_adda6_adc"},
495 {"ADDA6 Capture", NULL, "aud_adda6_adc_hires",
496 mtk_afe_adda_hires_connect},
497 {"aud_adda6_adc_hires", NULL, "AUDIO_HIRES"},
499 {"I168", NULL, "ADDA Capture"},
500 {"I169", NULL, "ADDA Capture"},
501 {"I170", NULL, "ADDA6 Capture"},
502 {"I171", NULL, "ADDA6 Capture"},
504 {"ADDA Playback", NULL, "ADDA Enable"},
505 {"ADDA Playback", NULL, "ADDA Playback Enable"},
506 {"ADDA Playback", NULL, "aud_dac"},
507 {"ADDA Playback", NULL, "aud_dac_hires", mtk_afe_adda_hires_connect},
508 {"aud_dac_hires", NULL, "AUDIO_HIRES"},
510 {"DL_GAIN", NULL, "O176"},
511 {"DL_GAIN", NULL, "O177"},
513 {"DL_GAIN_MUX", "Bypass", "O176"},
514 {"DL_GAIN_MUX", "Bypass", "O177"},
515 {"DL_GAIN_MUX", "Connect", "DL_GAIN"},
517 {"ADDA Playback", NULL, "DL_GAIN_MUX"},
519 {"O176", "I000 Switch", "I000"},
520 {"O177", "I001 Switch", "I001"},
522 {"O176", "I002 Switch", "I002"},
523 {"O177", "I003 Switch", "I003"},
525 {"O176", "I020 Switch", "I020"},
526 {"O177", "I021 Switch", "I021"},
528 {"O176", "I022 Switch", "I022"},
529 {"O177", "I023 Switch", "I023"},
531 {"O176", "I070 Switch", "I070"},
532 {"O177", "I071 Switch", "I071"},
534 {"ADDA Capture", NULL, "ADDA_INPUT"},
535 {"ADDA6 Capture", NULL, "ADDA_INPUT"},
536 {"ADDA_OUTPUT", NULL, "ADDA Playback"},
539 static int mt8195_adda_dl_gain_put(struct snd_kcontrol *kcontrol,
540 struct snd_ctl_elem_value *ucontrol)
542 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
543 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
544 unsigned int reg = AFE_ADDA_DL_SRC2_CON1;
545 unsigned int mask = DL_2_GAIN_CTL_PRE_MASK;
546 unsigned int value = (unsigned int)(ucontrol->value.integer.value[0]);
548 regmap_update_bits(afe->regmap, reg, mask, DL_2_GAIN_CTL_PRE(value));
552 static int mt8195_adda_dl_gain_get(struct snd_kcontrol *kcontrol,
553 struct snd_ctl_elem_value *ucontrol)
555 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
556 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
557 unsigned int reg = AFE_ADDA_DL_SRC2_CON1;
558 unsigned int mask = DL_2_GAIN_CTL_PRE_MASK;
559 unsigned int value = 0;
561 regmap_read(afe->regmap, reg, &value);
563 ucontrol->value.integer.value[0] = ((value & mask) >>
564 DL_2_GAIN_CTL_PRE_SHIFT);
568 static int mt8195_adda6_only_get(struct snd_kcontrol *kcontrol,
569 struct snd_ctl_elem_value *ucontrol)
571 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
572 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
573 struct mt8195_afe_private *afe_priv = afe->platform_priv;
574 struct mtkaif_param *param = &afe_priv->mtkaif_params;
576 ucontrol->value.integer.value[0] = param->mtkaif_adda6_only;
580 static int mt8195_adda6_only_set(struct snd_kcontrol *kcontrol,
581 struct snd_ctl_elem_value *ucontrol)
583 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
584 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
585 struct mt8195_afe_private *afe_priv = afe->platform_priv;
586 struct mtkaif_param *param = &afe_priv->mtkaif_params;
587 int mtkaif_adda6_only;
589 mtkaif_adda6_only = ucontrol->value.integer.value[0];
591 dev_info(afe->dev, "%s(), kcontrol name %s, mtkaif_adda6_only %d\n",
592 __func__, kcontrol->id.name, mtkaif_adda6_only);
594 param->mtkaif_adda6_only = mtkaif_adda6_only;
599 static int mt8195_adda_dmic_get(struct snd_kcontrol *kcontrol,
600 struct snd_ctl_elem_value *ucontrol)
602 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
603 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
604 struct mt8195_afe_private *afe_priv = afe->platform_priv;
605 struct mtkaif_param *param = &afe_priv->mtkaif_params;
607 ucontrol->value.integer.value[0] = param->mtkaif_dmic_on;
611 static int mt8195_adda_dmic_set(struct snd_kcontrol *kcontrol,
612 struct snd_ctl_elem_value *ucontrol)
614 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
615 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
616 struct mt8195_afe_private *afe_priv = afe->platform_priv;
617 struct mtkaif_param *param = &afe_priv->mtkaif_params;
620 dmic_on = ucontrol->value.integer.value[0];
622 dev_dbg(afe->dev, "%s(), kcontrol name %s, dmic_on %d\n",
623 __func__, kcontrol->id.name, dmic_on);
625 param->mtkaif_dmic_on = dmic_on;
629 static const struct snd_kcontrol_new mtk_dai_adda_controls[] = {
630 SOC_SINGLE_EXT("ADDA_DL_Gain", SND_SOC_NOPM, 0, 65535, 0,
631 mt8195_adda_dl_gain_get, mt8195_adda_dl_gain_put),
632 SOC_SINGLE_BOOL_EXT("MTKAIF_DMIC", 0,
633 mt8195_adda_dmic_get, mt8195_adda_dmic_set),
634 SOC_SINGLE_BOOL_EXT("MTKAIF_ADDA6_ONLY", 0,
635 mt8195_adda6_only_get,
636 mt8195_adda6_only_set),
639 static int mtk_dai_da_configure(struct mtk_base_afe *afe,
640 unsigned int rate, int id)
642 unsigned int val = 0;
643 unsigned int mask = 0;
645 /* set sampling rate */
646 mask |= DL_2_INPUT_MODE_CTL_MASK;
647 val |= DL_2_INPUT_MODE_CTL(afe_adda_dl_rate_transform(afe, rate));
649 /* turn off saturation */
650 mask |= DL_2_CH1_SATURATION_EN_CTL;
651 mask |= DL_2_CH2_SATURATION_EN_CTL;
653 /* turn off mute function */
654 mask |= DL_2_MUTE_CH1_OFF_CTL_PRE;
655 mask |= DL_2_MUTE_CH2_OFF_CTL_PRE;
656 val |= DL_2_MUTE_CH1_OFF_CTL_PRE;
657 val |= DL_2_MUTE_CH2_OFF_CTL_PRE;
659 /* set voice input data if input sample rate is 8k or 16k */
660 mask |= DL_2_VOICE_MODE_CTL_PRE;
661 if (rate == 8000 || rate == 16000)
662 val |= DL_2_VOICE_MODE_CTL_PRE;
664 regmap_update_bits(afe->regmap, AFE_ADDA_DL_SRC2_CON0, mask, val);
670 mask |= DL_USE_NEW_2ND_SDM;
671 val |= DL_USE_NEW_2ND_SDM;
672 regmap_update_bits(afe->regmap, AFE_ADDA_DL_SDM_DCCOMP_CON, mask, val);
677 static int mtk_dai_ad_configure(struct mtk_base_afe *afe,
678 unsigned int rate, int id)
680 unsigned int val = 0;
681 unsigned int mask = 0;
683 mask |= UL_VOICE_MODE_CTL_MASK;
684 val |= UL_VOICE_MODE_CTL(afe_adda_ul_rate_transform(afe, rate));
687 case MT8195_AFE_IO_UL_SRC1:
688 regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
691 case MT8195_AFE_IO_UL_SRC2:
692 regmap_update_bits(afe->regmap, AFE_ADDA6_UL_SRC_CON0,
701 static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
702 struct snd_pcm_hw_params *params,
703 struct snd_soc_dai *dai)
705 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
706 struct mt8195_afe_private *afe_priv = afe->platform_priv;
707 struct mtk_dai_adda_priv *adda_priv = afe_priv->dai_priv[dai->id];
708 unsigned int rate = params_rate(params);
712 dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
713 __func__, id, substream->stream, rate);
715 if (rate > ADDA_HIRES_THRES)
716 adda_priv->hires_required = 1;
718 adda_priv->hires_required = 0;
720 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
721 ret = mtk_dai_da_configure(afe, rate, id);
723 ret = mtk_dai_ad_configure(afe, rate, id);
728 static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
729 .hw_params = mtk_dai_adda_hw_params,
733 #define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\
734 SNDRV_PCM_RATE_96000 |\
735 SNDRV_PCM_RATE_192000)
737 #define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
738 SNDRV_PCM_RATE_16000 |\
739 SNDRV_PCM_RATE_32000 |\
740 SNDRV_PCM_RATE_48000 |\
741 SNDRV_PCM_RATE_96000 |\
742 SNDRV_PCM_RATE_192000)
744 #define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
745 SNDRV_PCM_FMTBIT_S24_LE |\
746 SNDRV_PCM_FMTBIT_S32_LE)
748 static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
751 .id = MT8195_AFE_IO_DL_SRC,
753 .stream_name = "ADDA Playback",
756 .rates = MTK_ADDA_PLAYBACK_RATES,
757 .formats = MTK_ADDA_FORMATS,
759 .ops = &mtk_dai_adda_ops,
763 .id = MT8195_AFE_IO_UL_SRC1,
765 .stream_name = "ADDA Capture",
768 .rates = MTK_ADDA_CAPTURE_RATES,
769 .formats = MTK_ADDA_FORMATS,
771 .ops = &mtk_dai_adda_ops,
775 .id = MT8195_AFE_IO_UL_SRC2,
777 .stream_name = "ADDA6 Capture",
780 .rates = MTK_ADDA_CAPTURE_RATES,
781 .formats = MTK_ADDA_FORMATS,
783 .ops = &mtk_dai_adda_ops,
787 static int init_adda_priv_data(struct mtk_base_afe *afe)
789 struct mt8195_afe_private *afe_priv = afe->platform_priv;
790 struct mtk_dai_adda_priv *adda_priv;
791 static const int adda_dai_list[] = {
792 MT8195_AFE_IO_DL_SRC,
793 MT8195_AFE_IO_UL_SRC1,
794 MT8195_AFE_IO_UL_SRC2
798 for (i = 0; i < ARRAY_SIZE(adda_dai_list); i++) {
799 adda_priv = devm_kzalloc(afe->dev,
800 sizeof(struct mtk_dai_adda_priv),
805 afe_priv->dai_priv[adda_dai_list[i]] = adda_priv;
811 int mt8195_dai_adda_register(struct mtk_base_afe *afe)
813 struct mtk_base_afe_dai *dai;
815 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
819 list_add(&dai->list, &afe->sub_dais);
821 dai->dai_drivers = mtk_dai_adda_driver;
822 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
824 dai->dapm_widgets = mtk_dai_adda_widgets;
825 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
826 dai->dapm_routes = mtk_dai_adda_routes;
827 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
828 dai->controls = mtk_dai_adda_controls;
829 dai->num_controls = ARRAY_SIZE(mtk_dai_adda_controls);
831 return init_adda_priv_data(afe);