sound/soc/mediatek/mt8186/mt8186-dai-adda.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // MediaTek ALSA SoC Audio DAI ADDA Control
   4 //
   5 // Copyright (c) 2022 MediaTek Inc.
   6 // Author: Jiaxin Yu <jiaxin.yu@mediatek.com>
   7
   8 #include <linux/regmap.h>
   9 #include <linux/delay.h>
  10 #include "mt8186-afe-clk.h"
  11 #include "mt8186-afe-common.h"
  12 #include "mt8186-afe-gpio.h"
  13 #include "mt8186-interconnection.h"
  14
  15 enum {
  16         UL_IIR_SW = 0,
  17         UL_IIR_5HZ,
  18         UL_IIR_10HZ,
  19         UL_IIR_25HZ,
  20         UL_IIR_50HZ,
  21         UL_IIR_75HZ,
  22 };
  23
  24 enum {
  25         AUDIO_SDM_LEVEL_MUTE = 0,
  26         AUDIO_SDM_LEVEL_NORMAL = 0x1d,
  27         /* if you change level normal */
  28         /* you need to change formula of hp impedance and dc trim too */
  29 };
  30
  31 enum {
  32         AUDIO_SDM_2ND = 0,
  33         AUDIO_SDM_3RD,
  34 };
  35
  36 enum {
  37         DELAY_DATA_MISO1 = 0,
  38         DELAY_DATA_MISO2,
  39 };
  40
  41 enum {
  42         MTK_AFE_ADDA_DL_RATE_8K = 0,
  43         MTK_AFE_ADDA_DL_RATE_11K = 1,
  44         MTK_AFE_ADDA_DL_RATE_12K = 2,
  45         MTK_AFE_ADDA_DL_RATE_16K = 3,
  46         MTK_AFE_ADDA_DL_RATE_22K = 4,
  47         MTK_AFE_ADDA_DL_RATE_24K = 5,
  48         MTK_AFE_ADDA_DL_RATE_32K = 6,
  49         MTK_AFE_ADDA_DL_RATE_44K = 7,
  50         MTK_AFE_ADDA_DL_RATE_48K = 8,
  51         MTK_AFE_ADDA_DL_RATE_96K = 9,
  52         MTK_AFE_ADDA_DL_RATE_192K = 10,
  53 };
  54
  55 enum {
  56         MTK_AFE_ADDA_UL_RATE_8K = 0,
  57         MTK_AFE_ADDA_UL_RATE_16K = 1,
  58         MTK_AFE_ADDA_UL_RATE_32K = 2,
  59         MTK_AFE_ADDA_UL_RATE_48K = 3,
  60         MTK_AFE_ADDA_UL_RATE_96K = 4,
  61         MTK_AFE_ADDA_UL_RATE_192K = 5,
  62         MTK_AFE_ADDA_UL_RATE_48K_HD = 6,
  63 };
  64
  65 #define SDM_AUTO_RESET_THRESHOLD 0x190000
  66
  67 struct mtk_afe_adda_priv {
  68         int dl_rate;
  69         int ul_rate;
  70 };
  71
  72 static struct mtk_afe_adda_priv *get_adda_priv_by_name(struct mtk_base_afe *afe,
  73                                                        const char *name)
  74 {
  75         struct mt8186_afe_private *afe_priv = afe->platform_priv;
  76         int dai_id;
  77
  78         if (strncmp(name, "aud_dac", 7) == 0 || strncmp(name, "aud_adc", 7) == 0)
  79                 dai_id = MT8186_DAI_ADDA;
  80         else
  81                 return NULL;
  82
  83         return afe_priv->dai_priv[dai_id];
  84 }
  85
  86 static unsigned int adda_dl_rate_transform(struct mtk_base_afe *afe,
  87                                            unsigned int rate)
  88 {
  89         switch (rate) {
  90         case 8000:
  91                 return MTK_AFE_ADDA_DL_RATE_8K;
  92         case 11025:
  93                 return MTK_AFE_ADDA_DL_RATE_11K;
  94         case 12000:
  95                 return MTK_AFE_ADDA_DL_RATE_12K;
  96         case 16000:
  97                 return MTK_AFE_ADDA_DL_RATE_16K;
  98         case 22050:
  99                 return MTK_AFE_ADDA_DL_RATE_22K;
 100         case 24000:
 101                 return MTK_AFE_ADDA_DL_RATE_24K;
 102         case 32000:
 103                 return MTK_AFE_ADDA_DL_RATE_32K;
 104         case 44100:
 105                 return MTK_AFE_ADDA_DL_RATE_44K;
 106         case 48000:
 107                 return MTK_AFE_ADDA_DL_RATE_48K;
 108         case 96000:
 109                 return MTK_AFE_ADDA_DL_RATE_96K;
 110         case 192000:
 111                 return MTK_AFE_ADDA_DL_RATE_192K;
 112         default:
 113                 dev_info(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
 114                          __func__, rate);
 115         }
 116
 117         return MTK_AFE_ADDA_DL_RATE_48K;
 118 }
 119
 120 static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe,
 121                                            unsigned int rate)
 122 {
 123         switch (rate) {
 124         case 8000:
 125                 return MTK_AFE_ADDA_UL_RATE_8K;
 126         case 16000:
 127                 return MTK_AFE_ADDA_UL_RATE_16K;
 128         case 32000:
 129                 return MTK_AFE_ADDA_UL_RATE_32K;
 130         case 48000:
 131                 return MTK_AFE_ADDA_UL_RATE_48K;
 132         case 96000:
 133                 return MTK_AFE_ADDA_UL_RATE_96K;
 134         case 192000:
 135                 return MTK_AFE_ADDA_UL_RATE_192K;
 136         default:
 137                 dev_info(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
 138                          __func__, rate);
 139         }
 140
 141         return MTK_AFE_ADDA_UL_RATE_48K;
 142 }
 143
 144 /* dai component */
 145 static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = {
 146         SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN3, I_DL1_CH1, 1, 0),
 147         SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN3, I_DL12_CH1, 1, 0),
 148         SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN3, I_DL2_CH1, 1, 0),
 149         SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN3, I_DL3_CH1, 1, 0),
 150         SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN3_1, I_DL4_CH1, 1, 0),
 151         SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN3_1, I_DL5_CH1, 1, 0),
 152         SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN3_1, I_DL6_CH1, 1, 0),
 153         SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1 Switch", AFE_CONN3_1, I_DL8_CH1, 1, 0),
 154         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN3,
 155                                     I_ADDA_UL_CH2, 1, 0),
 156         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN3,
 157                                     I_ADDA_UL_CH1, 1, 0),
 158         SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1 Switch", AFE_CONN3,
 159                                     I_GAIN1_OUT_CH1, 1, 0),
 160         SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1 Switch", AFE_CONN3,
 161                                     I_PCM_1_CAP_CH1, 1, 0),
 162         SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1 Switch", AFE_CONN3,
 163                                     I_PCM_2_CAP_CH1, 1, 0),
 164         SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1 Switch", AFE_CONN3_1,
 165                                     I_SRC_1_OUT_CH1, 1, 0),
 166         SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH1 Switch", AFE_CONN3_1,
 167                                     I_SRC_2_OUT_CH1, 1, 0),
 168 };
 169
 170 static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = {
 171         SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN4, I_DL1_CH1, 1, 0),
 172         SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN4, I_DL1_CH2, 1, 0),
 173         SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN4, I_DL12_CH2, 1, 0),
 174         SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN4, I_DL2_CH1, 1, 0),
 175         SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN4, I_DL2_CH2, 1, 0),
 176         SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN4, I_DL3_CH1, 1, 0),
 177         SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN4, I_DL3_CH2, 1, 0),
 178         SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN4_1, I_DL4_CH2, 1, 0),
 179         SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN4_1, I_DL5_CH2, 1, 0),
 180         SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2 Switch", AFE_CONN4_1, I_DL6_CH2, 1, 0),
 181         SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2 Switch", AFE_CONN4_1, I_DL8_CH2, 1, 0),
 182         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN4,
 183                                     I_ADDA_UL_CH2, 1, 0),
 184         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN4,
 185                                     I_ADDA_UL_CH1, 1, 0),
 186         SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2 Switch", AFE_CONN4,
 187                                     I_GAIN1_OUT_CH2, 1, 0),
 188         SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2 Switch", AFE_CONN4,
 189                                     I_PCM_1_CAP_CH2, 1, 0),
 190         SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2 Switch", AFE_CONN4,
 191                                     I_PCM_2_CAP_CH2, 1, 0),
 192         SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2 Switch", AFE_CONN4_1,
 193                                     I_SRC_1_OUT_CH2, 1, 0),
 194         SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH2 Switch", AFE_CONN4_1,
 195                                     I_SRC_2_OUT_CH2, 1, 0),
 196 };
 197
 198 enum {
 199         SUPPLY_SEQ_ADDA_AFE_ON,
 200         SUPPLY_SEQ_ADDA_DL_ON,
 201         SUPPLY_SEQ_ADDA_AUD_PAD_TOP,
 202         SUPPLY_SEQ_ADDA_MTKAIF_CFG,
 203         SUPPLY_SEQ_ADDA_FIFO,
 204         SUPPLY_SEQ_ADDA_AP_DMIC,
 205         SUPPLY_SEQ_ADDA_UL_ON,
 206 };
 207
 208 static int mtk_adda_ul_src_dmic(struct mtk_base_afe *afe, int id)
 209 {
 210         unsigned int reg;
 211
 212         switch (id) {
 213         case MT8186_DAI_ADDA:
 214         case MT8186_DAI_AP_DMIC:
 215                 reg = AFE_ADDA_UL_SRC_CON0;
 216                 break;
 217         default:
 218                 return -EINVAL;
 219         }
 220
 221         /* dmic mode, 3.25M*/
 222         regmap_update_bits(afe->regmap, reg,
 223                            DIGMIC_3P25M_1P625M_SEL_MASK_SFT, 0);
 224         regmap_update_bits(afe->regmap, reg,
 225                            DMIC_LOW_POWER_CTL_MASK_SFT, 0);
 226
 227         /* turn on dmic, ch1, ch2 */
 228         regmap_update_bits(afe->regmap, reg,
 229                            UL_SDM_3_LEVEL_MASK_SFT,
 230                            BIT(UL_SDM_3_LEVEL_SFT));
 231         regmap_update_bits(afe->regmap, reg,
 232                            UL_MODE_3P25M_CH1_CTL_MASK_SFT,
 233                            BIT(UL_MODE_3P25M_CH1_CTL_SFT));
 234         regmap_update_bits(afe->regmap, reg,
 235                            UL_MODE_3P25M_CH2_CTL_MASK_SFT,
 236                            BIT(UL_MODE_3P25M_CH2_CTL_SFT));
 237
 238         return 0;
 239 }
 240
 241 static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
 242                              struct snd_kcontrol *kcontrol,
 243                              int event)
 244 {
 245         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 246         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 247         struct mt8186_afe_private *afe_priv = afe->platform_priv;
 248         int mtkaif_dmic = afe_priv->mtkaif_dmic;
 249
 250         dev_dbg(afe->dev, "%s(), name %s, event 0x%x, mtkaif_dmic %d\n",
 251                 __func__, w->name, event, mtkaif_dmic);
 252
 253         switch (event) {
 254         case SND_SOC_DAPM_PRE_PMU:
 255                 mt8186_afe_gpio_request(afe->dev, true, MT8186_DAI_ADDA, 1);
 256
 257                 /* update setting to dmic */
 258                 if (mtkaif_dmic) {
 259                         /* mtkaif_rxif_data_mode = 1, dmic */
 260                         regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
 261                                            0x1, 0x1);
 262
 263                         /* dmic mode, 3.25M*/
 264                         regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
 265                                            MTKAIF_RXIF_VOICE_MODE_MASK_SFT,
 266                                            0x0);
 267                         mtk_adda_ul_src_dmic(afe, MT8186_DAI_ADDA);
 268                 }
 269                 break;
 270         case SND_SOC_DAPM_POST_PMD:
 271                 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
 272                 usleep_range(125, 135);
 273                 mt8186_afe_gpio_request(afe->dev, false, MT8186_DAI_ADDA, 1);
 274
 275                 /* reset dmic */
 276                 afe_priv->mtkaif_dmic = 0;
 277                 break;
 278         default:
 279                 break;
 280         }
 281
 282         return 0;
 283 }
 284
 285 static int mtk_adda_pad_top_event(struct snd_soc_dapm_widget *w,
 286                                   struct snd_kcontrol *kcontrol,
 287                                   int event)
 288 {
 289         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 290         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 291         struct mt8186_afe_private *afe_priv = afe->platform_priv;
 292
 293         switch (event) {
 294         case SND_SOC_DAPM_PRE_PMU:
 295                 if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2)
 296                         regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x39);
 297                 else
 298                         regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x31);
 299                 break;
 300         default:
 301                 break;
 302         }
 303
 304         return 0;
 305 }
 306
 307 static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w,
 308                                      struct snd_kcontrol *kcontrol,
 309                                      int event)
 310 {
 311         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 312         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 313         struct mt8186_afe_private *afe_priv = afe->platform_priv;
 314         int delay_data;
 315         int delay_cycle;
 316
 317         switch (event) {
 318         case SND_SOC_DAPM_PRE_PMU:
 319                 if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2) {
 320                         /* set protocol 2 */
 321                         regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x10000);
 322                         /* mtkaif_rxif_clkinv_adc inverse */
 323                         regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
 324                                            MTKAIF_RXIF_CLKINV_ADC_MASK_SFT,
 325                                            BIT(MTKAIF_RXIF_CLKINV_ADC_SFT));
 326
 327                         if (strcmp(w->name, "ADDA_MTKAIF_CFG") == 0) {
 328                                 if (afe_priv->mtkaif_chosen_phase[0] < 0 &&
 329                                     afe_priv->mtkaif_chosen_phase[1] < 0) {
 330                                         dev_err(afe->dev,
 331                                                 "%s(), calib fail mtkaif_chosen_phase[0/1]:%d/%d\n",
 332                                                 __func__,
 333                                                 afe_priv->mtkaif_chosen_phase[0],
 334                                                 afe_priv->mtkaif_chosen_phase[1]);
 335                                         break;
 336                                 }
 337
 338                                 if (afe_priv->mtkaif_chosen_phase[0] < 0 ||
 339                                     afe_priv->mtkaif_chosen_phase[1] < 0) {
 340                                         dev_err(afe->dev,
 341                                                 "%s(), skip delay setting mtkaif_chosen_phase[0/1]:%d/%d\n",
 342                                                 __func__,
 343                                                 afe_priv->mtkaif_chosen_phase[0],
 344                                                 afe_priv->mtkaif_chosen_phase[1]);
 345                                         break;
 346                                 }
 347                         }
 348
 349                         /* set delay for ch12 */
 350                         if (afe_priv->mtkaif_phase_cycle[0] >=
 351                             afe_priv->mtkaif_phase_cycle[1]) {
 352                                 delay_data = DELAY_DATA_MISO1;
 353                                 delay_cycle = afe_priv->mtkaif_phase_cycle[0] -
 354                                               afe_priv->mtkaif_phase_cycle[1];
 355                         } else {
 356                                 delay_data = DELAY_DATA_MISO2;
 357                                 delay_cycle = afe_priv->mtkaif_phase_cycle[1] -
 358                                               afe_priv->mtkaif_phase_cycle[0];
 359                         }
 360
 361                         regmap_update_bits(afe->regmap,
 362                                            AFE_ADDA_MTKAIF_RX_CFG2,
 363                                            MTKAIF_RXIF_DELAY_DATA_MASK_SFT,
 364                                            delay_data <<
 365                                            MTKAIF_RXIF_DELAY_DATA_SFT);
 366
 367                         regmap_update_bits(afe->regmap,
 368                                            AFE_ADDA_MTKAIF_RX_CFG2,
 369                                            MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT,
 370                                            delay_cycle <<
 371                                            MTKAIF_RXIF_DELAY_CYCLE_SFT);
 372
 373                 } else if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2) {
 374                         regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x10000);
 375                 } else {
 376                         regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0);
 377                 }
 378
 379                 break;
 380         default:
 381                 break;
 382         }
 383
 384         return 0;
 385 }
 386
 387 static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w,
 388                              struct snd_kcontrol *kcontrol,
 389                              int event)
 390 {
 391         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 392         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 393
 394         dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
 395                 __func__, w->name, event);
 396
 397         switch (event) {
 398         case SND_SOC_DAPM_PRE_PMU:
 399                 mt8186_afe_gpio_request(afe->dev, true, MT8186_DAI_ADDA, 0);
 400                 break;
 401         case SND_SOC_DAPM_POST_PMD:
 402                 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
 403                 usleep_range(125, 135);
 404                 mt8186_afe_gpio_request(afe->dev, false, MT8186_DAI_ADDA, 0);
 405                 break;
 406         default:
 407                 break;
 408         }
 409
 410         return 0;
 411 }
 412
 413 static int mt8186_adda_dmic_get(struct snd_kcontrol *kcontrol,
 414                                 struct snd_ctl_elem_value *ucontrol)
 415 {
 416         struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
 417         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 418         struct mt8186_afe_private *afe_priv = afe->platform_priv;
 419
 420         ucontrol->value.integer.value[0] = afe_priv->mtkaif_dmic;
 421
 422         return 0;
 423 }
 424
 425 static int mt8186_adda_dmic_set(struct snd_kcontrol *kcontrol,
 426                                 struct snd_ctl_elem_value *ucontrol)
 427 {
 428         struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
 429         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 430         struct mt8186_afe_private *afe_priv = afe->platform_priv;
 431         int dmic_on;
 432
 433         dmic_on = ucontrol->value.integer.value[0];
 434
 435         dev_dbg(afe->dev, "%s(), kcontrol name %s, dmic_on %d\n",
 436                 __func__, kcontrol->id.name, dmic_on);
 437
 438         if (afe_priv->mtkaif_dmic == dmic_on)
 439                 return 0;
 440
 441         afe_priv->mtkaif_dmic = dmic_on;
 442
 443         return 1;
 444 }
 445
 446 static const struct snd_kcontrol_new mtk_adda_controls[] = {
 447         SOC_SINGLE("ADDA_DL_GAIN", AFE_ADDA_DL_SRC2_CON1,
 448                    DL_2_GAIN_CTL_PRE_SFT, DL_2_GAIN_CTL_PRE_MASK, 0),
 449         SOC_SINGLE_BOOL_EXT("MTKAIF_DMIC Switch", 0,
 450                             mt8186_adda_dmic_get, mt8186_adda_dmic_set),
 451 };
 452
 453 /* ADDA UL MUX */
 454 enum {
 455         ADDA_UL_MUX_MTKAIF = 0,
 456         ADDA_UL_MUX_AP_DMIC,
 457         ADDA_UL_MUX_MASK = 0x1,
 458 };
 459
 460 static const char * const adda_ul_mux_map[] = {
 461         "MTKAIF", "AP_DMIC"
 462 };
 463
 464 static int adda_ul_map_value[] = {
 465         ADDA_UL_MUX_MTKAIF,
 466         ADDA_UL_MUX_AP_DMIC,
 467 };
 468
 469 static SOC_VALUE_ENUM_SINGLE_DECL(adda_ul_mux_map_enum,
 470                                   SND_SOC_NOPM,
 471                                   0,
 472                                   ADDA_UL_MUX_MASK,
 473                                   adda_ul_mux_map,
 474                                   adda_ul_map_value);
 475
 476 static const struct snd_kcontrol_new adda_ul_mux_control =
 477         SOC_DAPM_ENUM("ADDA_UL_MUX Select", adda_ul_mux_map_enum);
 478
 479 static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
 480         /* inter-connections */
 481         SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0,
 482                            mtk_adda_dl_ch1_mix,
 483                            ARRAY_SIZE(mtk_adda_dl_ch1_mix)),
 484         SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0,
 485                            mtk_adda_dl_ch2_mix,
 486                            ARRAY_SIZE(mtk_adda_dl_ch2_mix)),
 487
 488         SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
 489                               AFE_ADDA_UL_DL_CON0, ADDA_AFE_ON_SFT, 0,
 490                               NULL, 0),
 491
 492         SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
 493                               AFE_ADDA_DL_SRC2_CON0,
 494                               DL_2_SRC_ON_CTL_PRE_SFT, 0,
 495                               mtk_adda_dl_event,
 496                               SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 497
 498         SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
 499                               AFE_ADDA_UL_SRC_CON0,
 500                               UL_SRC_ON_CTL_SFT, 0,
 501                               mtk_adda_ul_event,
 502                               SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 503
 504         SND_SOC_DAPM_SUPPLY_S("AUD_PAD_TOP", SUPPLY_SEQ_ADDA_AUD_PAD_TOP,
 505                               0, 0, 0,
 506                               mtk_adda_pad_top_event,
 507                               SND_SOC_DAPM_PRE_PMU),
 508         SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG,
 509                               SND_SOC_NOPM, 0, 0,
 510                               mtk_adda_mtkaif_cfg_event,
 511                               SND_SOC_DAPM_PRE_PMU),
 512
 513         SND_SOC_DAPM_SUPPLY_S("AP_DMIC_EN", SUPPLY_SEQ_ADDA_AP_DMIC,
 514                               AFE_ADDA_UL_SRC_CON0,
 515                               UL_AP_DMIC_ON_SFT, 0,
 516                               NULL, 0),
 517
 518         SND_SOC_DAPM_SUPPLY_S("ADDA_FIFO", SUPPLY_SEQ_ADDA_FIFO,
 519                               AFE_ADDA_UL_DL_CON0,
 520                               AFE_ADDA_FIFO_AUTO_RST_SFT, 1,
 521                               NULL, 0),
 522
 523         SND_SOC_DAPM_MUX("ADDA_UL_Mux", SND_SOC_NOPM, 0, 0,
 524                          &adda_ul_mux_control),
 525
 526         SND_SOC_DAPM_INPUT("AP_DMIC_INPUT"),
 527
 528         /* clock */
 529         SND_SOC_DAPM_CLOCK_SUPPLY("top_mux_audio_h"),
 530
 531         SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_clk"),
 532         SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_hires_clk"),
 533         SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_predis_clk"),
 534
 535         SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_clk"),
 536         SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_hires_clk"),
 537 };
 538
 539 #define HIRES_THRESHOLD 48000
 540 static int mtk_afe_dac_hires_connect(struct snd_soc_dapm_widget *source,
 541                                      struct snd_soc_dapm_widget *sink)
 542 {
 543         struct snd_soc_dapm_widget *w = source;
 544         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 545         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 546         struct mtk_afe_adda_priv *adda_priv;
 547
 548         adda_priv = get_adda_priv_by_name(afe, w->name);
 549
 550         if (!adda_priv) {
 551                 dev_err(afe->dev, "%s(), adda_priv == NULL", __func__);
 552                 return 0;
 553         }
 554
 555         return (adda_priv->dl_rate > HIRES_THRESHOLD) ? 1 : 0;
 556 }
 557
 558 static int mtk_afe_adc_hires_connect(struct snd_soc_dapm_widget *source,
 559                                      struct snd_soc_dapm_widget *sink)
 560 {
 561         struct snd_soc_dapm_widget *w = source;
 562         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 563         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 564         struct mtk_afe_adda_priv *adda_priv;
 565
 566         adda_priv = get_adda_priv_by_name(afe, w->name);
 567
 568         if (!adda_priv) {
 569                 dev_err(afe->dev, "%s(), adda_priv == NULL", __func__);
 570                 return 0;
 571         }
 572
 573         return (adda_priv->ul_rate > HIRES_THRESHOLD) ? 1 : 0;
 574 }
 575
 576 static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
 577         /* playback */
 578         {"ADDA_DL_CH1", "DL1_CH1 Switch", "DL1"},
 579         {"ADDA_DL_CH2", "DL1_CH1 Switch", "DL1"},
 580         {"ADDA_DL_CH2", "DL1_CH2 Switch", "DL1"},
 581
 582         {"ADDA_DL_CH1", "DL12_CH1 Switch", "DL12"},
 583         {"ADDA_DL_CH2", "DL12_CH2 Switch", "DL12"},
 584
 585         {"ADDA_DL_CH1", "DL6_CH1 Switch", "DL6"},
 586         {"ADDA_DL_CH2", "DL6_CH2 Switch", "DL6"},
 587
 588         {"ADDA_DL_CH1", "DL8_CH1 Switch", "DL8"},
 589         {"ADDA_DL_CH2", "DL8_CH2 Switch", "DL8"},
 590
 591         {"ADDA_DL_CH1", "DL2_CH1 Switch", "DL2"},
 592         {"ADDA_DL_CH2", "DL2_CH1 Switch", "DL2"},
 593         {"ADDA_DL_CH2", "DL2_CH2 Switch", "DL2"},
 594
 595         {"ADDA_DL_CH1", "DL3_CH1 Switch", "DL3"},
 596         {"ADDA_DL_CH2", "DL3_CH1 Switch", "DL3"},
 597         {"ADDA_DL_CH2", "DL3_CH2 Switch", "DL3"},
 598
 599         {"ADDA_DL_CH1", "DL4_CH1 Switch", "DL4"},
 600         {"ADDA_DL_CH2", "DL4_CH2 Switch", "DL4"},
 601
 602         {"ADDA_DL_CH1", "DL5_CH1 Switch", "DL5"},
 603         {"ADDA_DL_CH2", "DL5_CH2 Switch", "DL5"},
 604
 605         {"ADDA Playback", NULL, "ADDA_DL_CH1"},
 606         {"ADDA Playback", NULL, "ADDA_DL_CH2"},
 607
 608         {"ADDA Playback", NULL, "ADDA Enable"},
 609         {"ADDA Playback", NULL, "ADDA Playback Enable"},
 610
 611         /* capture */
 612         {"ADDA_UL_Mux", "MTKAIF", "ADDA Capture"},
 613         {"ADDA_UL_Mux", "AP_DMIC", "AP DMIC Capture"},
 614
 615         {"ADDA Capture", NULL, "ADDA Enable"},
 616         {"ADDA Capture", NULL, "ADDA Capture Enable"},
 617         {"ADDA Capture", NULL, "AUD_PAD_TOP"},
 618         {"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"},
 619
 620         {"AP DMIC Capture", NULL, "ADDA Enable"},
 621         {"AP DMIC Capture", NULL, "ADDA Capture Enable"},
 622         {"AP DMIC Capture", NULL, "ADDA_FIFO"},
 623         {"AP DMIC Capture", NULL, "AP_DMIC_EN"},
 624
 625         {"AP DMIC Capture", NULL, "AP_DMIC_INPUT"},
 626
 627         /* clk */
 628         {"ADDA Playback", NULL, "aud_dac_clk"},
 629         {"ADDA Playback", NULL, "aud_dac_predis_clk"},
 630         {"ADDA Playback", NULL, "aud_dac_hires_clk", mtk_afe_dac_hires_connect},
 631
 632         {"ADDA Capture Enable", NULL, "aud_adc_clk"},
 633         {"ADDA Capture Enable", NULL, "aud_adc_hires_clk",
 634          mtk_afe_adc_hires_connect},
 635
 636         /* hires source from apll1 */
 637         {"top_mux_audio_h", NULL, APLL2_W_NAME},
 638
 639         {"aud_dac_hires_clk", NULL, "top_mux_audio_h"},
 640         {"aud_adc_hires_clk", NULL, "top_mux_audio_h"},
 641 };
 642
 643 /* dai ops */
 644 static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
 645                                   struct snd_pcm_hw_params *params,
 646                                   struct snd_soc_dai *dai)
 647 {
 648         struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
 649         struct mt8186_afe_private *afe_priv = afe->platform_priv;
 650         unsigned int rate = params_rate(params);
 651         int id = dai->id;
 652         struct mtk_afe_adda_priv *adda_priv = afe_priv->dai_priv[id];
 653
 654         dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
 655                 __func__, id, substream->stream, rate);
 656
 657         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 658                 unsigned int dl_src2_con0;
 659                 unsigned int dl_src2_con1;
 660
 661                 adda_priv->dl_rate = rate;
 662
 663                 /* set sampling rate */
 664                 dl_src2_con0 = adda_dl_rate_transform(afe, rate) <<
 665                                DL_2_INPUT_MODE_CTL_SFT;
 666
 667                 /* set output mode, UP_SAMPLING_RATE_X8 */
 668                 dl_src2_con0 |= (0x3 << DL_2_OUTPUT_SEL_CTL_SFT);
 669
 670                 /* turn off mute function */
 671                 dl_src2_con0 |= BIT(DL_2_MUTE_CH2_OFF_CTL_PRE_SFT);
 672                 dl_src2_con0 |= BIT(DL_2_MUTE_CH1_OFF_CTL_PRE_SFT);
 673
 674                 /* set voice input data if input sample rate is 8k or 16k */
 675                 if (rate == 8000 || rate == 16000)
 676                         dl_src2_con0 |= BIT(DL_2_VOICE_MODE_CTL_PRE_SFT);
 677
 678                 /* SA suggest apply -0.3db to audio/speech path */
 679                 dl_src2_con1 = MTK_AFE_ADDA_DL_GAIN_NORMAL <<
 680                                DL_2_GAIN_CTL_PRE_SFT;
 681
 682                 /* turn on down-link gain */
 683                 dl_src2_con0 |= BIT(DL_2_GAIN_ON_CTL_PRE_SFT);
 684
 685                 if (id == MT8186_DAI_ADDA) {
 686                         /* clean predistortion */
 687                         regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON0, 0);
 688                         regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON1, 0);
 689
 690                         regmap_write(afe->regmap,
 691                                      AFE_ADDA_DL_SRC2_CON0, dl_src2_con0);
 692                         regmap_write(afe->regmap,
 693                                      AFE_ADDA_DL_SRC2_CON1, dl_src2_con1);
 694
 695                         /* set sdm gain */
 696                         regmap_update_bits(afe->regmap,
 697                                            AFE_ADDA_DL_SDM_DCCOMP_CON,
 698                                            ATTGAIN_CTL_MASK_SFT,
 699                                            AUDIO_SDM_LEVEL_NORMAL <<
 700                                            ATTGAIN_CTL_SFT);
 701
 702                         /* Use new 2nd sdm */
 703                         regmap_update_bits(afe->regmap,
 704                                            AFE_ADDA_DL_SDM_DITHER_CON,
 705                                            AFE_DL_SDM_DITHER_64TAP_EN_MASK_SFT,
 706                                            BIT(AFE_DL_SDM_DITHER_64TAP_EN_SFT));
 707                         regmap_update_bits(afe->regmap,
 708                                            AFE_ADDA_DL_SDM_AUTO_RESET_CON,
 709                                            AFE_DL_USE_NEW_2ND_SDM_MASK_SFT,
 710                                            BIT(AFE_DL_USE_NEW_2ND_SDM_SFT));
 711                         regmap_update_bits(afe->regmap,
 712                                            AFE_ADDA_DL_SDM_DCCOMP_CON,
 713                                            USE_3RD_SDM_MASK_SFT,
 714                                            AUDIO_SDM_2ND << USE_3RD_SDM_SFT);
 715
 716                         /* sdm auto reset */
 717                         regmap_write(afe->regmap,
 718                                      AFE_ADDA_DL_SDM_AUTO_RESET_CON,
 719                                      SDM_AUTO_RESET_THRESHOLD);
 720                         regmap_update_bits(afe->regmap,
 721                                            AFE_ADDA_DL_SDM_AUTO_RESET_CON,
 722                                            SDM_AUTO_RESET_TEST_ON_MASK_SFT,
 723                                            BIT(SDM_AUTO_RESET_TEST_ON_SFT));
 724                 }
 725         } else {
 726                 unsigned int ul_src_con0 = 0;
 727                 unsigned int voice_mode = adda_ul_rate_transform(afe, rate);
 728
 729                 adda_priv->ul_rate = rate;
 730                 ul_src_con0 |= (voice_mode << 17) & (0x7 << 17);
 731
 732                 /* enable iir */
 733                 ul_src_con0 |= (1 << UL_IIR_ON_TMP_CTL_SFT) &
 734                                UL_IIR_ON_TMP_CTL_MASK_SFT;
 735                 ul_src_con0 |= (UL_IIR_SW << UL_IIRMODE_CTL_SFT) &
 736                                UL_IIRMODE_CTL_MASK_SFT;
 737                 switch (id) {
 738                 case MT8186_DAI_ADDA:
 739                 case MT8186_DAI_AP_DMIC:
 740                         /* 35Hz @ 48k */
 741                         regmap_write(afe->regmap,
 742                                      AFE_ADDA_IIR_COEF_02_01, 0);
 743                         regmap_write(afe->regmap,
 744                                      AFE_ADDA_IIR_COEF_04_03, 0x3fb8);
 745                         regmap_write(afe->regmap,
 746                                      AFE_ADDA_IIR_COEF_06_05, 0x3fb80000);
 747                         regmap_write(afe->regmap,
 748                                      AFE_ADDA_IIR_COEF_08_07, 0x3fb80000);
 749                         regmap_write(afe->regmap,
 750                                      AFE_ADDA_IIR_COEF_10_09, 0xc048);
 751
 752                         regmap_write(afe->regmap,
 753                                      AFE_ADDA_UL_SRC_CON0, ul_src_con0);
 754
 755                         /* Using Internal ADC */
 756                         regmap_update_bits(afe->regmap, AFE_ADDA_TOP_CON0, BIT(0), 0);
 757
 758                         /* mtkaif_rxif_data_mode = 0, amic */
 759                         regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0, BIT(0), 0);
 760                         break;
 761                 default:
 762                         break;
 763                 }
 764
 765                 /* ap dmic */
 766                 switch (id) {
 767                 case MT8186_DAI_AP_DMIC:
 768                         mtk_adda_ul_src_dmic(afe, id);
 769                         break;
 770                 default:
 771                         break;
 772                 }
 773         }
 774
 775         return 0;
 776 }
 777
 778 static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
 779         .hw_params = mtk_dai_adda_hw_params,
 780 };
 781
 782 /* dai driver */
 783 #define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\
 784                                  SNDRV_PCM_RATE_96000 |\
 785                                  SNDRV_PCM_RATE_192000)
 786
 787 #define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
 788                                 SNDRV_PCM_RATE_16000 |\
 789                                 SNDRV_PCM_RATE_32000 |\
 790                                 SNDRV_PCM_RATE_48000 |\
 791                                 SNDRV_PCM_RATE_96000 |\
 792                                 SNDRV_PCM_RATE_192000)
 793
 794 #define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
 795                           SNDRV_PCM_FMTBIT_S24_LE |\
 796                           SNDRV_PCM_FMTBIT_S32_LE)
 797
 798 static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
 799         {
 800                 .name = "ADDA",
 801                 .id = MT8186_DAI_ADDA,
 802                 .playback = {
 803                         .stream_name = "ADDA Playback",
 804                         .channels_min = 1,
 805                         .channels_max = 2,
 806                         .rates = MTK_ADDA_PLAYBACK_RATES,
 807                         .formats = MTK_ADDA_FORMATS,
 808                 },
 809                 .capture = {
 810                         .stream_name = "ADDA Capture",
 811                         .channels_min = 1,
 812                         .channels_max = 2,
 813                         .rates = MTK_ADDA_CAPTURE_RATES,
 814                         .formats = MTK_ADDA_FORMATS,
 815                 },
 816                 .ops = &mtk_dai_adda_ops,
 817         },
 818         {
 819                 .name = "AP_DMIC",
 820                 .id = MT8186_DAI_AP_DMIC,
 821                 .capture = {
 822                         .stream_name = "AP DMIC Capture",
 823                         .channels_min = 1,
 824                         .channels_max = 2,
 825                         .rates = MTK_ADDA_CAPTURE_RATES,
 826                         .formats = MTK_ADDA_FORMATS,
 827                 },
 828                 .ops = &mtk_dai_adda_ops,
 829         },
 830 };
 831
 832 int mt8186_dai_adda_register(struct mtk_base_afe *afe)
 833 {
 834         struct mtk_base_afe_dai *dai;
 835         struct mt8186_afe_private *afe_priv = afe->platform_priv;
 836         int ret;
 837
 838         dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
 839         if (!dai)
 840                 return -ENOMEM;
 841
 842         list_add(&dai->list, &afe->sub_dais);
 843
 844         dai->dai_drivers = mtk_dai_adda_driver;
 845         dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
 846
 847         dai->controls = mtk_adda_controls;
 848         dai->num_controls = ARRAY_SIZE(mtk_adda_controls);
 849         dai->dapm_widgets = mtk_dai_adda_widgets;
 850         dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
 851         dai->dapm_routes = mtk_dai_adda_routes;
 852         dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
 853
 854         /* set dai priv */
 855         ret = mt8186_dai_set_priv(afe, MT8186_DAI_ADDA,
 856                                   sizeof(struct mtk_afe_adda_priv), NULL);
 857         if (ret)
 858                 return ret;
 859
 860         /* ap dmic priv share with adda */
 861         afe_priv->dai_priv[MT8186_DAI_AP_DMIC] =
 862                 afe_priv->dai_priv[MT8186_DAI_ADDA];
 863
 864         return 0;
 865 }