1 // SPDX-License-Identifier: GPL-2.0
3 * Mediatek 8173 ALSA SoC AFE platform driver
5 * Copyright (c) 2015 MediaTek Inc.
6 * Author: Koro Chen <koro.chen@mediatek.com>
7 * Sascha Hauer <s.hauer@pengutronix.de>
8 * Hidalgo Huang <hidalgo.huang@mediatek.com>
9 * Ir Lian <ir.lian@mediatek.com>
12 #include <linux/delay.h>
13 #include <linux/module.h>
15 #include <linux/of_address.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/pm_runtime.h>
18 #include <sound/soc.h>
19 #include "mt8173-afe-common.h"
20 #include "../common/mtk-base-afe.h"
21 #include "../common/mtk-afe-platform-driver.h"
22 #include "../common/mtk-afe-fe-dai.h"
24 /*****************************************************************************
25 * R E G I S T E R D E F I N I T I O N
26 *****************************************************************************/
27 #define AUDIO_TOP_CON0 0x0000
28 #define AUDIO_TOP_CON1 0x0004
29 #define AFE_DAC_CON0 0x0010
30 #define AFE_DAC_CON1 0x0014
31 #define AFE_I2S_CON1 0x0034
32 #define AFE_I2S_CON2 0x0038
33 #define AFE_CONN_24BIT 0x006c
34 #define AFE_MEMIF_MSB 0x00cc
36 #define AFE_CONN1 0x0024
37 #define AFE_CONN2 0x0028
38 #define AFE_CONN3 0x002c
39 #define AFE_CONN7 0x0460
40 #define AFE_CONN8 0x0464
41 #define AFE_HDMI_CONN0 0x0390
43 /* Memory interface */
44 #define AFE_DL1_BASE 0x0040
45 #define AFE_DL1_CUR 0x0044
46 #define AFE_DL1_END 0x0048
47 #define AFE_DL2_BASE 0x0050
48 #define AFE_DL2_CUR 0x0054
49 #define AFE_AWB_BASE 0x0070
50 #define AFE_AWB_CUR 0x007c
51 #define AFE_VUL_BASE 0x0080
52 #define AFE_VUL_CUR 0x008c
53 #define AFE_VUL_END 0x0088
54 #define AFE_DAI_BASE 0x0090
55 #define AFE_DAI_CUR 0x009c
56 #define AFE_MOD_PCM_BASE 0x0330
57 #define AFE_MOD_PCM_CUR 0x033c
58 #define AFE_HDMI_OUT_BASE 0x0374
59 #define AFE_HDMI_OUT_CUR 0x0378
60 #define AFE_HDMI_OUT_END 0x037c
62 #define AFE_ADDA_TOP_CON0 0x0120
63 #define AFE_ADDA2_TOP_CON0 0x0600
65 #define AFE_HDMI_OUT_CON0 0x0370
67 #define AFE_IRQ_MCU_CON 0x03a0
68 #define AFE_IRQ_STATUS 0x03a4
69 #define AFE_IRQ_CLR 0x03a8
70 #define AFE_IRQ_CNT1 0x03ac
71 #define AFE_IRQ_CNT2 0x03b0
72 #define AFE_IRQ_MCU_EN 0x03b4
73 #define AFE_IRQ_CNT5 0x03bc
74 #define AFE_IRQ_CNT7 0x03dc
76 #define AFE_TDM_CON1 0x0548
77 #define AFE_TDM_CON2 0x054c
79 #define AFE_IRQ_STATUS_BITS 0xff
81 /* AUDIO_TOP_CON0 (0x0000) */
82 #define AUD_TCON0_PDN_SPDF (0x1 << 21)
83 #define AUD_TCON0_PDN_HDMI (0x1 << 20)
84 #define AUD_TCON0_PDN_24M (0x1 << 9)
85 #define AUD_TCON0_PDN_22M (0x1 << 8)
86 #define AUD_TCON0_PDN_AFE (0x1 << 2)
88 /* AFE_I2S_CON1 (0x0034) */
89 #define AFE_I2S_CON1_LOW_JITTER_CLK (0x1 << 12)
90 #define AFE_I2S_CON1_RATE(x) (((x) & 0xf) << 8)
91 #define AFE_I2S_CON1_FORMAT_I2S (0x1 << 3)
92 #define AFE_I2S_CON1_EN (0x1 << 0)
94 /* AFE_I2S_CON2 (0x0038) */
95 #define AFE_I2S_CON2_LOW_JITTER_CLK (0x1 << 12)
96 #define AFE_I2S_CON2_RATE(x) (((x) & 0xf) << 8)
97 #define AFE_I2S_CON2_FORMAT_I2S (0x1 << 3)
98 #define AFE_I2S_CON2_EN (0x1 << 0)
100 /* AFE_CONN_24BIT (0x006c) */
101 #define AFE_CONN_24BIT_O04 (0x1 << 4)
102 #define AFE_CONN_24BIT_O03 (0x1 << 3)
104 /* AFE_HDMI_CONN0 (0x0390) */
105 #define AFE_HDMI_CONN0_O37_I37 (0x7 << 21)
106 #define AFE_HDMI_CONN0_O36_I36 (0x6 << 18)
107 #define AFE_HDMI_CONN0_O35_I33 (0x3 << 15)
108 #define AFE_HDMI_CONN0_O34_I32 (0x2 << 12)
109 #define AFE_HDMI_CONN0_O33_I35 (0x5 << 9)
110 #define AFE_HDMI_CONN0_O32_I34 (0x4 << 6)
111 #define AFE_HDMI_CONN0_O31_I31 (0x1 << 3)
112 #define AFE_HDMI_CONN0_O30_I30 (0x0 << 0)
114 /* AFE_TDM_CON1 (0x0548) */
115 #define AFE_TDM_CON1_LRCK_WIDTH(x) (((x) - 1) << 24)
116 #define AFE_TDM_CON1_32_BCK_CYCLES (0x2 << 12)
117 #define AFE_TDM_CON1_WLEN_32BIT (0x2 << 8)
118 #define AFE_TDM_CON1_MSB_ALIGNED (0x1 << 4)
119 #define AFE_TDM_CON1_1_BCK_DELAY (0x1 << 3)
120 #define AFE_TDM_CON1_LRCK_INV (0x1 << 2)
121 #define AFE_TDM_CON1_BCK_INV (0x1 << 1)
122 #define AFE_TDM_CON1_EN (0x1 << 0)
124 enum afe_tdm_ch_start {
125 AFE_TDM_CH_START_O30_O31 = 0,
126 AFE_TDM_CH_START_O32_O33,
127 AFE_TDM_CH_START_O34_O35,
128 AFE_TDM_CH_START_O36_O37,
132 static const unsigned int mt8173_afe_backup_list[] = {
149 struct mt8173_afe_private {
150 struct clk *clocks[MT8173_CLK_NUM];
153 static const struct snd_pcm_hardware mt8173_afe_hardware = {
154 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
155 SNDRV_PCM_INFO_MMAP_VALID),
156 .buffer_bytes_max = 256 * 1024,
157 .period_bytes_min = 512,
158 .period_bytes_max = 128 * 1024,
164 struct mt8173_afe_rate {
166 unsigned int regvalue;
169 static const struct mt8173_afe_rate mt8173_afe_i2s_rates[] = {
170 { .rate = 8000, .regvalue = 0 },
171 { .rate = 11025, .regvalue = 1 },
172 { .rate = 12000, .regvalue = 2 },
173 { .rate = 16000, .regvalue = 4 },
174 { .rate = 22050, .regvalue = 5 },
175 { .rate = 24000, .regvalue = 6 },
176 { .rate = 32000, .regvalue = 8 },
177 { .rate = 44100, .regvalue = 9 },
178 { .rate = 48000, .regvalue = 10 },
179 { .rate = 88000, .regvalue = 11 },
180 { .rate = 96000, .regvalue = 12 },
181 { .rate = 174000, .regvalue = 13 },
182 { .rate = 192000, .regvalue = 14 },
185 static int mt8173_afe_i2s_fs(unsigned int sample_rate)
189 for (i = 0; i < ARRAY_SIZE(mt8173_afe_i2s_rates); i++)
190 if (mt8173_afe_i2s_rates[i].rate == sample_rate)
191 return mt8173_afe_i2s_rates[i].regvalue;
196 static int mt8173_afe_set_i2s(struct mtk_base_afe *afe, unsigned int rate)
199 int fs = mt8173_afe_i2s_fs(rate);
204 /* from external ADC */
205 regmap_update_bits(afe->regmap, AFE_ADDA_TOP_CON0, 0x1, 0x1);
206 regmap_update_bits(afe->regmap, AFE_ADDA2_TOP_CON0, 0x1, 0x1);
209 val = AFE_I2S_CON2_LOW_JITTER_CLK |
210 AFE_I2S_CON2_RATE(fs) |
211 AFE_I2S_CON2_FORMAT_I2S;
213 regmap_update_bits(afe->regmap, AFE_I2S_CON2, ~AFE_I2S_CON2_EN, val);
216 val = AFE_I2S_CON1_LOW_JITTER_CLK |
217 AFE_I2S_CON1_RATE(fs) |
218 AFE_I2S_CON1_FORMAT_I2S;
220 regmap_update_bits(afe->regmap, AFE_I2S_CON1, ~AFE_I2S_CON1_EN, val);
224 static void mt8173_afe_set_i2s_enable(struct mtk_base_afe *afe, bool enable)
228 regmap_read(afe->regmap, AFE_I2S_CON2, &val);
229 if (!!(val & AFE_I2S_CON2_EN) == enable)
233 regmap_update_bits(afe->regmap, AFE_I2S_CON2, 0x1, enable);
236 regmap_update_bits(afe->regmap, AFE_I2S_CON1, 0x1, enable);
239 static int mt8173_afe_dais_enable_clks(struct mtk_base_afe *afe,
240 struct clk *m_ck, struct clk *b_ck)
245 ret = clk_prepare_enable(m_ck);
247 dev_err(afe->dev, "Failed to enable m_ck\n");
253 ret = clk_prepare_enable(b_ck);
255 dev_err(afe->dev, "Failed to enable b_ck\n");
262 static int mt8173_afe_dais_set_clks(struct mtk_base_afe *afe,
263 struct clk *m_ck, unsigned int mck_rate,
264 struct clk *b_ck, unsigned int bck_rate)
269 ret = clk_set_rate(m_ck, mck_rate);
271 dev_err(afe->dev, "Failed to set m_ck rate\n");
277 ret = clk_set_rate(b_ck, bck_rate);
279 dev_err(afe->dev, "Failed to set b_ck rate\n");
286 static void mt8173_afe_dais_disable_clks(struct mtk_base_afe *afe,
287 struct clk *m_ck, struct clk *b_ck)
290 clk_disable_unprepare(m_ck);
292 clk_disable_unprepare(b_ck);
295 static int mt8173_afe_i2s_startup(struct snd_pcm_substream *substream,
296 struct snd_soc_dai *dai)
298 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
300 if (snd_soc_dai_active(dai))
303 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
304 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, 0);
308 static void mt8173_afe_i2s_shutdown(struct snd_pcm_substream *substream,
309 struct snd_soc_dai *dai)
311 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
313 if (snd_soc_dai_active(dai))
316 mt8173_afe_set_i2s_enable(afe, false);
317 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
318 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M,
319 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M);
322 static int mt8173_afe_i2s_prepare(struct snd_pcm_substream *substream,
323 struct snd_soc_dai *dai)
325 struct snd_pcm_runtime * const runtime = substream->runtime;
326 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
327 struct mt8173_afe_private *afe_priv = afe->platform_priv;
330 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S1_M],
331 runtime->rate * 256, NULL, 0);
332 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S2_M],
333 runtime->rate * 256, NULL, 0);
335 ret = mt8173_afe_set_i2s(afe, substream->runtime->rate);
339 mt8173_afe_set_i2s_enable(afe, true);
344 static int mt8173_afe_hdmi_startup(struct snd_pcm_substream *substream,
345 struct snd_soc_dai *dai)
347 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
348 struct mt8173_afe_private *afe_priv = afe->platform_priv;
350 if (snd_soc_dai_active(dai))
353 mt8173_afe_dais_enable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M],
354 afe_priv->clocks[MT8173_CLK_I2S3_B]);
358 static void mt8173_afe_hdmi_shutdown(struct snd_pcm_substream *substream,
359 struct snd_soc_dai *dai)
361 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
362 struct mt8173_afe_private *afe_priv = afe->platform_priv;
364 if (snd_soc_dai_active(dai))
367 mt8173_afe_dais_disable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M],
368 afe_priv->clocks[MT8173_CLK_I2S3_B]);
371 static int mt8173_afe_hdmi_prepare(struct snd_pcm_substream *substream,
372 struct snd_soc_dai *dai)
374 struct snd_pcm_runtime * const runtime = substream->runtime;
375 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
376 struct mt8173_afe_private *afe_priv = afe->platform_priv;
380 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M],
382 afe_priv->clocks[MT8173_CLK_I2S3_B],
383 runtime->rate * runtime->channels * 32);
385 val = AFE_TDM_CON1_BCK_INV |
386 AFE_TDM_CON1_LRCK_INV |
387 AFE_TDM_CON1_1_BCK_DELAY |
388 AFE_TDM_CON1_MSB_ALIGNED | /* I2S mode */
389 AFE_TDM_CON1_WLEN_32BIT |
390 AFE_TDM_CON1_32_BCK_CYCLES |
391 AFE_TDM_CON1_LRCK_WIDTH(32);
392 regmap_update_bits(afe->regmap, AFE_TDM_CON1, ~AFE_TDM_CON1_EN, val);
394 /* set tdm2 config */
395 switch (runtime->channels) {
398 val = AFE_TDM_CH_START_O30_O31;
399 val |= (AFE_TDM_CH_ZERO << 4);
400 val |= (AFE_TDM_CH_ZERO << 8);
401 val |= (AFE_TDM_CH_ZERO << 12);
405 val = AFE_TDM_CH_START_O30_O31;
406 val |= (AFE_TDM_CH_START_O32_O33 << 4);
407 val |= (AFE_TDM_CH_ZERO << 8);
408 val |= (AFE_TDM_CH_ZERO << 12);
412 val = AFE_TDM_CH_START_O30_O31;
413 val |= (AFE_TDM_CH_START_O32_O33 << 4);
414 val |= (AFE_TDM_CH_START_O34_O35 << 8);
415 val |= (AFE_TDM_CH_ZERO << 12);
419 val = AFE_TDM_CH_START_O30_O31;
420 val |= (AFE_TDM_CH_START_O32_O33 << 4);
421 val |= (AFE_TDM_CH_START_O34_O35 << 8);
422 val |= (AFE_TDM_CH_START_O36_O37 << 12);
427 regmap_update_bits(afe->regmap, AFE_TDM_CON2, 0x0000ffff, val);
429 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
430 0x000000f0, runtime->channels << 4);
434 static int mt8173_afe_hdmi_trigger(struct snd_pcm_substream *substream, int cmd,
435 struct snd_soc_dai *dai)
437 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
439 dev_info(afe->dev, "%s cmd=%d %s\n", __func__, cmd, dai->name);
442 case SNDRV_PCM_TRIGGER_START:
443 case SNDRV_PCM_TRIGGER_RESUME:
444 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
445 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF, 0);
447 /* set connections: O30~O37: L/R/LS/RS/C/LFE/CH7/CH8 */
448 regmap_write(afe->regmap, AFE_HDMI_CONN0,
449 AFE_HDMI_CONN0_O30_I30 |
450 AFE_HDMI_CONN0_O31_I31 |
451 AFE_HDMI_CONN0_O32_I34 |
452 AFE_HDMI_CONN0_O33_I35 |
453 AFE_HDMI_CONN0_O34_I32 |
454 AFE_HDMI_CONN0_O35_I33 |
455 AFE_HDMI_CONN0_O36_I36 |
456 AFE_HDMI_CONN0_O37_I37);
458 /* enable Out control */
459 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0x1);
462 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0x1);
465 case SNDRV_PCM_TRIGGER_STOP:
466 case SNDRV_PCM_TRIGGER_SUSPEND:
468 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0);
470 /* disable Out control */
471 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0);
473 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
474 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF,
475 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF);
482 static int mt8173_memif_fs(struct snd_pcm_substream *substream,
485 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
486 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
487 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
488 struct mtk_base_afe_memif *memif = &afe->memif[asoc_rtd_to_cpu(rtd, 0)->id];
491 if (memif->data->id == MT8173_AFE_MEMIF_DAI ||
492 memif->data->id == MT8173_AFE_MEMIF_MOD_DAI) {
507 fs = mt8173_afe_i2s_fs(rate);
512 static int mt8173_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
514 return mt8173_afe_i2s_fs(rate);
518 static const struct snd_soc_dai_ops mt8173_afe_i2s_ops = {
519 .startup = mt8173_afe_i2s_startup,
520 .shutdown = mt8173_afe_i2s_shutdown,
521 .prepare = mt8173_afe_i2s_prepare,
524 static const struct snd_soc_dai_ops mt8173_afe_hdmi_ops = {
525 .startup = mt8173_afe_hdmi_startup,
526 .shutdown = mt8173_afe_hdmi_shutdown,
527 .prepare = mt8173_afe_hdmi_prepare,
528 .trigger = mt8173_afe_hdmi_trigger,
531 static struct snd_soc_dai_driver mt8173_afe_pcm_dais[] = {
532 /* FE DAIs: memory intefaces to CPU */
534 .name = "DL1", /* downlink 1 */
535 .id = MT8173_AFE_MEMIF_DL1,
537 .stream_name = "DL1",
540 .rates = SNDRV_PCM_RATE_8000_48000,
541 .formats = SNDRV_PCM_FMTBIT_S16_LE,
543 .ops = &mtk_afe_fe_ops,
545 .name = "VUL", /* voice uplink */
546 .id = MT8173_AFE_MEMIF_VUL,
548 .stream_name = "VUL",
551 .rates = SNDRV_PCM_RATE_8000_48000,
552 .formats = SNDRV_PCM_FMTBIT_S16_LE,
554 .ops = &mtk_afe_fe_ops,
558 .id = MT8173_AFE_IO_I2S,
560 .stream_name = "I2S Playback",
563 .rates = SNDRV_PCM_RATE_8000_48000,
564 .formats = SNDRV_PCM_FMTBIT_S16_LE,
567 .stream_name = "I2S Capture",
570 .rates = SNDRV_PCM_RATE_8000_48000,
571 .formats = SNDRV_PCM_FMTBIT_S16_LE,
573 .ops = &mt8173_afe_i2s_ops,
578 static struct snd_soc_dai_driver mt8173_afe_hdmi_dais[] = {
582 .id = MT8173_AFE_MEMIF_HDMI,
584 .stream_name = "HDMI",
587 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
588 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
589 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
590 SNDRV_PCM_RATE_192000,
591 .formats = SNDRV_PCM_FMTBIT_S16_LE,
593 .ops = &mtk_afe_fe_ops,
597 .id = MT8173_AFE_IO_HDMI,
599 .stream_name = "HDMIO Playback",
602 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
603 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
604 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
605 SNDRV_PCM_RATE_192000,
606 .formats = SNDRV_PCM_FMTBIT_S16_LE,
608 .ops = &mt8173_afe_hdmi_ops,
612 static const struct snd_kcontrol_new mt8173_afe_o03_mix[] = {
613 SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN1, 21, 1, 0),
616 static const struct snd_kcontrol_new mt8173_afe_o04_mix[] = {
617 SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN2, 6, 1, 0),
620 static const struct snd_kcontrol_new mt8173_afe_o09_mix[] = {
621 SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN3, 0, 1, 0),
622 SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN7, 30, 1, 0),
625 static const struct snd_kcontrol_new mt8173_afe_o10_mix[] = {
626 SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN3, 3, 1, 0),
627 SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN8, 0, 1, 0),
630 static const struct snd_soc_dapm_widget mt8173_afe_pcm_widgets[] = {
631 /* inter-connections */
632 SND_SOC_DAPM_MIXER("I03", SND_SOC_NOPM, 0, 0, NULL, 0),
633 SND_SOC_DAPM_MIXER("I04", SND_SOC_NOPM, 0, 0, NULL, 0),
634 SND_SOC_DAPM_MIXER("I05", SND_SOC_NOPM, 0, 0, NULL, 0),
635 SND_SOC_DAPM_MIXER("I06", SND_SOC_NOPM, 0, 0, NULL, 0),
636 SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0),
637 SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0),
639 SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0,
640 mt8173_afe_o03_mix, ARRAY_SIZE(mt8173_afe_o03_mix)),
641 SND_SOC_DAPM_MIXER("O04", SND_SOC_NOPM, 0, 0,
642 mt8173_afe_o04_mix, ARRAY_SIZE(mt8173_afe_o04_mix)),
643 SND_SOC_DAPM_MIXER("O09", SND_SOC_NOPM, 0, 0,
644 mt8173_afe_o09_mix, ARRAY_SIZE(mt8173_afe_o09_mix)),
645 SND_SOC_DAPM_MIXER("O10", SND_SOC_NOPM, 0, 0,
646 mt8173_afe_o10_mix, ARRAY_SIZE(mt8173_afe_o10_mix)),
649 static const struct snd_soc_dapm_route mt8173_afe_pcm_routes[] = {
650 {"I05", NULL, "DL1"},
651 {"I06", NULL, "DL1"},
652 {"I2S Playback", NULL, "O03"},
653 {"I2S Playback", NULL, "O04"},
654 {"VUL", NULL, "O09"},
655 {"VUL", NULL, "O10"},
656 {"I03", NULL, "I2S Capture"},
657 {"I04", NULL, "I2S Capture"},
658 {"I17", NULL, "I2S Capture"},
659 {"I18", NULL, "I2S Capture"},
660 { "O03", "I05 Switch", "I05" },
661 { "O04", "I06 Switch", "I06" },
662 { "O09", "I17 Switch", "I17" },
663 { "O09", "I03 Switch", "I03" },
664 { "O10", "I18 Switch", "I18" },
665 { "O10", "I04 Switch", "I04" },
668 static const struct snd_soc_dapm_route mt8173_afe_hdmi_routes[] = {
669 {"HDMIO Playback", NULL, "HDMI"},
672 static const struct snd_soc_component_driver mt8173_afe_pcm_dai_component = {
673 .name = "mt8173-afe-pcm-dai",
674 .dapm_widgets = mt8173_afe_pcm_widgets,
675 .num_dapm_widgets = ARRAY_SIZE(mt8173_afe_pcm_widgets),
676 .dapm_routes = mt8173_afe_pcm_routes,
677 .num_dapm_routes = ARRAY_SIZE(mt8173_afe_pcm_routes),
678 .suspend = mtk_afe_suspend,
679 .resume = mtk_afe_resume,
682 static const struct snd_soc_component_driver mt8173_afe_hdmi_dai_component = {
683 .name = "mt8173-afe-hdmi-dai",
684 .dapm_routes = mt8173_afe_hdmi_routes,
685 .num_dapm_routes = ARRAY_SIZE(mt8173_afe_hdmi_routes),
686 .suspend = mtk_afe_suspend,
687 .resume = mtk_afe_resume,
690 static const char *aud_clks[MT8173_CLK_NUM] = {
691 [MT8173_CLK_INFRASYS_AUD] = "infra_sys_audio_clk",
692 [MT8173_CLK_TOP_PDN_AUD] = "top_pdn_audio",
693 [MT8173_CLK_TOP_PDN_AUD_BUS] = "top_pdn_aud_intbus",
694 [MT8173_CLK_I2S0_M] = "i2s0_m",
695 [MT8173_CLK_I2S1_M] = "i2s1_m",
696 [MT8173_CLK_I2S2_M] = "i2s2_m",
697 [MT8173_CLK_I2S3_M] = "i2s3_m",
698 [MT8173_CLK_I2S3_B] = "i2s3_b",
699 [MT8173_CLK_BCK0] = "bck0",
700 [MT8173_CLK_BCK1] = "bck1",
703 static const struct mtk_base_memif_data memif_data[MT8173_AFE_MEMIF_NUM] = {
706 .id = MT8173_AFE_MEMIF_DL1,
707 .reg_ofs_base = AFE_DL1_BASE,
708 .reg_ofs_cur = AFE_DL1_CUR,
709 .fs_reg = AFE_DAC_CON1,
712 .mono_reg = AFE_DAC_CON1,
715 .enable_reg = AFE_DAC_CON0,
717 .msb_reg = AFE_MEMIF_MSB,
719 .agent_disable_reg = -1,
722 .id = MT8173_AFE_MEMIF_DL2,
723 .reg_ofs_base = AFE_DL2_BASE,
724 .reg_ofs_cur = AFE_DL2_CUR,
725 .fs_reg = AFE_DAC_CON1,
728 .mono_reg = AFE_DAC_CON1,
731 .enable_reg = AFE_DAC_CON0,
733 .msb_reg = AFE_MEMIF_MSB,
735 .agent_disable_reg = -1,
738 .id = MT8173_AFE_MEMIF_VUL,
739 .reg_ofs_base = AFE_VUL_BASE,
740 .reg_ofs_cur = AFE_VUL_CUR,
741 .fs_reg = AFE_DAC_CON1,
744 .mono_reg = AFE_DAC_CON1,
747 .enable_reg = AFE_DAC_CON0,
749 .msb_reg = AFE_MEMIF_MSB,
751 .agent_disable_reg = -1,
754 .id = MT8173_AFE_MEMIF_DAI,
755 .reg_ofs_base = AFE_DAI_BASE,
756 .reg_ofs_cur = AFE_DAI_CUR,
757 .fs_reg = AFE_DAC_CON0,
763 .enable_reg = AFE_DAC_CON0,
765 .msb_reg = AFE_MEMIF_MSB,
767 .agent_disable_reg = -1,
770 .id = MT8173_AFE_MEMIF_AWB,
771 .reg_ofs_base = AFE_AWB_BASE,
772 .reg_ofs_cur = AFE_AWB_CUR,
773 .fs_reg = AFE_DAC_CON1,
776 .mono_reg = AFE_DAC_CON1,
779 .enable_reg = AFE_DAC_CON0,
781 .msb_reg = AFE_MEMIF_MSB,
783 .agent_disable_reg = -1,
786 .id = MT8173_AFE_MEMIF_MOD_DAI,
787 .reg_ofs_base = AFE_MOD_PCM_BASE,
788 .reg_ofs_cur = AFE_MOD_PCM_CUR,
789 .fs_reg = AFE_DAC_CON1,
792 .mono_reg = AFE_DAC_CON1,
795 .enable_reg = AFE_DAC_CON0,
797 .msb_reg = AFE_MEMIF_MSB,
799 .agent_disable_reg = -1,
802 .id = MT8173_AFE_MEMIF_HDMI,
803 .reg_ofs_base = AFE_HDMI_OUT_BASE,
804 .reg_ofs_cur = AFE_HDMI_OUT_CUR,
812 .msb_reg = AFE_MEMIF_MSB,
814 .agent_disable_reg = -1,
818 static const struct mtk_base_irq_data irq_data[MT8173_AFE_IRQ_NUM] = {
820 .id = MT8173_AFE_IRQ_DL1,
821 .irq_cnt_reg = AFE_IRQ_CNT1,
823 .irq_cnt_maskbit = 0x3ffff,
824 .irq_en_reg = AFE_IRQ_MCU_CON,
826 .irq_fs_reg = AFE_IRQ_MCU_CON,
828 .irq_fs_maskbit = 0xf,
829 .irq_clr_reg = AFE_IRQ_CLR,
832 .id = MT8173_AFE_IRQ_DL2,
833 .irq_cnt_reg = AFE_IRQ_CNT1,
835 .irq_cnt_maskbit = 0x3ffff,
836 .irq_en_reg = AFE_IRQ_MCU_CON,
838 .irq_fs_reg = AFE_IRQ_MCU_CON,
840 .irq_fs_maskbit = 0xf,
841 .irq_clr_reg = AFE_IRQ_CLR,
845 .id = MT8173_AFE_IRQ_VUL,
846 .irq_cnt_reg = AFE_IRQ_CNT2,
848 .irq_cnt_maskbit = 0x3ffff,
849 .irq_en_reg = AFE_IRQ_MCU_CON,
851 .irq_fs_reg = AFE_IRQ_MCU_CON,
853 .irq_fs_maskbit = 0xf,
854 .irq_clr_reg = AFE_IRQ_CLR,
857 .id = MT8173_AFE_IRQ_DAI,
858 .irq_cnt_reg = AFE_IRQ_CNT2,
860 .irq_cnt_maskbit = 0x3ffff,
861 .irq_en_reg = AFE_IRQ_MCU_CON,
863 .irq_fs_reg = AFE_IRQ_MCU_CON,
865 .irq_fs_maskbit = 0xf,
866 .irq_clr_reg = AFE_IRQ_CLR,
869 .id = MT8173_AFE_IRQ_AWB,
870 .irq_cnt_reg = AFE_IRQ_CNT7,
872 .irq_cnt_maskbit = 0x3ffff,
873 .irq_en_reg = AFE_IRQ_MCU_CON,
875 .irq_fs_reg = AFE_IRQ_MCU_CON,
877 .irq_fs_maskbit = 0xf,
878 .irq_clr_reg = AFE_IRQ_CLR,
881 .id = MT8173_AFE_IRQ_DAI,
882 .irq_cnt_reg = AFE_IRQ_CNT2,
884 .irq_cnt_maskbit = 0x3ffff,
885 .irq_en_reg = AFE_IRQ_MCU_CON,
887 .irq_fs_reg = AFE_IRQ_MCU_CON,
889 .irq_fs_maskbit = 0xf,
890 .irq_clr_reg = AFE_IRQ_CLR,
893 .id = MT8173_AFE_IRQ_HDMI,
894 .irq_cnt_reg = AFE_IRQ_CNT5,
896 .irq_cnt_maskbit = 0x3ffff,
897 .irq_en_reg = AFE_IRQ_MCU_CON,
900 .irq_fs_maskbit = -1,
901 .irq_clr_reg = AFE_IRQ_CLR,
906 static const struct regmap_config mt8173_afe_regmap_config = {
910 .max_register = AFE_ADDA2_TOP_CON0,
911 .cache_type = REGCACHE_NONE,
914 static irqreturn_t mt8173_afe_irq_handler(int irq, void *dev_id)
916 struct mtk_base_afe *afe = dev_id;
917 unsigned int reg_value;
920 ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, ®_value);
922 dev_err(afe->dev, "%s irq status err\n", __func__);
923 reg_value = AFE_IRQ_STATUS_BITS;
927 for (i = 0; i < MT8173_AFE_MEMIF_NUM; i++) {
928 struct mtk_base_afe_memif *memif = &afe->memif[i];
929 struct mtk_base_afe_irq *irq_p;
931 if (memif->irq_usage < 0)
934 irq_p = &afe->irqs[memif->irq_usage];
936 if (!(reg_value & (1 << irq_p->irq_data->irq_clr_shift)))
939 snd_pcm_period_elapsed(memif->substream);
944 regmap_write(afe->regmap, AFE_IRQ_CLR,
945 reg_value & AFE_IRQ_STATUS_BITS);
950 static int mt8173_afe_runtime_suspend(struct device *dev)
952 struct mtk_base_afe *afe = dev_get_drvdata(dev);
953 struct mt8173_afe_private *afe_priv = afe->platform_priv;
956 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0);
958 /* disable AFE clk */
959 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
960 AUD_TCON0_PDN_AFE, AUD_TCON0_PDN_AFE);
962 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_M]);
963 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S2_M]);
964 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK0]);
965 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK1]);
966 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]);
967 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]);
968 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]);
972 static int mt8173_afe_runtime_resume(struct device *dev)
974 struct mtk_base_afe *afe = dev_get_drvdata(dev);
975 struct mt8173_afe_private *afe_priv = afe->platform_priv;
978 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]);
982 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]);
986 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]);
988 goto err_top_aud_bus;
990 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_BCK0]);
994 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_BCK1]);
997 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_I2S1_M]);
1000 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_I2S2_M]);
1004 /* enable AFE clk */
1005 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, AUD_TCON0_PDN_AFE, 0);
1007 /* set O3/O4 16bits */
1008 regmap_update_bits(afe->regmap, AFE_CONN_24BIT,
1009 AFE_CONN_24BIT_O03 | AFE_CONN_24BIT_O04, 0);
1011 /* unmask all IRQs */
1012 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_EN, 0xff, 0xff);
1015 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
1019 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_M]);
1021 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S2_M]);
1023 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK0]);
1025 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]);
1027 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]);
1029 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]);
1033 static int mt8173_afe_init_audio_clk(struct mtk_base_afe *afe)
1036 struct mt8173_afe_private *afe_priv = afe->platform_priv;
1038 for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
1039 afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);
1040 if (IS_ERR(afe_priv->clocks[i])) {
1041 dev_err(afe->dev, "%s devm_clk_get %s fail\n",
1042 __func__, aud_clks[i]);
1043 return PTR_ERR(afe_priv->clocks[i]);
1046 clk_set_rate(afe_priv->clocks[MT8173_CLK_BCK0], 22579200); /* 22M */
1047 clk_set_rate(afe_priv->clocks[MT8173_CLK_BCK1], 24576000); /* 24M */
1051 static int mt8173_afe_pcm_dev_probe(struct platform_device *pdev)
1055 struct mtk_base_afe *afe;
1056 struct mt8173_afe_private *afe_priv;
1057 struct snd_soc_component *comp_pcm, *comp_hdmi;
1059 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(33));
1063 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
1067 afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
1069 afe_priv = afe->platform_priv;
1073 afe->dev = &pdev->dev;
1075 irq_id = platform_get_irq(pdev, 0);
1077 return irq_id < 0 ? irq_id : -ENXIO;
1078 ret = devm_request_irq(afe->dev, irq_id, mt8173_afe_irq_handler,
1079 0, "Afe_ISR_Handle", (void *)afe);
1081 dev_err(afe->dev, "could not request_irq\n");
1085 afe->base_addr = devm_platform_ioremap_resource(pdev, 0);
1086 if (IS_ERR(afe->base_addr))
1087 return PTR_ERR(afe->base_addr);
1089 afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
1090 &mt8173_afe_regmap_config);
1091 if (IS_ERR(afe->regmap))
1092 return PTR_ERR(afe->regmap);
1094 /* initial audio related clock */
1095 ret = mt8173_afe_init_audio_clk(afe);
1097 dev_err(afe->dev, "mt8173_afe_init_audio_clk fail\n");
1101 /* memif % irq initialize*/
1102 afe->memif_size = MT8173_AFE_MEMIF_NUM;
1103 afe->memif = devm_kcalloc(afe->dev, afe->memif_size,
1104 sizeof(*afe->memif), GFP_KERNEL);
1108 afe->irqs_size = MT8173_AFE_IRQ_NUM;
1109 afe->irqs = devm_kcalloc(afe->dev, afe->irqs_size,
1110 sizeof(*afe->irqs), GFP_KERNEL);
1114 for (i = 0; i < afe->irqs_size; i++) {
1115 afe->memif[i].data = &memif_data[i];
1116 afe->irqs[i].irq_data = &irq_data[i];
1117 afe->irqs[i].irq_occupyed = true;
1118 afe->memif[i].irq_usage = i;
1119 afe->memif[i].const_irq = 1;
1122 afe->mtk_afe_hardware = &mt8173_afe_hardware;
1123 afe->memif_fs = mt8173_memif_fs;
1124 afe->irq_fs = mt8173_irq_fs;
1126 platform_set_drvdata(pdev, afe);
1128 pm_runtime_enable(&pdev->dev);
1129 if (!pm_runtime_enabled(&pdev->dev)) {
1130 ret = mt8173_afe_runtime_resume(&pdev->dev);
1132 goto err_pm_disable;
1135 afe->reg_back_up_list = mt8173_afe_backup_list;
1136 afe->reg_back_up_list_num = ARRAY_SIZE(mt8173_afe_backup_list);
1137 afe->runtime_resume = mt8173_afe_runtime_resume;
1138 afe->runtime_suspend = mt8173_afe_runtime_suspend;
1140 ret = devm_snd_soc_register_component(&pdev->dev,
1141 &mtk_afe_pcm_platform,
1144 goto err_pm_disable;
1146 comp_pcm = devm_kzalloc(&pdev->dev, sizeof(*comp_pcm), GFP_KERNEL);
1149 goto err_pm_disable;
1152 ret = snd_soc_component_initialize(comp_pcm,
1153 &mt8173_afe_pcm_dai_component,
1156 goto err_pm_disable;
1158 #ifdef CONFIG_DEBUG_FS
1159 comp_pcm->debugfs_prefix = "pcm";
1162 ret = snd_soc_add_component(comp_pcm,
1163 mt8173_afe_pcm_dais,
1164 ARRAY_SIZE(mt8173_afe_pcm_dais));
1166 goto err_pm_disable;
1168 comp_hdmi = devm_kzalloc(&pdev->dev, sizeof(*comp_hdmi), GFP_KERNEL);
1171 goto err_pm_disable;
1174 ret = snd_soc_component_initialize(comp_hdmi,
1175 &mt8173_afe_hdmi_dai_component,
1178 goto err_pm_disable;
1180 #ifdef CONFIG_DEBUG_FS
1181 comp_hdmi->debugfs_prefix = "hdmi";
1184 ret = snd_soc_add_component(comp_hdmi,
1185 mt8173_afe_hdmi_dais,
1186 ARRAY_SIZE(mt8173_afe_hdmi_dais));
1188 goto err_cleanup_components;
1190 dev_info(&pdev->dev, "MT8173 AFE driver initialized.\n");
1193 err_cleanup_components:
1194 snd_soc_unregister_component(&pdev->dev);
1196 pm_runtime_disable(&pdev->dev);
1200 static int mt8173_afe_pcm_dev_remove(struct platform_device *pdev)
1202 snd_soc_unregister_component(&pdev->dev);
1204 pm_runtime_disable(&pdev->dev);
1205 if (!pm_runtime_status_suspended(&pdev->dev))
1206 mt8173_afe_runtime_suspend(&pdev->dev);
1210 static const struct of_device_id mt8173_afe_pcm_dt_match[] = {
1211 { .compatible = "mediatek,mt8173-afe-pcm", },
1214 MODULE_DEVICE_TABLE(of, mt8173_afe_pcm_dt_match);
1216 static const struct dev_pm_ops mt8173_afe_pm_ops = {
1217 SET_RUNTIME_PM_OPS(mt8173_afe_runtime_suspend,
1218 mt8173_afe_runtime_resume, NULL)
1221 static struct platform_driver mt8173_afe_pcm_driver = {
1223 .name = "mt8173-afe-pcm",
1224 .of_match_table = mt8173_afe_pcm_dt_match,
1225 .pm = &mt8173_afe_pm_ops,
1227 .probe = mt8173_afe_pcm_dev_probe,
1228 .remove = mt8173_afe_pcm_dev_remove,
1231 module_platform_driver(mt8173_afe_pcm_driver);
1233 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver");
1234 MODULE_AUTHOR("Koro Chen <koro.chen@mediatek.com>");
1235 MODULE_LICENSE("GPL v2");