1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek ALSA SoC AFE platform driver for MT7986
5 * Copyright (c) 2023 MediaTek Inc.
6 * Authors: Vic Wu <vic.wu@mediatek.com>
7 * Maso Huang <maso.huang@mediatek.com>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/module.h>
14 #include <linux/of_address.h>
15 #include <linux/pm_runtime.h>
17 #include "mt7986-afe-common.h"
18 #include "mt7986-reg.h"
19 #include "../common/mtk-afe-platform-driver.h"
20 #include "../common/mtk-afe-fe-dai.h"
31 MTK_AFE_RATE_48K = 10,
32 MTK_AFE_RATE_88K = 13,
33 MTK_AFE_RATE_96K = 14,
34 MTK_AFE_RATE_176K = 17,
35 MTK_AFE_RATE_192K = 18,
39 CLK_INFRA_AUD_BUS_CK = 0,
47 static const char *aud_clks[CLK_NUM] = {
48 [CLK_INFRA_AUD_BUS_CK] = "aud_bus_ck",
49 [CLK_INFRA_AUD_26M_CK] = "aud_26m_ck",
50 [CLK_INFRA_AUD_L_CK] = "aud_l_ck",
51 [CLK_INFRA_AUD_AUD_CK] = "aud_aud_ck",
52 [CLK_INFRA_AUD_EG2_CK] = "aud_eg2_ck",
55 unsigned int mt7986_afe_rate_transform(struct device *dev, unsigned int rate)
59 return MTK_AFE_RATE_8K;
61 return MTK_AFE_RATE_11K;
63 return MTK_AFE_RATE_12K;
65 return MTK_AFE_RATE_16K;
67 return MTK_AFE_RATE_22K;
69 return MTK_AFE_RATE_24K;
71 return MTK_AFE_RATE_32K;
73 return MTK_AFE_RATE_44K;
75 return MTK_AFE_RATE_48K;
77 return MTK_AFE_RATE_88K;
79 return MTK_AFE_RATE_96K;
81 return MTK_AFE_RATE_176K;
83 return MTK_AFE_RATE_192K;
85 dev_warn(dev, "%s(), rate %u invalid, using %d!!!\n",
86 __func__, rate, MTK_AFE_RATE_48K);
87 return MTK_AFE_RATE_48K;
91 static const struct snd_pcm_hardware mt7986_afe_hardware = {
92 .info = SNDRV_PCM_INFO_MMAP |
93 SNDRV_PCM_INFO_INTERLEAVED |
94 SNDRV_PCM_INFO_MMAP_VALID,
95 .formats = SNDRV_PCM_FMTBIT_S16_LE |
96 SNDRV_PCM_FMTBIT_S24_LE |
97 SNDRV_PCM_FMTBIT_S32_LE,
98 .period_bytes_min = 256,
99 .period_bytes_max = 4 * 48 * 1024,
102 .buffer_bytes_max = 8 * 48 * 1024,
106 static int mt7986_memif_fs(struct snd_pcm_substream *substream,
109 struct snd_soc_pcm_runtime *rtd = substream->private_data;
110 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
111 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
113 return mt7986_afe_rate_transform(afe->dev, rate);
116 static int mt7986_irq_fs(struct snd_pcm_substream *substream,
119 struct snd_soc_pcm_runtime *rtd = substream->private_data;
120 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
121 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
123 return mt7986_afe_rate_transform(afe->dev, rate);
126 #define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
127 SNDRV_PCM_RATE_88200 |\
128 SNDRV_PCM_RATE_96000 |\
129 SNDRV_PCM_RATE_176400 |\
130 SNDRV_PCM_RATE_192000)
132 #define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
133 SNDRV_PCM_FMTBIT_S24_LE |\
134 SNDRV_PCM_FMTBIT_S32_LE)
136 static struct snd_soc_dai_driver mt7986_memif_dai_driver[] = {
137 /* FE DAIs: memory intefaces to CPU */
140 .id = MT7986_MEMIF_DL1,
142 .stream_name = "DL1",
145 .rates = MTK_PCM_RATES,
146 .formats = MTK_PCM_FORMATS,
148 .ops = &mtk_afe_fe_ops,
152 .id = MT7986_MEMIF_VUL12,
154 .stream_name = "UL1",
157 .rates = MTK_PCM_RATES,
158 .formats = MTK_PCM_FORMATS,
160 .ops = &mtk_afe_fe_ops,
164 static const struct snd_kcontrol_new o018_mix[] = {
165 SOC_DAPM_SINGLE_AUTODISABLE("I150_Switch", AFE_CONN018_4, 22, 1, 0),
168 static const struct snd_kcontrol_new o019_mix[] = {
169 SOC_DAPM_SINGLE_AUTODISABLE("I151_Switch", AFE_CONN019_4, 23, 1, 0),
172 static const struct snd_soc_dapm_widget mt7986_memif_widgets[] = {
174 SND_SOC_DAPM_MIXER("I032", SND_SOC_NOPM, 0, 0, NULL, 0),
175 SND_SOC_DAPM_MIXER("I033", SND_SOC_NOPM, 0, 0, NULL, 0),
178 SND_SOC_DAPM_MIXER("O018", SND_SOC_NOPM, 0, 0,
179 o018_mix, ARRAY_SIZE(o018_mix)),
180 SND_SOC_DAPM_MIXER("O019", SND_SOC_NOPM, 0, 0,
181 o019_mix, ARRAY_SIZE(o019_mix)),
184 static const struct snd_soc_dapm_route mt7986_memif_routes[] = {
185 {"I032", NULL, "DL1"},
186 {"I033", NULL, "DL1"},
187 {"UL1", NULL, "O018"},
188 {"UL1", NULL, "O019"},
189 {"O018", "I150_Switch", "I150"},
190 {"O019", "I151_Switch", "I151"},
193 static const struct snd_soc_component_driver mt7986_afe_pcm_dai_component = {
194 .name = "mt7986-afe-pcm-dai",
197 static const struct mtk_base_memif_data memif_data[MT7986_MEMIF_NUM] = {
198 [MT7986_MEMIF_DL1] = {
200 .id = MT7986_MEMIF_DL1,
201 .reg_ofs_base = AFE_DL0_BASE,
202 .reg_ofs_cur = AFE_DL0_CUR,
203 .reg_ofs_end = AFE_DL0_END,
204 .reg_ofs_base_msb = AFE_DL0_BASE_MSB,
205 .reg_ofs_cur_msb = AFE_DL0_CUR_MSB,
206 .reg_ofs_end_msb = AFE_DL0_END_MSB,
207 .fs_reg = AFE_DL0_CON0,
208 .fs_shift = DL0_MODE_SFT,
209 .fs_maskbit = DL0_MODE_MASK,
210 .mono_reg = AFE_DL0_CON0,
211 .mono_shift = DL0_MONO_SFT,
212 .enable_reg = AFE_DL0_CON0,
213 .enable_shift = DL0_ON_SFT,
214 .hd_reg = AFE_DL0_CON0,
215 .hd_shift = DL0_HD_MODE_SFT,
216 .hd_align_reg = AFE_DL0_CON0,
217 .hd_align_mshift = DL0_HALIGN_SFT,
218 .pbuf_reg = AFE_DL0_CON0,
219 .pbuf_shift = DL0_PBUF_SIZE_SFT,
220 .minlen_reg = AFE_DL0_CON0,
221 .minlen_shift = DL0_MINLEN_SFT,
223 [MT7986_MEMIF_VUL12] = {
225 .id = MT7986_MEMIF_VUL12,
226 .reg_ofs_base = AFE_VUL0_BASE,
227 .reg_ofs_cur = AFE_VUL0_CUR,
228 .reg_ofs_end = AFE_VUL0_END,
229 .reg_ofs_base_msb = AFE_VUL0_BASE_MSB,
230 .reg_ofs_cur_msb = AFE_VUL0_CUR_MSB,
231 .reg_ofs_end_msb = AFE_VUL0_END_MSB,
232 .fs_reg = AFE_VUL0_CON0,
233 .fs_shift = VUL0_MODE_SFT,
234 .fs_maskbit = VUL0_MODE_MASK,
235 .mono_reg = AFE_VUL0_CON0,
236 .mono_shift = VUL0_MONO_SFT,
237 .enable_reg = AFE_VUL0_CON0,
238 .enable_shift = VUL0_ON_SFT,
239 .hd_reg = AFE_VUL0_CON0,
240 .hd_shift = VUL0_HD_MODE_SFT,
241 .hd_align_reg = AFE_VUL0_CON0,
242 .hd_align_mshift = VUL0_HALIGN_SFT,
246 static const struct mtk_base_irq_data irq_data[MT7986_IRQ_NUM] = {
249 .irq_cnt_reg = AFE_IRQ0_MCU_CFG1,
250 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
251 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
252 .irq_fs_reg = AFE_IRQ0_MCU_CFG0,
253 .irq_fs_shift = IRQ_MCU_MODE_SFT,
254 .irq_fs_maskbit = IRQ_MCU_MODE_MASK,
255 .irq_en_reg = AFE_IRQ0_MCU_CFG0,
256 .irq_en_shift = IRQ_MCU_ON_SFT,
257 .irq_clr_reg = AFE_IRQ_MCU_CLR,
258 .irq_clr_shift = IRQ0_MCU_CLR_SFT,
262 .irq_cnt_reg = AFE_IRQ1_MCU_CFG1,
263 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
264 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
265 .irq_fs_reg = AFE_IRQ1_MCU_CFG0,
266 .irq_fs_shift = IRQ_MCU_MODE_SFT,
267 .irq_fs_maskbit = IRQ_MCU_MODE_MASK,
268 .irq_en_reg = AFE_IRQ1_MCU_CFG0,
269 .irq_en_shift = IRQ_MCU_ON_SFT,
270 .irq_clr_reg = AFE_IRQ_MCU_CLR,
271 .irq_clr_shift = IRQ1_MCU_CLR_SFT,
275 .irq_cnt_reg = AFE_IRQ2_MCU_CFG1,
276 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
277 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
278 .irq_fs_reg = AFE_IRQ2_MCU_CFG0,
279 .irq_fs_shift = IRQ_MCU_MODE_SFT,
280 .irq_fs_maskbit = IRQ_MCU_MODE_MASK,
281 .irq_en_reg = AFE_IRQ2_MCU_CFG0,
282 .irq_en_shift = IRQ_MCU_ON_SFT,
283 .irq_clr_reg = AFE_IRQ_MCU_CLR,
284 .irq_clr_shift = IRQ2_MCU_CLR_SFT,
288 static bool mt7986_is_volatile_reg(struct device *dev, unsigned int reg)
291 * Those auto-gen regs are read-only, so put it as volatile because
292 * volatile registers cannot be cached, which means that they cannot
293 * be set when power is off
297 case AFE_DL0_CUR_MSB:
299 case AFE_DL0_RCH_MON:
300 case AFE_DL0_LCH_MON:
301 case AFE_VUL0_CUR_MSB:
303 case AFE_IRQ_MCU_STATUS:
304 case AFE_MEMIF_RD_MON:
305 case AFE_MEMIF_WR_MON:
312 static const struct regmap_config mt7986_afe_regmap_config = {
316 .volatile_reg = mt7986_is_volatile_reg,
317 .max_register = AFE_MAX_REGISTER,
318 .num_reg_defaults_raw = ((AFE_MAX_REGISTER / 4) + 1),
321 static int mt7986_init_clock(struct mtk_base_afe *afe)
323 struct mt7986_afe_private *afe_priv = afe->platform_priv;
326 afe_priv->clks = devm_kcalloc(afe->dev, CLK_NUM,
327 sizeof(*afe_priv->clks), GFP_KERNEL);
330 afe_priv->num_clks = CLK_NUM;
332 for (i = 0; i < afe_priv->num_clks; i++)
333 afe_priv->clks[i].id = aud_clks[i];
335 ret = devm_clk_bulk_get(afe->dev, afe_priv->num_clks, afe_priv->clks);
337 return dev_err_probe(afe->dev, ret, "Failed to get clocks\n");
342 static irqreturn_t mt7986_afe_irq_handler(int irq_id, void *dev)
344 struct mtk_base_afe *afe = dev;
345 struct mtk_base_afe_irq *irq;
346 u32 mcu_en, status, status_mcu;
348 irqreturn_t irq_ret = IRQ_HANDLED;
350 /* get irq that is sent to MCU */
351 regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);
353 ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);
354 /* only care IRQ which is sent to MCU */
355 status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS;
357 if (ret || status_mcu == 0) {
358 dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n",
359 __func__, ret, status, mcu_en);
365 for (i = 0; i < MT7986_MEMIF_NUM; i++) {
366 struct mtk_base_afe_memif *memif = &afe->memif[i];
368 if (!memif->substream)
371 if (memif->irq_usage < 0)
374 irq = &afe->irqs[memif->irq_usage];
376 if (status_mcu & (1 << irq->irq_data->irq_en_shift))
377 snd_pcm_period_elapsed(memif->substream);
382 regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, status_mcu);
387 static int mt7986_afe_runtime_suspend(struct device *dev)
389 struct mtk_base_afe *afe = dev_get_drvdata(dev);
390 struct mt7986_afe_private *afe_priv = afe->platform_priv;
392 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
396 regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, 0x3fff, 0x3fff);
397 regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_APLL2_EN_MASK, 0);
398 regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_26M_EN_MASK, 0);
400 /* make sure all irq status are cleared, twice intended */
401 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
404 clk_bulk_disable_unprepare(afe_priv->num_clks, afe_priv->clks);
409 static int mt7986_afe_runtime_resume(struct device *dev)
411 struct mtk_base_afe *afe = dev_get_drvdata(dev);
412 struct mt7986_afe_private *afe_priv = afe->platform_priv;
415 ret = clk_bulk_prepare_enable(afe_priv->num_clks, afe_priv->clks);
417 return dev_err_probe(afe->dev, ret, "Failed to enable clocks\n");
419 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
423 regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, 0x3fff, 0);
424 regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_APLL2_EN_MASK,
426 regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_26M_EN_MASK,
432 static int mt7986_afe_component_probe(struct snd_soc_component *component)
434 return mtk_afe_add_sub_dai_control(component);
437 static const struct snd_soc_component_driver mt7986_afe_component = {
438 .name = AFE_PCM_NAME,
439 .probe = mt7986_afe_component_probe,
440 .pointer = mtk_afe_pcm_pointer,
441 .pcm_construct = mtk_afe_pcm_new,
444 static int mt7986_dai_memif_register(struct mtk_base_afe *afe)
446 struct mtk_base_afe_dai *dai;
448 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
452 list_add(&dai->list, &afe->sub_dais);
454 dai->dai_drivers = mt7986_memif_dai_driver;
455 dai->num_dai_drivers = ARRAY_SIZE(mt7986_memif_dai_driver);
457 dai->dapm_widgets = mt7986_memif_widgets;
458 dai->num_dapm_widgets = ARRAY_SIZE(mt7986_memif_widgets);
459 dai->dapm_routes = mt7986_memif_routes;
460 dai->num_dapm_routes = ARRAY_SIZE(mt7986_memif_routes);
465 typedef int (*dai_register_cb)(struct mtk_base_afe *);
466 static const dai_register_cb dai_register_cbs[] = {
467 mt7986_dai_etdm_register,
468 mt7986_dai_memif_register,
471 static int mt7986_afe_pcm_dev_probe(struct platform_device *pdev)
473 struct mtk_base_afe *afe;
474 struct mt7986_afe_private *afe_priv;
478 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
481 platform_set_drvdata(pdev, afe);
483 afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
485 if (!afe->platform_priv)
488 afe_priv = afe->platform_priv;
489 afe->dev = &pdev->dev;
492 afe->base_addr = devm_platform_ioremap_resource(pdev, 0);
493 if (IS_ERR(afe->base_addr))
494 return PTR_ERR(afe->base_addr);
496 /* initial audio related clock */
497 ret = mt7986_init_clock(afe);
499 return dev_err_probe(dev, ret, "Cannot initialize clocks\n");
501 ret = devm_pm_runtime_enable(dev);
505 /* enable clock for regcache get default value from hw */
506 afe_priv->pm_runtime_bypass_reg_ctl = true;
507 pm_runtime_get_sync(&pdev->dev);
509 afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
510 &mt7986_afe_regmap_config);
512 pm_runtime_put_sync(&pdev->dev);
513 if (IS_ERR(afe->regmap))
514 return PTR_ERR(afe->regmap);
516 afe_priv->pm_runtime_bypass_reg_ctl = false;
519 afe->memif_size = MT7986_MEMIF_NUM;
520 afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
525 for (i = 0; i < afe->memif_size; i++) {
526 afe->memif[i].data = &memif_data[i];
527 afe->memif[i].irq_usage = -1;
530 mutex_init(&afe->irq_alloc_lock);
533 afe->irqs_size = MT7986_IRQ_NUM;
534 afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
539 for (i = 0; i < afe->irqs_size; i++)
540 afe->irqs[i].irq_data = &irq_data[i];
543 irq_id = platform_get_irq(pdev, 0);
546 return dev_err_probe(dev, ret, "No irq found\n");
548 ret = devm_request_irq(dev, irq_id, mt7986_afe_irq_handler,
549 IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
551 return dev_err_probe(dev, ret, "Failed to request irq for asys-isr\n");
554 INIT_LIST_HEAD(&afe->sub_dais);
556 for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
557 ret = dai_register_cbs[i](afe);
559 return dev_err_probe(dev, ret, "DAI register failed, i: %d\n", i);
562 /* init dai_driver and component_driver */
563 ret = mtk_afe_combine_sub_dai(afe);
565 return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n");
567 afe->mtk_afe_hardware = &mt7986_afe_hardware;
568 afe->memif_fs = mt7986_memif_fs;
569 afe->irq_fs = mt7986_irq_fs;
571 afe->runtime_resume = mt7986_afe_runtime_resume;
572 afe->runtime_suspend = mt7986_afe_runtime_suspend;
574 /* register component */
575 ret = devm_snd_soc_register_component(&pdev->dev,
576 &mt7986_afe_component,
579 return dev_err_probe(dev, ret, "Cannot register AFE component\n");
581 ret = devm_snd_soc_register_component(afe->dev,
582 &mt7986_afe_pcm_dai_component,
584 afe->num_dai_drivers);
586 return dev_err_probe(dev, ret, "Cannot register PCM DAI component\n");
591 static void mt7986_afe_pcm_dev_remove(struct platform_device *pdev)
593 pm_runtime_disable(&pdev->dev);
594 if (!pm_runtime_status_suspended(&pdev->dev))
595 mt7986_afe_runtime_suspend(&pdev->dev);
598 static const struct of_device_id mt7986_afe_pcm_dt_match[] = {
599 { .compatible = "mediatek,mt7986-afe" },
602 MODULE_DEVICE_TABLE(of, mt7986_afe_pcm_dt_match);
604 static const struct dev_pm_ops mt7986_afe_pm_ops = {
605 SET_RUNTIME_PM_OPS(mt7986_afe_runtime_suspend,
606 mt7986_afe_runtime_resume, NULL)
609 static struct platform_driver mt7986_afe_pcm_driver = {
611 .name = "mt7986-audio",
612 .of_match_table = mt7986_afe_pcm_dt_match,
613 .pm = &mt7986_afe_pm_ops,
615 .probe = mt7986_afe_pcm_dev_probe,
616 .remove_new = mt7986_afe_pcm_dev_remove,
618 module_platform_driver(mt7986_afe_pcm_driver);
620 MODULE_DESCRIPTION("MediaTek SoC AFE platform driver for ALSA MT7986");
621 MODULE_AUTHOR("Vic Wu <vic.wu@mediatek.com>");
622 MODULE_LICENSE("GPL");