2 * Intel SST Haswell/Broadwell IPC Support
4 * Copyright (C) 2013, Intel Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #ifndef __SST_HASWELL_IPC_H
18 #define __SST_HASWELL_IPC_H
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/platform_device.h>
24 #define SST_HSW_NO_CHANNELS 4
25 #define SST_HSW_MAX_DX_REGIONS 14
26 #define SST_HSW_DX_CONTEXT_SIZE (640 * 1024)
28 #define SST_HSW_FW_LOG_CONFIG_DWORDS 12
29 #define SST_HSW_GLOBAL_LOG 15
32 * Upfront defined maximum message size that is
33 * expected by the in/out communication pipes in FW.
35 #define SST_HSW_IPC_MAX_PAYLOAD_SIZE 400
36 #define SST_HSW_MAX_INFO_SIZE 64
37 #define SST_HSW_BUILD_HASH_LENGTH 40
40 struct sst_hsw_stream;
41 struct sst_hsw_log_stream;
44 struct sst_module_runtime;
45 extern struct sst_ops haswell_ops;
47 /* Stream Allocate Path ID */
48 enum sst_hsw_stream_path_id {
49 SST_HSW_STREAM_PATH_SSP0_OUT = 0,
50 SST_HSW_STREAM_PATH_SSP0_IN = 1,
51 SST_HSW_STREAM_PATH_MAX_PATH_ID = 2,
54 /* Stream Allocate Stream Type */
55 enum sst_hsw_stream_type {
56 SST_HSW_STREAM_TYPE_RENDER = 0,
57 SST_HSW_STREAM_TYPE_SYSTEM = 1,
58 SST_HSW_STREAM_TYPE_CAPTURE = 2,
59 SST_HSW_STREAM_TYPE_LOOPBACK = 3,
60 SST_HSW_STREAM_TYPE_MAX_STREAM_TYPE = 4,
63 /* Stream Allocate Stream Format */
64 enum sst_hsw_stream_format {
65 SST_HSW_STREAM_FORMAT_PCM_FORMAT = 0,
66 SST_HSW_STREAM_FORMAT_MP3_FORMAT = 1,
67 SST_HSW_STREAM_FORMAT_AAC_FORMAT = 2,
68 SST_HSW_STREAM_FORMAT_MAX_FORMAT_ID = 3,
72 enum sst_hsw_device_id {
73 SST_HSW_DEVICE_SSP_0 = 0,
74 SST_HSW_DEVICE_SSP_1 = 1,
77 /* Device Master Clock Frequency */
78 enum sst_hsw_device_mclk {
79 SST_HSW_DEVICE_MCLK_OFF = 0,
80 SST_HSW_DEVICE_MCLK_FREQ_6_MHZ = 1,
81 SST_HSW_DEVICE_MCLK_FREQ_12_MHZ = 2,
82 SST_HSW_DEVICE_MCLK_FREQ_24_MHZ = 3,
85 /* Device Clock Master */
86 enum sst_hsw_device_mode {
87 SST_HSW_DEVICE_CLOCK_SLAVE = 0,
88 SST_HSW_DEVICE_CLOCK_MASTER = 1,
89 SST_HSW_DEVICE_TDM_CLOCK_MASTER = 2,
93 enum sst_hsw_dx_state {
94 SST_HSW_DX_STATE_D0 = 0,
95 SST_HSW_DX_STATE_D1 = 1,
96 SST_HSW_DX_STATE_D3 = 3,
97 SST_HSW_DX_STATE_MAX = 3,
100 /* Audio stream stage IDs */
101 enum sst_hsw_fx_stage_id {
102 SST_HSW_STAGE_ID_WAVES = 0,
103 SST_HSW_STAGE_ID_DTS = 1,
104 SST_HSW_STAGE_ID_DOLBY = 2,
105 SST_HSW_STAGE_ID_BOOST = 3,
106 SST_HSW_STAGE_ID_MAX_FX_ID
110 enum sst_hsw_dx_type {
111 SST_HSW_DX_TYPE_FW_IMAGE = 0,
112 SST_HSW_DX_TYPE_MEMORY_DUMP = 1
115 /* Volume Curve Type*/
116 enum sst_hsw_volume_curve {
117 SST_HSW_VOLUME_CURVE_NONE = 0,
118 SST_HSW_VOLUME_CURVE_FADE = 1
121 /* Sample ordering */
122 enum sst_hsw_interleaving {
123 SST_HSW_INTERLEAVING_PER_CHANNEL = 0,
124 SST_HSW_INTERLEAVING_PER_SAMPLE = 1,
127 /* Channel indices */
128 enum sst_hsw_channel_index {
129 SST_HSW_CHANNEL_LEFT = 0,
130 SST_HSW_CHANNEL_CENTER = 1,
131 SST_HSW_CHANNEL_RIGHT = 2,
132 SST_HSW_CHANNEL_LEFT_SURROUND = 3,
133 SST_HSW_CHANNEL_CENTER_SURROUND = 3,
134 SST_HSW_CHANNEL_RIGHT_SURROUND = 4,
135 SST_HSW_CHANNEL_LFE = 7,
136 SST_HSW_CHANNEL_INVALID = 0xF,
139 /* List of supported channel maps. */
140 enum sst_hsw_channel_config {
141 SST_HSW_CHANNEL_CONFIG_MONO = 0, /* mono only. */
142 SST_HSW_CHANNEL_CONFIG_STEREO = 1, /* L & R. */
143 SST_HSW_CHANNEL_CONFIG_2_POINT_1 = 2, /* L, R & LFE; PCM only. */
144 SST_HSW_CHANNEL_CONFIG_3_POINT_0 = 3, /* L, C & R; MP3 & AAC only. */
145 SST_HSW_CHANNEL_CONFIG_3_POINT_1 = 4, /* L, C, R & LFE; PCM only. */
146 SST_HSW_CHANNEL_CONFIG_QUATRO = 5, /* L, R, Ls & Rs; PCM only. */
147 SST_HSW_CHANNEL_CONFIG_4_POINT_0 = 6, /* L, C, R & Cs; MP3 & AAC only. */
148 SST_HSW_CHANNEL_CONFIG_5_POINT_0 = 7, /* L, C, R, Ls & Rs. */
149 SST_HSW_CHANNEL_CONFIG_5_POINT_1 = 8, /* L, C, R, Ls, Rs & LFE. */
150 SST_HSW_CHANNEL_CONFIG_DUAL_MONO = 9, /* One channel replicated in two. */
151 SST_HSW_CHANNEL_CONFIG_INVALID,
154 /* List of supported bit depths. */
155 enum sst_hsw_bitdepth {
156 SST_HSW_DEPTH_8BIT = 8,
157 SST_HSW_DEPTH_16BIT = 16,
158 SST_HSW_DEPTH_24BIT = 24, /* Default. */
159 SST_HSW_DEPTH_32BIT = 32,
160 SST_HSW_DEPTH_INVALID = 33,
163 enum sst_hsw_module_id {
164 SST_HSW_MODULE_BASE_FW = 0x0,
165 SST_HSW_MODULE_MP3 = 0x1,
166 SST_HSW_MODULE_AAC_5_1 = 0x2,
167 SST_HSW_MODULE_AAC_2_0 = 0x3,
168 SST_HSW_MODULE_SRC = 0x4,
169 SST_HSW_MODULE_WAVES = 0x5,
170 SST_HSW_MODULE_DOLBY = 0x6,
171 SST_HSW_MODULE_BOOST = 0x7,
172 SST_HSW_MODULE_LPAL = 0x8,
173 SST_HSW_MODULE_DTS = 0x9,
174 SST_HSW_MODULE_PCM_CAPTURE = 0xA,
175 SST_HSW_MODULE_PCM_SYSTEM = 0xB,
176 SST_HSW_MODULE_PCM_REFERENCE = 0xC,
177 SST_HSW_MODULE_PCM = 0xD,
178 SST_HSW_MODULE_BLUETOOTH_RENDER_MODULE = 0xE,
179 SST_HSW_MODULE_BLUETOOTH_CAPTURE_MODULE = 0xF,
180 SST_HSW_MAX_MODULE_ID,
183 enum sst_hsw_performance_action {
184 SST_HSW_PERF_START = 0,
185 SST_HSW_PERF_STOP = 1,
188 /* SST firmware module info */
189 struct sst_hsw_module_info {
190 u8 name[SST_HSW_MAX_INFO_SIZE];
191 u8 version[SST_HSW_MAX_INFO_SIZE];
192 } __attribute__((packed));
194 /* Module entry point */
195 struct sst_hsw_module_entry {
196 enum sst_hsw_module_id module_id;
198 } __attribute__((packed));
200 /* Module map - alignement matches DSP */
201 struct sst_hsw_module_map {
202 u8 module_entries_count;
203 struct sst_hsw_module_entry module_entries[1];
204 } __attribute__((packed));
206 struct sst_hsw_memory_info {
209 } __attribute__((packed));
211 struct sst_hsw_fx_enable {
212 struct sst_hsw_module_map module_map;
213 struct sst_hsw_memory_info persistent_mem;
214 } __attribute__((packed));
216 struct sst_hsw_get_fx_param {
219 } __attribute__((packed));
221 struct sst_hsw_perf_action {
223 } __attribute__((packed));
225 struct sst_hsw_perf_data {
229 } __attribute__((packed));
232 struct sst_hsw_ipc_fw_version {
237 u8 fw_build_hash[SST_HSW_BUILD_HASH_LENGTH];
238 u32 fw_log_providers_hash;
239 } __attribute__((packed));
241 /* Stream ring info */
242 struct sst_hsw_ipc_stream_ring {
248 } __attribute__((packed));
250 /* Debug Dump Log Enable Request */
251 struct sst_hsw_ipc_debug_log_enable_req {
252 struct sst_hsw_ipc_stream_ring ringinfo;
253 u32 config[SST_HSW_FW_LOG_CONFIG_DWORDS];
254 } __attribute__((packed));
256 /* Debug Dump Log Reply */
257 struct sst_hsw_ipc_debug_log_reply {
258 u32 log_buffer_begining;
260 } __attribute__((packed));
262 /* Stream glitch position */
263 struct sst_hsw_ipc_stream_glitch_position {
267 } __attribute__((packed));
269 /* Stream get position */
270 struct sst_hsw_ipc_stream_get_position {
273 } __attribute__((packed));
275 /* Stream set position */
276 struct sst_hsw_ipc_stream_set_position {
279 } __attribute__((packed));
281 /* Stream Free Request */
282 struct sst_hsw_ipc_stream_free_req {
285 } __attribute__((packed));
287 /* Set Volume Request */
288 struct sst_hsw_ipc_volume_req {
293 } __attribute__((packed));
295 /* Device Configuration Request */
296 struct sst_hsw_ipc_device_config_req {
303 } __attribute__((packed));
305 /* Audio Data formats */
306 struct sst_hsw_audio_data_format_ipc {
315 } __attribute__((packed));
317 /* Stream Allocate Request */
318 struct sst_hsw_ipc_stream_alloc_req {
323 struct sst_hsw_audio_data_format_ipc format;
324 struct sst_hsw_ipc_stream_ring ringinfo;
325 struct sst_hsw_module_map map;
326 struct sst_hsw_memory_info persistent_mem;
327 struct sst_hsw_memory_info scratch_mem;
328 u32 number_of_notifications;
329 } __attribute__((packed));
331 /* Stream Allocate Reply */
332 struct sst_hsw_ipc_stream_alloc_reply {
334 u32 mixer_hw_id; // returns rate ????
335 u32 read_position_register_address;
336 u32 presentation_position_register_address;
337 u32 peak_meter_register_address[SST_HSW_NO_CHANNELS];
338 u32 volume_register_address[SST_HSW_NO_CHANNELS];
339 } __attribute__((packed));
341 /* Get Mixer Stream Info */
342 struct sst_hsw_ipc_stream_info_reply {
344 u32 peak_meter_register_address[SST_HSW_NO_CHANNELS];
345 u32 volume_register_address[SST_HSW_NO_CHANNELS];
346 } __attribute__((packed));
348 /* DX State Request */
349 struct sst_hsw_ipc_dx_req {
352 } __attribute__((packed));
354 /* DX State Reply Memory Info Item */
355 struct sst_hsw_ipc_dx_memory_item {
359 } __attribute__((packed));
362 struct sst_hsw_ipc_dx_reply {
364 struct sst_hsw_ipc_dx_memory_item mem_info[SST_HSW_MAX_DX_REGIONS];
365 } __attribute__((packed));
367 struct sst_hsw_ipc_fw_version;
369 /* SST Init & Free */
370 struct sst_hsw *sst_hsw_new(struct device *dev, const u8 *fw, size_t fw_length,
372 void sst_hsw_free(struct sst_hsw *hsw);
373 int sst_hsw_fw_get_version(struct sst_hsw *hsw,
374 struct sst_hsw_ipc_fw_version *version);
375 u32 create_channel_map(enum sst_hsw_channel_config config);
377 /* Stream Mixer Controls - */
378 int sst_hsw_stream_mute(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
379 u32 stage_id, u32 channel);
380 int sst_hsw_stream_unmute(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
381 u32 stage_id, u32 channel);
383 int sst_hsw_stream_set_volume(struct sst_hsw *hsw,
384 struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 volume);
385 int sst_hsw_stream_get_volume(struct sst_hsw *hsw,
386 struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 *volume);
388 int sst_hsw_stream_set_volume_curve(struct sst_hsw *hsw,
389 struct sst_hsw_stream *stream, u64 curve_duration,
390 enum sst_hsw_volume_curve curve);
392 /* Global Mixer Controls - */
393 int sst_hsw_mixer_mute(struct sst_hsw *hsw, u32 stage_id, u32 channel);
394 int sst_hsw_mixer_unmute(struct sst_hsw *hsw, u32 stage_id, u32 channel);
396 int sst_hsw_mixer_set_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
398 int sst_hsw_mixer_get_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
401 int sst_hsw_mixer_set_volume_curve(struct sst_hsw *hsw,
402 u64 curve_duration, enum sst_hsw_volume_curve curve);
405 struct sst_hsw_stream *sst_hsw_stream_new(struct sst_hsw *hsw, int id,
406 u32 (*get_write_position)(struct sst_hsw_stream *stream, void *data),
409 int sst_hsw_stream_free(struct sst_hsw *hsw, struct sst_hsw_stream *stream);
411 /* Stream Configuration */
412 int sst_hsw_stream_format(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
413 enum sst_hsw_stream_path_id path_id,
414 enum sst_hsw_stream_type stream_type,
415 enum sst_hsw_stream_format format_id);
417 int sst_hsw_stream_buffer(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
418 u32 ring_pt_address, u32 num_pages,
419 u32 ring_size, u32 ring_offset, u32 ring_first_pfn);
421 int sst_hsw_stream_commit(struct sst_hsw *hsw, struct sst_hsw_stream *stream);
423 int sst_hsw_stream_set_valid(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
425 int sst_hsw_stream_set_rate(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
427 int sst_hsw_stream_set_bits(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
428 enum sst_hsw_bitdepth bits);
429 int sst_hsw_stream_set_channels(struct sst_hsw *hsw,
430 struct sst_hsw_stream *stream, int channels);
431 int sst_hsw_stream_set_map_config(struct sst_hsw *hsw,
432 struct sst_hsw_stream *stream, u32 map,
433 enum sst_hsw_channel_config config);
434 int sst_hsw_stream_set_style(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
435 enum sst_hsw_interleaving style);
436 int sst_hsw_stream_set_module_info(struct sst_hsw *hsw,
437 struct sst_hsw_stream *stream, struct sst_module_runtime *runtime);
438 int sst_hsw_stream_set_pmemory_info(struct sst_hsw *hsw,
439 struct sst_hsw_stream *stream, u32 offset, u32 size);
440 int sst_hsw_stream_set_smemory_info(struct sst_hsw *hsw,
441 struct sst_hsw_stream *stream, u32 offset, u32 size);
442 int sst_hsw_stream_get_hw_id(struct sst_hsw *hsw,
443 struct sst_hsw_stream *stream);
444 int sst_hsw_stream_get_mixer_id(struct sst_hsw *hsw,
445 struct sst_hsw_stream *stream);
446 u32 sst_hsw_stream_get_read_reg(struct sst_hsw *hsw,
447 struct sst_hsw_stream *stream);
448 u32 sst_hsw_stream_get_pointer_reg(struct sst_hsw *hsw,
449 struct sst_hsw_stream *stream);
450 u32 sst_hsw_stream_get_peak_reg(struct sst_hsw *hsw,
451 struct sst_hsw_stream *stream, u32 channel);
452 u32 sst_hsw_stream_get_vol_reg(struct sst_hsw *hsw,
453 struct sst_hsw_stream *stream, u32 channel);
454 int sst_hsw_mixer_get_info(struct sst_hsw *hsw);
456 /* Stream ALSA trigger operations */
457 int sst_hsw_stream_pause(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
459 int sst_hsw_stream_resume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
461 int sst_hsw_stream_reset(struct sst_hsw *hsw, struct sst_hsw_stream *stream);
463 /* Stream pointer positions */
464 int sst_hsw_stream_get_read_pos(struct sst_hsw *hsw,
465 struct sst_hsw_stream *stream, u32 *position);
466 int sst_hsw_stream_get_write_pos(struct sst_hsw *hsw,
467 struct sst_hsw_stream *stream, u32 *position);
468 int sst_hsw_stream_set_write_position(struct sst_hsw *hsw,
469 struct sst_hsw_stream *stream, u32 stage_id, u32 position);
470 u32 sst_hsw_get_dsp_position(struct sst_hsw *hsw,
471 struct sst_hsw_stream *stream);
472 u64 sst_hsw_get_dsp_presentation_position(struct sst_hsw *hsw,
473 struct sst_hsw_stream *stream);
476 int sst_hsw_device_set_config(struct sst_hsw *hsw,
477 enum sst_hsw_device_id dev, enum sst_hsw_device_mclk mclk,
478 enum sst_hsw_device_mode mode, u32 clock_divider);
481 int sst_hsw_dx_set_state(struct sst_hsw *hsw,
482 enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx);
483 int sst_hsw_dx_get_state(struct sst_hsw *hsw, u32 item,
484 u32 *offset, u32 *size, u32 *source);
487 int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata);
488 void sst_hsw_dsp_free(struct device *dev, struct sst_pdata *pdata);
489 struct sst_dsp *sst_hsw_get_dsp(struct sst_hsw *hsw);
491 /* runtime module management */
492 struct sst_module_runtime *sst_hsw_runtime_module_create(struct sst_hsw *hsw,
493 int mod_id, int offset);
494 void sst_hsw_runtime_module_free(struct sst_module_runtime *runtime);
497 int sst_hsw_dsp_runtime_resume(struct sst_hsw *hsw);
498 int sst_hsw_dsp_runtime_suspend(struct sst_hsw *hsw);
499 int sst_hsw_dsp_load(struct sst_hsw *hsw);
500 int sst_hsw_dsp_runtime_sleep(struct sst_hsw *hsw);