2 * skl_topology.h - Intel HDA Platform topology header file
4 * Copyright (C) 2014-15 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
6 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
21 #ifndef __SKL_TOPOLOGY_H__
22 #define __SKL_TOPOLOGY_H__
24 #include <linux/types.h>
26 #include <sound/hdaudio_ext.h>
27 #include <sound/soc.h>
29 #include "skl-tplg-interface.h"
31 #define BITS_PER_BYTE 8
32 #define MAX_TS_GROUPS 8
33 #define MAX_DMIC_TS_GROUPS 4
34 #define MAX_FIXED_DMIC_PARAMS_SIZE 727
36 /* Maximum number of coefficients up down mixer module */
37 #define UP_DOWN_MIXER_MAX_COEFF 6
39 #define MODULE_MAX_IN_PINS 8
40 #define MODULE_MAX_OUT_PINS 8
42 #define SKL_MIC_CH_SUPPORT 4
43 #define SKL_MIC_MAX_CH_SUPPORT 8
44 #define SKL_DEFAULT_MIC_SEL_GAIN 0x3FF
45 #define SKL_MIC_SEL_SWITCH 0x3
47 #define SKL_OUTPUT_PIN 0
48 #define SKL_INPUT_PIN 1
49 #define SKL_MAX_PATH_CONFIGS 8
50 #define SKL_MAX_MODULES_IN_PIPE 8
51 #define SKL_MAX_MODULE_FORMATS 32
52 #define SKL_MAX_MODULE_RESOURCES 32
54 enum skl_channel_index {
56 SKL_CHANNEL_RIGHT = 1,
57 SKL_CHANNEL_CENTER = 2,
58 SKL_CHANNEL_LEFT_SURROUND = 3,
59 SKL_CHANNEL_CENTER_SURROUND = 3,
60 SKL_CHANNEL_RIGHT_SURROUND = 4,
62 SKL_CHANNEL_INVALID = 0xF,
87 SKL_FS_128000 = 128000,
88 SKL_FS_176400 = 176400,
89 SKL_FS_192000 = 192000,
93 enum skl_widget_type {
94 SKL_WIDGET_VMIXER = 1,
100 struct skl_audio_data_format {
101 enum skl_s_freq s_freq;
102 enum skl_bitdepth bit_depth;
104 enum skl_ch_cfg ch_cfg;
105 enum skl_interleaving interleaving;
106 u8 number_of_channels;
112 struct skl_base_cfg {
117 struct skl_audio_data_format audio_fmt;
120 struct skl_cpr_gtw_cfg {
124 /* not mandatory; required only for DMIC/I2S */
128 struct skl_dma_control {
135 struct skl_base_cfg base_cfg;
136 struct skl_audio_data_format out_fmt;
137 u32 cpr_feature_mask;
138 struct skl_cpr_gtw_cfg gtw_cfg;
141 struct skl_cpr_pin_fmt {
143 struct skl_audio_data_format src_fmt;
144 struct skl_audio_data_format dst_fmt;
147 struct skl_src_module_cfg {
148 struct skl_base_cfg base_cfg;
149 enum skl_s_freq src_cfg;
152 struct notification_mask {
157 struct skl_up_down_mixer_cfg {
158 struct skl_base_cfg base_cfg;
159 enum skl_ch_cfg out_ch_cfg;
160 /* This should be set to 1 if user coefficients are required */
162 /* Pass the user coeff in this array */
163 s32 coeff[UP_DOWN_MIXER_MAX_COEFF];
166 struct skl_algo_cfg {
167 struct skl_base_cfg base_cfg;
171 struct skl_base_outfmt_cfg {
172 struct skl_base_cfg base_cfg;
173 struct skl_audio_data_format out_fmt;
177 SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0,
178 SKL_DMA_HDA_HOST_INPUT_CLASS = 1,
179 SKL_DMA_HDA_HOST_INOUT_CLASS = 2,
180 SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8,
181 SKL_DMA_HDA_LINK_INPUT_CLASS = 9,
182 SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA,
183 SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB,
184 SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC,
185 SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD,
188 union skl_ssp_dma_node {
191 u8 time_slot_index:4;
196 union skl_connector_node_id {
205 struct skl_module_fmt {
211 u32 interleaving_style;
216 struct skl_module_cfg;
218 struct skl_mod_inst_map {
223 struct skl_kpb_params {
225 struct skl_mod_inst_map map[0];
228 struct skl_module_inst_id {
235 enum skl_module_pin_state {
237 SKL_PIN_BIND_DONE = 1,
240 struct skl_module_pin {
241 struct skl_module_inst_id id;
244 enum skl_module_pin_state pin_state;
245 struct skl_module_cfg *tgt_mcfg;
248 struct skl_specific_cfg {
255 enum skl_pipe_state {
256 SKL_PIPE_INVALID = 0,
257 SKL_PIPE_CREATED = 1,
259 SKL_PIPE_STARTED = 3,
263 struct skl_pipe_module {
264 struct snd_soc_dapm_widget *w;
265 struct list_head node;
268 struct skl_pipe_params {
275 snd_pcm_format_t format;
278 unsigned int host_bps;
279 unsigned int link_bps;
282 struct skl_pipe_fmt {
288 struct skl_pipe_mcfg {
293 struct skl_path_config {
295 struct skl_pipe_fmt in_fmt;
296 struct skl_pipe_fmt out_fmt;
305 struct skl_pipe_params *p_params;
306 enum skl_pipe_state state;
310 struct skl_path_config configs[SKL_MAX_PATH_CONFIGS];
311 struct list_head w_list;
315 enum skl_module_state {
316 SKL_MODULE_UNINIT = 0,
317 SKL_MODULE_LOADED = 1,
318 SKL_MODULE_INIT_DONE = 2,
319 SKL_MODULE_BIND_DONE = 3,
320 SKL_MODULE_UNLOADED = 4,
323 enum d0i3_capability {
325 SKL_D0I3_STREAMING = 1,
326 SKL_D0I3_NON_STREAMING = 2,
329 struct skl_module_pin_fmt {
331 struct skl_module_fmt fmt;
334 struct skl_module_iface {
338 struct skl_module_pin_fmt inputs[MAX_IN_QUEUE];
339 struct skl_module_pin_fmt outputs[MAX_OUT_QUEUE];
342 struct skl_module_pin_resources {
347 struct skl_module_res {
357 struct skl_module_pin_resources input[MAX_IN_QUEUE];
358 struct skl_module_pin_resources output[MAX_OUT_QUEUE];
370 struct skl_module_res resources[SKL_MAX_MODULE_RESOURCES];
371 struct skl_module_iface formats[SKL_MAX_MODULE_FORMATS];
374 struct skl_module_cfg {
376 struct skl_module_inst_id id;
377 struct skl_module *module;
381 bool homogenous_inputs;
382 bool homogenous_outputs;
383 struct skl_module_fmt in_fmt[MODULE_MAX_IN_PINS];
384 struct skl_module_fmt out_fmt[MODULE_MAX_OUT_PINS];
399 u8 dmic_ch_combo_index;
405 enum d0i3_capability d0i3_caps;
406 u32 dma_buffer_size; /* in milli seconds */
407 struct skl_module_pin *m_in_pin;
408 struct skl_module_pin *m_out_pin;
409 enum skl_module_type m_type;
410 enum skl_hw_conn_type hw_conn_type;
411 enum skl_module_state m_state;
412 struct skl_pipe *pipe;
413 struct skl_specific_cfg formats_config;
414 struct skl_pipe_mcfg mod_cfg[SKL_MAX_MODULES_IN_PIPE];
417 struct skl_algo_data {
425 struct skl_pipeline {
426 struct skl_pipe *pipe;
427 struct list_head node;
430 struct skl_module_deferred_bind {
431 struct skl_module_cfg *src;
432 struct skl_module_cfg *dst;
433 struct list_head node;
436 struct skl_mic_sel_config {
439 u16 blob[SKL_MIC_MAX_CH_SUPPORT][SKL_MIC_MAX_CH_SUPPORT];
449 static inline struct skl *get_skl_ctx(struct device *dev)
451 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
453 return ebus_to_skl(ebus);
456 int skl_tplg_be_update_params(struct snd_soc_dai *dai,
457 struct skl_pipe_params *params);
458 int skl_dsp_set_dma_control(struct skl_sst *ctx,
459 struct skl_module_cfg *mconfig);
460 void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai,
461 struct skl_pipe_params *params, int stream);
462 int skl_tplg_init(struct snd_soc_platform *platform,
463 struct hdac_ext_bus *ebus);
464 struct skl_module_cfg *skl_tplg_fe_get_cpr_module(
465 struct snd_soc_dai *dai, int stream);
466 int skl_tplg_update_pipe_params(struct device *dev,
467 struct skl_module_cfg *mconfig, struct skl_pipe_params *params);
469 void skl_tplg_d0i3_get(struct skl *skl, enum d0i3_capability caps);
470 void skl_tplg_d0i3_put(struct skl *skl, enum d0i3_capability caps);
472 int skl_create_pipeline(struct skl_sst *ctx, struct skl_pipe *pipe);
474 int skl_run_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
476 int skl_pause_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
478 int skl_delete_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
480 int skl_stop_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
482 int skl_reset_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
484 int skl_init_module(struct skl_sst *ctx, struct skl_module_cfg *module_config);
486 int skl_bind_modules(struct skl_sst *ctx, struct skl_module_cfg
487 *src_module, struct skl_module_cfg *dst_module);
489 int skl_unbind_modules(struct skl_sst *ctx, struct skl_module_cfg
490 *src_module, struct skl_module_cfg *dst_module);
492 int skl_set_module_params(struct skl_sst *ctx, u32 *params, int size,
493 u32 param_id, struct skl_module_cfg *mcfg);
494 int skl_get_module_params(struct skl_sst *ctx, u32 *params, int size,
495 u32 param_id, struct skl_module_cfg *mcfg);
497 struct skl_module_cfg *skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai,
499 enum skl_bitdepth skl_get_bit_depth(int params);
500 int skl_pcm_host_dma_prepare(struct device *dev,
501 struct skl_pipe_params *params);
502 int skl_pcm_link_dma_prepare(struct device *dev,
503 struct skl_pipe_params *params);