sound/soc/intel/skylake/skl-pcm.c

   1 /*
   2  *  skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality
   3  *
   4  *  Copyright (C) 2014-2015 Intel Corp
   5  *  Author:  Jeeja KP <jeeja.kp@intel.com>
   6  *
   7  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   8  *
   9  *  This program is free software; you can redistribute it and/or modify
  10  *  it under the terms of the GNU General Public License as published by
  11  *  the Free Software Foundation; version 2 of the License.
  12  *
  13  *  This program is distributed in the hope that it will be useful, but
  14  *  WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  *  General Public License for more details.
  17  *
  18  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  19  *
  20  */
  21
  22 #include <linux/pci.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/delay.h>
  25 #include <sound/pcm_params.h>
  26 #include <sound/soc.h>
  27 #include "skl.h"
  28 #include "skl-topology.h"
  29 #include "skl-sst-dsp.h"
  30 #include "skl-sst-ipc.h"
  31
  32 #define HDA_MONO 1
  33 #define HDA_STEREO 2
  34 #define HDA_QUAD 4
  35 #define HDA_MAX 8
  36
  37 static const struct snd_pcm_hardware azx_pcm_hw = {
  38         .info =                 (SNDRV_PCM_INFO_MMAP |
  39                                  SNDRV_PCM_INFO_INTERLEAVED |
  40                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
  41                                  SNDRV_PCM_INFO_MMAP_VALID |
  42                                  SNDRV_PCM_INFO_PAUSE |
  43                                  SNDRV_PCM_INFO_RESUME |
  44                                  SNDRV_PCM_INFO_SYNC_START |
  45                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
  46                                  SNDRV_PCM_INFO_HAS_LINK_ATIME |
  47                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
  48         .formats =              SNDRV_PCM_FMTBIT_S16_LE |
  49                                 SNDRV_PCM_FMTBIT_S32_LE |
  50                                 SNDRV_PCM_FMTBIT_S24_LE,
  51         .rates =                SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
  52                                 SNDRV_PCM_RATE_8000,
  53         .rate_min =             8000,
  54         .rate_max =             48000,
  55         .channels_min =         1,
  56         .channels_max =         8,
  57         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
  58         .period_bytes_min =     128,
  59         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
  60         .periods_min =          2,
  61         .periods_max =          AZX_MAX_FRAG,
  62         .fifo_size =            0,
  63 };
  64
  65 static inline
  66 struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream)
  67 {
  68         return substream->runtime->private_data;
  69 }
  70
  71 static struct hdac_bus *get_bus_ctx(struct snd_pcm_substream *substream)
  72 {
  73         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
  74         struct hdac_stream *hstream = hdac_stream(stream);
  75         struct hdac_bus *bus = hstream->bus;
  76         return bus;
  77 }
  78
  79 static int skl_substream_alloc_pages(struct hdac_bus *bus,
  80                                  struct snd_pcm_substream *substream,
  81                                  size_t size)
  82 {
  83         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
  84
  85         hdac_stream(stream)->bufsize = 0;
  86         hdac_stream(stream)->period_bytes = 0;
  87         hdac_stream(stream)->format_val = 0;
  88
  89         return snd_pcm_lib_malloc_pages(substream, size);
  90 }
  91
  92 static int skl_substream_free_pages(struct hdac_bus *bus,
  93                                 struct snd_pcm_substream *substream)
  94 {
  95         return snd_pcm_lib_free_pages(substream);
  96 }
  97
  98 static void skl_set_pcm_constrains(struct hdac_bus *bus,
  99                                  struct snd_pcm_runtime *runtime)
 100 {
 101         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
 102
 103         /* avoid wrap-around with wall-clock */
 104         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
 105                                      20, 178000000);
 106 }
 107
 108 static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_bus *bus)
 109 {
 110         if (bus->ppcap)
 111                 return HDAC_EXT_STREAM_TYPE_HOST;
 112         else
 113                 return HDAC_EXT_STREAM_TYPE_COUPLED;
 114 }
 115
 116 /*
 117  * check if the stream opened is marked as ignore_suspend by machine, if so
 118  * then enable suspend_active refcount
 119  *
 120  * The count supend_active does not need lock as it is used in open/close
 121  * and suspend context
 122  */
 123 static void skl_set_suspend_active(struct snd_pcm_substream *substream,
 124                                          struct snd_soc_dai *dai, bool enable)
 125 {
 126         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 127         struct snd_soc_dapm_widget *w;
 128         struct skl *skl = bus_to_skl(bus);
 129
 130         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 131                 w = dai->playback_widget;
 132         else
 133                 w = dai->capture_widget;
 134
 135         if (w->ignore_suspend && enable)
 136                 skl->supend_active++;
 137         else if (w->ignore_suspend && !enable)
 138                 skl->supend_active--;
 139 }
 140
 141 int skl_pcm_host_dma_prepare(struct device *dev, struct skl_pipe_params *params)
 142 {
 143         struct hdac_bus *bus = dev_get_drvdata(dev);
 144         unsigned int format_val;
 145         struct hdac_stream *hstream;
 146         struct hdac_ext_stream *stream;
 147         int err;
 148
 149         hstream = snd_hdac_get_stream(bus, params->stream,
 150                                         params->host_dma_id + 1);
 151         if (!hstream)
 152                 return -EINVAL;
 153
 154         stream = stream_to_hdac_ext_stream(hstream);
 155         snd_hdac_ext_stream_decouple(bus, stream, true);
 156
 157         format_val = snd_hdac_calc_stream_format(params->s_freq,
 158                         params->ch, params->format, params->host_bps, 0);
 159
 160         dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
 161                 format_val, params->s_freq, params->ch, params->format);
 162
 163         snd_hdac_stream_reset(hdac_stream(stream));
 164         err = snd_hdac_stream_set_params(hdac_stream(stream), format_val);
 165         if (err < 0)
 166                 return err;
 167
 168         err = snd_hdac_stream_setup(hdac_stream(stream));
 169         if (err < 0)
 170                 return err;
 171
 172         hdac_stream(stream)->prepared = 1;
 173
 174         return 0;
 175 }
 176
 177 int skl_pcm_link_dma_prepare(struct device *dev, struct skl_pipe_params *params)
 178 {
 179         struct hdac_bus *bus = dev_get_drvdata(dev);
 180         unsigned int format_val;
 181         struct hdac_stream *hstream;
 182         struct hdac_ext_stream *stream;
 183         struct hdac_ext_link *link;
 184
 185         hstream = snd_hdac_get_stream(bus, params->stream,
 186                                         params->link_dma_id + 1);
 187         if (!hstream)
 188                 return -EINVAL;
 189
 190         stream = stream_to_hdac_ext_stream(hstream);
 191         snd_hdac_ext_stream_decouple(bus, stream, true);
 192         format_val = snd_hdac_calc_stream_format(params->s_freq, params->ch,
 193                                         params->format, params->link_bps, 0);
 194
 195         dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
 196                 format_val, params->s_freq, params->ch, params->format);
 197
 198         snd_hdac_ext_link_stream_reset(stream);
 199
 200         snd_hdac_ext_link_stream_setup(stream, format_val);
 201
 202         list_for_each_entry(link, &bus->hlink_list, list) {
 203                 if (link->index == params->link_index)
 204                         snd_hdac_ext_link_set_stream_id(link,
 205                                         hstream->stream_tag);
 206         }
 207
 208         stream->link_prepared = 1;
 209
 210         return 0;
 211 }
 212
 213 static int skl_pcm_open(struct snd_pcm_substream *substream,
 214                 struct snd_soc_dai *dai)
 215 {
 216         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 217         struct hdac_ext_stream *stream;
 218         struct snd_pcm_runtime *runtime = substream->runtime;
 219         struct skl_dma_params *dma_params;
 220         struct skl *skl = get_skl_ctx(dai->dev);
 221         struct skl_module_cfg *mconfig;
 222
 223         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 224
 225         stream = snd_hdac_ext_stream_assign(bus, substream,
 226                                         skl_get_host_stream_type(bus));
 227         if (stream == NULL)
 228                 return -EBUSY;
 229
 230         skl_set_pcm_constrains(bus, runtime);
 231
 232         /*
 233          * disable WALLCLOCK timestamps for capture streams
 234          * until we figure out how to handle digital inputs
 235          */
 236         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 237                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
 238                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
 239         }
 240
 241         runtime->private_data = stream;
 242
 243         dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL);
 244         if (!dma_params)
 245                 return -ENOMEM;
 246
 247         dma_params->stream_tag = hdac_stream(stream)->stream_tag;
 248         snd_soc_dai_set_dma_data(dai, substream, dma_params);
 249
 250         dev_dbg(dai->dev, "stream tag set in dma params=%d\n",
 251                                  dma_params->stream_tag);
 252         skl_set_suspend_active(substream, dai, true);
 253         snd_pcm_set_sync(substream);
 254
 255         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 256         if (!mconfig)
 257                 return -EINVAL;
 258
 259         skl_tplg_d0i3_get(skl, mconfig->d0i3_caps);
 260
 261         return 0;
 262 }
 263
 264 static int skl_pcm_prepare(struct snd_pcm_substream *substream,
 265                 struct snd_soc_dai *dai)
 266 {
 267         struct skl *skl = get_skl_ctx(dai->dev);
 268         struct skl_module_cfg *mconfig;
 269         int ret;
 270
 271         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 272
 273         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 274
 275         /*
 276          * In case of XRUN recovery or in the case when the application
 277          * calls prepare another time, reset the FW pipe to clean state
 278          */
 279         if (mconfig &&
 280                 (substream->runtime->status->state == SNDRV_PCM_STATE_XRUN ||
 281                  mconfig->pipe->state == SKL_PIPE_CREATED ||
 282                  mconfig->pipe->state == SKL_PIPE_PAUSED)) {
 283
 284                 ret = skl_reset_pipe(skl->skl_sst, mconfig->pipe);
 285
 286                 if (ret < 0)
 287                         return ret;
 288
 289                 ret = skl_pcm_host_dma_prepare(dai->dev,
 290                                         mconfig->pipe->p_params);
 291                 if (ret < 0)
 292                         return ret;
 293         }
 294
 295         return 0;
 296 }
 297
 298 static int skl_pcm_hw_params(struct snd_pcm_substream *substream,
 299                                 struct snd_pcm_hw_params *params,
 300                                 struct snd_soc_dai *dai)
 301 {
 302         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 303         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 304         struct snd_pcm_runtime *runtime = substream->runtime;
 305         struct skl_pipe_params p_params = {0};
 306         struct skl_module_cfg *m_cfg;
 307         int ret, dma_id;
 308
 309         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 310         ret = skl_substream_alloc_pages(bus, substream,
 311                                           params_buffer_bytes(params));
 312         if (ret < 0)
 313                 return ret;
 314
 315         dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n",
 316                         runtime->rate, runtime->channels, runtime->format);
 317
 318         dma_id = hdac_stream(stream)->stream_tag - 1;
 319         dev_dbg(dai->dev, "dma_id=%d\n", dma_id);
 320
 321         p_params.s_fmt = snd_pcm_format_width(params_format(params));
 322         p_params.ch = params_channels(params);
 323         p_params.s_freq = params_rate(params);
 324         p_params.host_dma_id = dma_id;
 325         p_params.stream = substream->stream;
 326         p_params.format = params_format(params);
 327         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 328                 p_params.host_bps = dai->driver->playback.sig_bits;
 329         else
 330                 p_params.host_bps = dai->driver->capture.sig_bits;
 331
 332
 333         m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream);
 334         if (m_cfg)
 335                 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params);
 336
 337         return 0;
 338 }
 339
 340 static void skl_pcm_close(struct snd_pcm_substream *substream,
 341                 struct snd_soc_dai *dai)
 342 {
 343         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 344         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 345         struct skl_dma_params *dma_params = NULL;
 346         struct skl *skl = bus_to_skl(bus);
 347         struct skl_module_cfg *mconfig;
 348
 349         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 350
 351         snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(bus));
 352
 353         dma_params = snd_soc_dai_get_dma_data(dai, substream);
 354         /*
 355          * now we should set this to NULL as we are freeing by the
 356          * dma_params
 357          */
 358         snd_soc_dai_set_dma_data(dai, substream, NULL);
 359         skl_set_suspend_active(substream, dai, false);
 360
 361         /*
 362          * check if close is for "Reference Pin" and set back the
 363          * CGCTL.MISCBDCGE if disabled by driver
 364          */
 365         if (!strncmp(dai->name, "Reference Pin", 13) &&
 366                         skl->skl_sst->miscbdcg_disabled) {
 367                 skl->skl_sst->enable_miscbdcge(dai->dev, true);
 368                 skl->skl_sst->miscbdcg_disabled = false;
 369         }
 370
 371         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 372         if (mconfig)
 373                 skl_tplg_d0i3_put(skl, mconfig->d0i3_caps);
 374
 375         kfree(dma_params);
 376 }
 377
 378 static int skl_pcm_hw_free(struct snd_pcm_substream *substream,
 379                 struct snd_soc_dai *dai)
 380 {
 381         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 382         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 383         struct skl *skl = get_skl_ctx(dai->dev);
 384         struct skl_module_cfg *mconfig;
 385         int ret;
 386
 387         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 388
 389         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 390
 391         if (mconfig) {
 392                 ret = skl_reset_pipe(skl->skl_sst, mconfig->pipe);
 393                 if (ret < 0)
 394                         dev_err(dai->dev, "%s:Reset failed ret =%d",
 395                                                 __func__, ret);
 396         }
 397
 398         snd_hdac_stream_cleanup(hdac_stream(stream));
 399         hdac_stream(stream)->prepared = 0;
 400
 401         return skl_substream_free_pages(bus, substream);
 402 }
 403
 404 static int skl_be_hw_params(struct snd_pcm_substream *substream,
 405                                 struct snd_pcm_hw_params *params,
 406                                 struct snd_soc_dai *dai)
 407 {
 408         struct skl_pipe_params p_params = {0};
 409
 410         p_params.s_fmt = snd_pcm_format_width(params_format(params));
 411         p_params.ch = params_channels(params);
 412         p_params.s_freq = params_rate(params);
 413         p_params.stream = substream->stream;
 414
 415         return skl_tplg_be_update_params(dai, &p_params);
 416 }
 417
 418 static int skl_decoupled_trigger(struct snd_pcm_substream *substream,
 419                 int cmd)
 420 {
 421         struct hdac_bus *bus = get_bus_ctx(substream);
 422         struct hdac_ext_stream *stream;
 423         int start;
 424         unsigned long cookie;
 425         struct hdac_stream *hstr;
 426
 427         stream = get_hdac_ext_stream(substream);
 428         hstr = hdac_stream(stream);
 429
 430         if (!hstr->prepared)
 431                 return -EPIPE;
 432
 433         switch (cmd) {
 434         case SNDRV_PCM_TRIGGER_START:
 435         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 436         case SNDRV_PCM_TRIGGER_RESUME:
 437                 start = 1;
 438                 break;
 439
 440         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 441         case SNDRV_PCM_TRIGGER_SUSPEND:
 442         case SNDRV_PCM_TRIGGER_STOP:
 443                 start = 0;
 444                 break;
 445
 446         default:
 447                 return -EINVAL;
 448         }
 449
 450         spin_lock_irqsave(&bus->reg_lock, cookie);
 451
 452         if (start) {
 453                 snd_hdac_stream_start(hdac_stream(stream), true);
 454                 snd_hdac_stream_timecounter_init(hstr, 0);
 455         } else {
 456                 snd_hdac_stream_stop(hdac_stream(stream));
 457         }
 458
 459         spin_unlock_irqrestore(&bus->reg_lock, cookie);
 460
 461         return 0;
 462 }
 463
 464 static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
 465                 struct snd_soc_dai *dai)
 466 {
 467         struct skl *skl = get_skl_ctx(dai->dev);
 468         struct skl_sst *ctx = skl->skl_sst;
 469         struct skl_module_cfg *mconfig;
 470         struct hdac_bus *bus = get_bus_ctx(substream);
 471         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 472         struct snd_soc_dapm_widget *w;
 473         int ret;
 474
 475         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 476         if (!mconfig)
 477                 return -EIO;
 478
 479         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 480                 w = dai->playback_widget;
 481         else
 482                 w = dai->capture_widget;
 483
 484         switch (cmd) {
 485         case SNDRV_PCM_TRIGGER_RESUME:
 486                 if (!w->ignore_suspend) {
 487                         /*
 488                          * enable DMA Resume enable bit for the stream, set the
 489                          * dpib & lpib position to resume before starting the
 490                          * DMA
 491                          */
 492                         snd_hdac_ext_stream_drsm_enable(bus, true,
 493                                                 hdac_stream(stream)->index);
 494                         snd_hdac_ext_stream_set_dpibr(bus, stream,
 495                                                         stream->lpib);
 496                         snd_hdac_ext_stream_set_lpib(stream, stream->lpib);
 497                 }
 498                 /* fall through */
 499
 500         case SNDRV_PCM_TRIGGER_START:
 501         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 502                 /*
 503                  * Start HOST DMA and Start FE Pipe.This is to make sure that
 504                  * there are no underrun/overrun in the case when the FE
 505                  * pipeline is started but there is a delay in starting the
 506                  * DMA channel on the host.
 507                  */
 508                 ret = skl_decoupled_trigger(substream, cmd);
 509                 if (ret < 0)
 510                         return ret;
 511                 return skl_run_pipe(ctx, mconfig->pipe);
 512                 break;
 513
 514         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 515         case SNDRV_PCM_TRIGGER_SUSPEND:
 516         case SNDRV_PCM_TRIGGER_STOP:
 517                 /*
 518                  * Stop FE Pipe first and stop DMA. This is to make sure that
 519                  * there are no underrun/overrun in the case if there is a delay
 520                  * between the two operations.
 521                  */
 522                 ret = skl_stop_pipe(ctx, mconfig->pipe);
 523                 if (ret < 0)
 524                         return ret;
 525
 526                 ret = skl_decoupled_trigger(substream, cmd);
 527                 if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) {
 528                         /* save the dpib and lpib positions */
 529                         stream->dpib = readl(bus->remap_addr +
 530                                         AZX_REG_VS_SDXDPIB_XBASE +
 531                                         (AZX_REG_VS_SDXDPIB_XINTERVAL *
 532                                         hdac_stream(stream)->index));
 533
 534                         stream->lpib = snd_hdac_stream_get_pos_lpib(
 535                                                         hdac_stream(stream));
 536                         snd_hdac_ext_stream_decouple(bus, stream, false);
 537                 }
 538                 break;
 539
 540         default:
 541                 return -EINVAL;
 542         }
 543
 544         return 0;
 545 }
 546
 547
 548 static int skl_link_hw_params(struct snd_pcm_substream *substream,
 549                                 struct snd_pcm_hw_params *params,
 550                                 struct snd_soc_dai *dai)
 551 {
 552         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 553         struct hdac_ext_stream *link_dev;
 554         struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
 555         struct snd_soc_dai *codec_dai = rtd->codec_dai;
 556         struct skl_pipe_params p_params = {0};
 557         struct hdac_ext_link *link;
 558         int stream_tag;
 559
 560         link_dev = snd_hdac_ext_stream_assign(bus, substream,
 561                                         HDAC_EXT_STREAM_TYPE_LINK);
 562         if (!link_dev)
 563                 return -EBUSY;
 564
 565         snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev);
 566
 567         link = snd_hdac_ext_bus_get_link(bus, codec_dai->component->name);
 568         if (!link)
 569                 return -EINVAL;
 570
 571         stream_tag = hdac_stream(link_dev)->stream_tag;
 572
 573         /* set the stream tag in the codec dai dma params  */
 574         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 575                 snd_soc_dai_set_tdm_slot(codec_dai, stream_tag, 0, 0, 0);
 576         else
 577                 snd_soc_dai_set_tdm_slot(codec_dai, 0, stream_tag, 0, 0);
 578
 579         p_params.s_fmt = snd_pcm_format_width(params_format(params));
 580         p_params.ch = params_channels(params);
 581         p_params.s_freq = params_rate(params);
 582         p_params.stream = substream->stream;
 583         p_params.link_dma_id = stream_tag - 1;
 584         p_params.link_index = link->index;
 585         p_params.format = params_format(params);
 586
 587         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 588                 p_params.link_bps = codec_dai->driver->playback.sig_bits;
 589         else
 590                 p_params.link_bps = codec_dai->driver->capture.sig_bits;
 591
 592         return skl_tplg_be_update_params(dai, &p_params);
 593 }
 594
 595 static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
 596                 struct snd_soc_dai *dai)
 597 {
 598         struct skl *skl = get_skl_ctx(dai->dev);
 599         struct skl_module_cfg *mconfig = NULL;
 600
 601         /* In case of XRUN recovery, reset the FW pipe to clean state */
 602         mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream);
 603         if (mconfig && !mconfig->pipe->passthru &&
 604                 (substream->runtime->status->state == SNDRV_PCM_STATE_XRUN))
 605                 skl_reset_pipe(skl->skl_sst, mconfig->pipe);
 606
 607         return 0;
 608 }
 609
 610 static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
 611         int cmd, struct snd_soc_dai *dai)
 612 {
 613         struct hdac_ext_stream *link_dev =
 614                                 snd_soc_dai_get_dma_data(dai, substream);
 615         struct hdac_bus *bus = get_bus_ctx(substream);
 616         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 617
 618         dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
 619         switch (cmd) {
 620         case SNDRV_PCM_TRIGGER_RESUME:
 621         case SNDRV_PCM_TRIGGER_START:
 622         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 623                 snd_hdac_ext_link_stream_start(link_dev);
 624                 break;
 625
 626         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 627         case SNDRV_PCM_TRIGGER_SUSPEND:
 628         case SNDRV_PCM_TRIGGER_STOP:
 629                 snd_hdac_ext_link_stream_clear(link_dev);
 630                 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
 631                         snd_hdac_ext_stream_decouple(bus, stream, false);
 632                 break;
 633
 634         default:
 635                 return -EINVAL;
 636         }
 637         return 0;
 638 }
 639
 640 static int skl_link_hw_free(struct snd_pcm_substream *substream,
 641                 struct snd_soc_dai *dai)
 642 {
 643         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 644         struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
 645         struct hdac_ext_stream *link_dev =
 646                                 snd_soc_dai_get_dma_data(dai, substream);
 647         struct hdac_ext_link *link;
 648
 649         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 650
 651         link_dev->link_prepared = 0;
 652
 653         link = snd_hdac_ext_bus_get_link(bus, rtd->codec_dai->component->name);
 654         if (!link)
 655                 return -EINVAL;
 656
 657         snd_hdac_ext_link_clear_stream_id(link, hdac_stream(link_dev)->stream_tag);
 658         snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK);
 659         return 0;
 660 }
 661
 662 static const struct snd_soc_dai_ops skl_pcm_dai_ops = {
 663         .startup = skl_pcm_open,
 664         .shutdown = skl_pcm_close,
 665         .prepare = skl_pcm_prepare,
 666         .hw_params = skl_pcm_hw_params,
 667         .hw_free = skl_pcm_hw_free,
 668         .trigger = skl_pcm_trigger,
 669 };
 670
 671 static const struct snd_soc_dai_ops skl_dmic_dai_ops = {
 672         .hw_params = skl_be_hw_params,
 673 };
 674
 675 static const struct snd_soc_dai_ops skl_be_ssp_dai_ops = {
 676         .hw_params = skl_be_hw_params,
 677 };
 678
 679 static const struct snd_soc_dai_ops skl_link_dai_ops = {
 680         .prepare = skl_link_pcm_prepare,
 681         .hw_params = skl_link_hw_params,
 682         .hw_free = skl_link_hw_free,
 683         .trigger = skl_link_pcm_trigger,
 684 };
 685
 686 static struct snd_soc_dai_driver skl_fe_dai[] = {
 687 {
 688         .name = "System Pin",
 689         .ops = &skl_pcm_dai_ops,
 690         .playback = {
 691                 .stream_name = "System Playback",
 692                 .channels_min = HDA_MONO,
 693                 .channels_max = HDA_STEREO,
 694                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
 695                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 696                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 697                 .sig_bits = 32,
 698         },
 699         .capture = {
 700                 .stream_name = "System Capture",
 701                 .channels_min = HDA_MONO,
 702                 .channels_max = HDA_STEREO,
 703                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 704                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 705                 .sig_bits = 32,
 706         },
 707 },
 708 {
 709         .name = "System Pin2",
 710         .ops = &skl_pcm_dai_ops,
 711         .playback = {
 712                 .stream_name = "Headset Playback",
 713                 .channels_min = HDA_MONO,
 714                 .channels_max = HDA_STEREO,
 715                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
 716                         SNDRV_PCM_RATE_8000,
 717                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 718                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 719         },
 720 },
 721 {
 722         .name = "Echoref Pin",
 723         .ops = &skl_pcm_dai_ops,
 724         .capture = {
 725                 .stream_name = "Echoreference Capture",
 726                 .channels_min = HDA_STEREO,
 727                 .channels_max = HDA_STEREO,
 728                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
 729                         SNDRV_PCM_RATE_8000,
 730                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 731                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 732         },
 733 },
 734 {
 735         .name = "Reference Pin",
 736         .ops = &skl_pcm_dai_ops,
 737         .capture = {
 738                 .stream_name = "Reference Capture",
 739                 .channels_min = HDA_MONO,
 740                 .channels_max = HDA_QUAD,
 741                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 742                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 743                 .sig_bits = 32,
 744         },
 745 },
 746 {
 747         .name = "Deepbuffer Pin",
 748         .ops = &skl_pcm_dai_ops,
 749         .playback = {
 750                 .stream_name = "Deepbuffer Playback",
 751                 .channels_min = HDA_STEREO,
 752                 .channels_max = HDA_STEREO,
 753                 .rates = SNDRV_PCM_RATE_48000,
 754                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 755                 .sig_bits = 32,
 756         },
 757 },
 758 {
 759         .name = "LowLatency Pin",
 760         .ops = &skl_pcm_dai_ops,
 761         .playback = {
 762                 .stream_name = "Low Latency Playback",
 763                 .channels_min = HDA_STEREO,
 764                 .channels_max = HDA_STEREO,
 765                 .rates = SNDRV_PCM_RATE_48000,
 766                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 767                 .sig_bits = 32,
 768         },
 769 },
 770 {
 771         .name = "DMIC Pin",
 772         .ops = &skl_pcm_dai_ops,
 773         .capture = {
 774                 .stream_name = "DMIC Capture",
 775                 .channels_min = HDA_MONO,
 776                 .channels_max = HDA_QUAD,
 777                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 778                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 779                 .sig_bits = 32,
 780         },
 781 },
 782 {
 783         .name = "HDMI1 Pin",
 784         .ops = &skl_pcm_dai_ops,
 785         .playback = {
 786                 .stream_name = "HDMI1 Playback",
 787                 .channels_min = HDA_STEREO,
 788                 .channels_max = 8,
 789                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 790                         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 791                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 792                         SNDRV_PCM_RATE_192000,
 793                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 794                         SNDRV_PCM_FMTBIT_S32_LE,
 795                 .sig_bits = 32,
 796         },
 797 },
 798 {
 799         .name = "HDMI2 Pin",
 800         .ops = &skl_pcm_dai_ops,
 801         .playback = {
 802                 .stream_name = "HDMI2 Playback",
 803                 .channels_min = HDA_STEREO,
 804                 .channels_max = 8,
 805                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 806                         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 807                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 808                         SNDRV_PCM_RATE_192000,
 809                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 810                         SNDRV_PCM_FMTBIT_S32_LE,
 811                 .sig_bits = 32,
 812         },
 813 },
 814 {
 815         .name = "HDMI3 Pin",
 816         .ops = &skl_pcm_dai_ops,
 817         .playback = {
 818                 .stream_name = "HDMI3 Playback",
 819                 .channels_min = HDA_STEREO,
 820                 .channels_max = 8,
 821                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 822                         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 823                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 824                         SNDRV_PCM_RATE_192000,
 825                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 826                         SNDRV_PCM_FMTBIT_S32_LE,
 827                 .sig_bits = 32,
 828         },
 829 },
 830 };
 831
 832 /* BE CPU  Dais */
 833 static struct snd_soc_dai_driver skl_platform_dai[] = {
 834 {
 835         .name = "SSP0 Pin",
 836         .ops = &skl_be_ssp_dai_ops,
 837         .playback = {
 838                 .stream_name = "ssp0 Tx",
 839                 .channels_min = HDA_STEREO,
 840                 .channels_max = HDA_STEREO,
 841                 .rates = SNDRV_PCM_RATE_48000,
 842                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 843         },
 844         .capture = {
 845                 .stream_name = "ssp0 Rx",
 846                 .channels_min = HDA_STEREO,
 847                 .channels_max = HDA_STEREO,
 848                 .rates = SNDRV_PCM_RATE_48000,
 849                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 850         },
 851 },
 852 {
 853         .name = "SSP1 Pin",
 854         .ops = &skl_be_ssp_dai_ops,
 855         .playback = {
 856                 .stream_name = "ssp1 Tx",
 857                 .channels_min = HDA_STEREO,
 858                 .channels_max = HDA_STEREO,
 859                 .rates = SNDRV_PCM_RATE_48000,
 860                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 861         },
 862         .capture = {
 863                 .stream_name = "ssp1 Rx",
 864                 .channels_min = HDA_STEREO,
 865                 .channels_max = HDA_STEREO,
 866                 .rates = SNDRV_PCM_RATE_48000,
 867                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 868         },
 869 },
 870 {
 871         .name = "SSP2 Pin",
 872         .ops = &skl_be_ssp_dai_ops,
 873         .playback = {
 874                 .stream_name = "ssp2 Tx",
 875                 .channels_min = HDA_STEREO,
 876                 .channels_max = HDA_STEREO,
 877                 .rates = SNDRV_PCM_RATE_48000,
 878                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 879         },
 880         .capture = {
 881                 .stream_name = "ssp2 Rx",
 882                 .channels_min = HDA_STEREO,
 883                 .channels_max = HDA_STEREO,
 884                 .rates = SNDRV_PCM_RATE_48000,
 885                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 886         },
 887 },
 888 {
 889         .name = "SSP3 Pin",
 890         .ops = &skl_be_ssp_dai_ops,
 891         .playback = {
 892                 .stream_name = "ssp3 Tx",
 893                 .channels_min = HDA_STEREO,
 894                 .channels_max = HDA_STEREO,
 895                 .rates = SNDRV_PCM_RATE_48000,
 896                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 897         },
 898         .capture = {
 899                 .stream_name = "ssp3 Rx",
 900                 .channels_min = HDA_STEREO,
 901                 .channels_max = HDA_STEREO,
 902                 .rates = SNDRV_PCM_RATE_48000,
 903                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 904         },
 905 },
 906 {
 907         .name = "SSP4 Pin",
 908         .ops = &skl_be_ssp_dai_ops,
 909         .playback = {
 910                 .stream_name = "ssp4 Tx",
 911                 .channels_min = HDA_STEREO,
 912                 .channels_max = HDA_STEREO,
 913                 .rates = SNDRV_PCM_RATE_48000,
 914                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 915         },
 916         .capture = {
 917                 .stream_name = "ssp4 Rx",
 918                 .channels_min = HDA_STEREO,
 919                 .channels_max = HDA_STEREO,
 920                 .rates = SNDRV_PCM_RATE_48000,
 921                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 922         },
 923 },
 924 {
 925         .name = "SSP5 Pin",
 926         .ops = &skl_be_ssp_dai_ops,
 927         .playback = {
 928                 .stream_name = "ssp5 Tx",
 929                 .channels_min = HDA_STEREO,
 930                 .channels_max = HDA_STEREO,
 931                 .rates = SNDRV_PCM_RATE_48000,
 932                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 933         },
 934         .capture = {
 935                 .stream_name = "ssp5 Rx",
 936                 .channels_min = HDA_STEREO,
 937                 .channels_max = HDA_STEREO,
 938                 .rates = SNDRV_PCM_RATE_48000,
 939                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 940         },
 941 },
 942 {
 943         .name = "iDisp1 Pin",
 944         .ops = &skl_link_dai_ops,
 945         .playback = {
 946                 .stream_name = "iDisp1 Tx",
 947                 .channels_min = HDA_STEREO,
 948                 .channels_max = 8,
 949                 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000,
 950                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
 951                         SNDRV_PCM_FMTBIT_S24_LE,
 952         },
 953 },
 954 {
 955         .name = "iDisp2 Pin",
 956         .ops = &skl_link_dai_ops,
 957         .playback = {
 958                 .stream_name = "iDisp2 Tx",
 959                 .channels_min = HDA_STEREO,
 960                 .channels_max = 8,
 961                 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
 962                         SNDRV_PCM_RATE_48000,
 963                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
 964                         SNDRV_PCM_FMTBIT_S24_LE,
 965         },
 966 },
 967 {
 968         .name = "iDisp3 Pin",
 969         .ops = &skl_link_dai_ops,
 970         .playback = {
 971                 .stream_name = "iDisp3 Tx",
 972                 .channels_min = HDA_STEREO,
 973                 .channels_max = 8,
 974                 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
 975                         SNDRV_PCM_RATE_48000,
 976                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
 977                         SNDRV_PCM_FMTBIT_S24_LE,
 978         },
 979 },
 980 {
 981         .name = "DMIC01 Pin",
 982         .ops = &skl_dmic_dai_ops,
 983         .capture = {
 984                 .stream_name = "DMIC01 Rx",
 985                 .channels_min = HDA_MONO,
 986                 .channels_max = HDA_QUAD,
 987                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 988                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 989         },
 990 },
 991 {
 992         .name = "DMIC16k Pin",
 993         .ops = &skl_dmic_dai_ops,
 994         .capture = {
 995                 .stream_name = "DMIC16k Rx",
 996                 .channels_min = HDA_MONO,
 997                 .channels_max = HDA_QUAD,
 998                 .rates = SNDRV_PCM_RATE_16000,
 999                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1000         },
1001 },
1002 {
1003         .name = "Analog CPU DAI",
1004         .ops = &skl_link_dai_ops,
1005         .playback = {
1006                 .stream_name = "Analog CPU Playback",
1007                 .channels_min = HDA_MONO,
1008                 .channels_max = HDA_MAX,
1009                 .rates = SNDRV_PCM_RATE_8000_192000,
1010                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1011                         SNDRV_PCM_FMTBIT_S32_LE,
1012         },
1013         .capture = {
1014                 .stream_name = "Analog CPU Capture",
1015                 .channels_min = HDA_MONO,
1016                 .channels_max = HDA_MAX,
1017                 .rates = SNDRV_PCM_RATE_8000_192000,
1018                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1019                         SNDRV_PCM_FMTBIT_S32_LE,
1020         },
1021 },
1022 {
1023         .name = "Alt Analog CPU DAI",
1024         .ops = &skl_link_dai_ops,
1025         .playback = {
1026                 .stream_name = "Alt Analog CPU Playback",
1027                 .channels_min = HDA_MONO,
1028                 .channels_max = HDA_MAX,
1029                 .rates = SNDRV_PCM_RATE_8000_192000,
1030                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1031                         SNDRV_PCM_FMTBIT_S32_LE,
1032         },
1033         .capture = {
1034                 .stream_name = "Alt Analog CPU Capture",
1035                 .channels_min = HDA_MONO,
1036                 .channels_max = HDA_MAX,
1037                 .rates = SNDRV_PCM_RATE_8000_192000,
1038                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1039                         SNDRV_PCM_FMTBIT_S32_LE,
1040         },
1041 },
1042 {
1043         .name = "Digital CPU DAI",
1044         .ops = &skl_link_dai_ops,
1045         .playback = {
1046                 .stream_name = "Digital CPU Playback",
1047                 .channels_min = HDA_MONO,
1048                 .channels_max = HDA_MAX,
1049                 .rates = SNDRV_PCM_RATE_8000_192000,
1050                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1051                         SNDRV_PCM_FMTBIT_S32_LE,
1052         },
1053         .capture = {
1054                 .stream_name = "Digital CPU Capture",
1055                 .channels_min = HDA_MONO,
1056                 .channels_max = HDA_MAX,
1057                 .rates = SNDRV_PCM_RATE_8000_192000,
1058                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1059                         SNDRV_PCM_FMTBIT_S32_LE,
1060         },
1061 },
1062 };
1063
1064 int skl_dai_load(struct snd_soc_component *cmp, int index,
1065                         struct snd_soc_dai_driver *dai_drv,
1066                         struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai)
1067 {
1068         dai_drv->ops = &skl_pcm_dai_ops;
1069
1070         return 0;
1071 }
1072
1073 static int skl_platform_open(struct snd_pcm_substream *substream)
1074 {
1075         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1076         struct snd_soc_dai_link *dai_link = rtd->dai_link;
1077
1078         dev_dbg(rtd->cpu_dai->dev, "In %s:%s\n", __func__,
1079                                         dai_link->cpu_dai_name);
1080
1081         snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw);
1082
1083         return 0;
1084 }
1085
1086 static int skl_coupled_trigger(struct snd_pcm_substream *substream,
1087                                         int cmd)
1088 {
1089         struct hdac_bus *bus = get_bus_ctx(substream);
1090         struct hdac_ext_stream *stream;
1091         struct snd_pcm_substream *s;
1092         bool start;
1093         int sbits = 0;
1094         unsigned long cookie;
1095         struct hdac_stream *hstr;
1096
1097         stream = get_hdac_ext_stream(substream);
1098         hstr = hdac_stream(stream);
1099
1100         dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd);
1101
1102         if (!hstr->prepared)
1103                 return -EPIPE;
1104
1105         switch (cmd) {
1106         case SNDRV_PCM_TRIGGER_START:
1107         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1108         case SNDRV_PCM_TRIGGER_RESUME:
1109                 start = true;
1110                 break;
1111
1112         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1113         case SNDRV_PCM_TRIGGER_SUSPEND:
1114         case SNDRV_PCM_TRIGGER_STOP:
1115                 start = false;
1116                 break;
1117
1118         default:
1119                 return -EINVAL;
1120         }
1121
1122         snd_pcm_group_for_each_entry(s, substream) {
1123                 if (s->pcm->card != substream->pcm->card)
1124                         continue;
1125                 stream = get_hdac_ext_stream(s);
1126                 sbits |= 1 << hdac_stream(stream)->index;
1127                 snd_pcm_trigger_done(s, substream);
1128         }
1129
1130         spin_lock_irqsave(&bus->reg_lock, cookie);
1131
1132         /* first, set SYNC bits of corresponding streams */
1133         snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC);
1134
1135         snd_pcm_group_for_each_entry(s, substream) {
1136                 if (s->pcm->card != substream->pcm->card)
1137                         continue;
1138                 stream = get_hdac_ext_stream(s);
1139                 if (start)
1140                         snd_hdac_stream_start(hdac_stream(stream), true);
1141                 else
1142                         snd_hdac_stream_stop(hdac_stream(stream));
1143         }
1144         spin_unlock_irqrestore(&bus->reg_lock, cookie);
1145
1146         snd_hdac_stream_sync(hstr, start, sbits);
1147
1148         spin_lock_irqsave(&bus->reg_lock, cookie);
1149
1150         /* reset SYNC bits */
1151         snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC);
1152         if (start)
1153                 snd_hdac_stream_timecounter_init(hstr, sbits);
1154         spin_unlock_irqrestore(&bus->reg_lock, cookie);
1155
1156         return 0;
1157 }
1158
1159 static int skl_platform_pcm_trigger(struct snd_pcm_substream *substream,
1160                                         int cmd)
1161 {
1162         struct hdac_bus *bus = get_bus_ctx(substream);
1163
1164         if (!bus->ppcap)
1165                 return skl_coupled_trigger(substream, cmd);
1166
1167         return 0;
1168 }
1169
1170 static snd_pcm_uframes_t skl_platform_pcm_pointer
1171                         (struct snd_pcm_substream *substream)
1172 {
1173         struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream);
1174         struct hdac_bus *bus = get_bus_ctx(substream);
1175         unsigned int pos;
1176
1177         /*
1178          * Use DPIB for Playback stream as the periodic DMA Position-in-
1179          * Buffer Writes may be scheduled at the same time or later than
1180          * the MSI and does not guarantee to reflect the Position of the
1181          * last buffer that was transferred. Whereas DPIB register in
1182          * HAD space reflects the actual data that is transferred.
1183          * Use the position buffer for capture, as DPIB write gets
1184          * completed earlier than the actual data written to the DDR.
1185          *
1186          * For capture stream following workaround is required to fix the
1187          * incorrect position reporting.
1188          *
1189          * 1. Wait for 20us before reading the DMA position in buffer once
1190          * the interrupt is generated for stream completion as update happens
1191          * on the HDA frame boundary i.e. 20.833uSec.
1192          * 2. Read DPIB register to flush the DMA position value. This dummy
1193          * read is required to flush DMA position value.
1194          * 3. Read the DMA Position-in-Buffer. This value now will be equal to
1195          * or greater than period boundary.
1196          */
1197
1198         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1199                 pos = readl(bus->remap_addr + AZX_REG_VS_SDXDPIB_XBASE +
1200                                 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1201                                 hdac_stream(hstream)->index));
1202         } else {
1203                 udelay(20);
1204                 readl(bus->remap_addr +
1205                                 AZX_REG_VS_SDXDPIB_XBASE +
1206                                 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1207                                  hdac_stream(hstream)->index));
1208                 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
1209         }
1210
1211         if (pos >= hdac_stream(hstream)->bufsize)
1212                 pos = 0;
1213
1214         return bytes_to_frames(substream->runtime, pos);
1215 }
1216
1217 static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
1218                                 u64 nsec)
1219 {
1220         struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
1221         struct snd_soc_dai *codec_dai = rtd->codec_dai;
1222         u64 codec_frames, codec_nsecs;
1223
1224         if (!codec_dai->driver->ops->delay)
1225                 return nsec;
1226
1227         codec_frames = codec_dai->driver->ops->delay(substream, codec_dai);
1228         codec_nsecs = div_u64(codec_frames * 1000000000LL,
1229                               substream->runtime->rate);
1230
1231         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1232                 return nsec + codec_nsecs;
1233
1234         return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1235 }
1236
1237 static int skl_get_time_info(struct snd_pcm_substream *substream,
1238                         struct timespec *system_ts, struct timespec *audio_ts,
1239                         struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
1240                         struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
1241 {
1242         struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream);
1243         struct hdac_stream *hstr = hdac_stream(sstream);
1244         u64 nsec;
1245
1246         if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
1247                 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
1248
1249                 snd_pcm_gettime(substream->runtime, system_ts);
1250
1251                 nsec = timecounter_read(&hstr->tc);
1252                 nsec = div_u64(nsec, 3); /* can be optimized */
1253                 if (audio_tstamp_config->report_delay)
1254                         nsec = skl_adjust_codec_delay(substream, nsec);
1255
1256                 *audio_ts = ns_to_timespec(nsec);
1257
1258                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
1259                 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */
1260                 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */
1261
1262         } else {
1263                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
1264         }
1265
1266         return 0;
1267 }
1268
1269 static const struct snd_pcm_ops skl_platform_ops = {
1270         .open = skl_platform_open,
1271         .ioctl = snd_pcm_lib_ioctl,
1272         .trigger = skl_platform_pcm_trigger,
1273         .pointer = skl_platform_pcm_pointer,
1274         .get_time_info =  skl_get_time_info,
1275         .mmap = snd_pcm_lib_default_mmap,
1276         .page = snd_pcm_sgbuf_ops_page,
1277 };
1278
1279 static void skl_pcm_free(struct snd_pcm *pcm)
1280 {
1281         snd_pcm_lib_preallocate_free_for_all(pcm);
1282 }
1283
1284 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
1285
1286 static int skl_pcm_new(struct snd_soc_pcm_runtime *rtd)
1287 {
1288         struct snd_soc_dai *dai = rtd->cpu_dai;
1289         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
1290         struct snd_pcm *pcm = rtd->pcm;
1291         unsigned int size;
1292         struct skl *skl = bus_to_skl(bus);
1293
1294         if (dai->driver->playback.channels_min ||
1295                 dai->driver->capture.channels_min) {
1296                 /* buffer pre-allocation */
1297                 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
1298                 if (size > MAX_PREALLOC_SIZE)
1299                         size = MAX_PREALLOC_SIZE;
1300                 snd_pcm_lib_preallocate_pages_for_all(pcm,
1301                                                 SNDRV_DMA_TYPE_DEV_SG,
1302                                                 snd_dma_pci_data(skl->pci),
1303                                                 size, MAX_PREALLOC_SIZE);
1304         }
1305
1306         return 0;
1307 }
1308
1309 static int skl_get_module_info(struct skl *skl, struct skl_module_cfg *mconfig)
1310 {
1311         struct skl_sst *ctx = skl->skl_sst;
1312         struct skl_module_inst_id *pin_id;
1313         uuid_le *uuid_mod, *uuid_tplg;
1314         struct skl_module *skl_module;
1315         struct uuid_module *module;
1316         int i, ret = -EIO;
1317
1318         uuid_mod = (uuid_le *)mconfig->guid;
1319
1320         if (list_empty(&ctx->uuid_list)) {
1321                 dev_err(ctx->dev, "Module list is empty\n");
1322                 return -EIO;
1323         }
1324
1325         list_for_each_entry(module, &ctx->uuid_list, list) {
1326                 if (uuid_le_cmp(*uuid_mod, module->uuid) == 0) {
1327                         mconfig->id.module_id = module->id;
1328                         if (mconfig->module)
1329                                 mconfig->module->loadable = module->is_loadable;
1330                         ret = 0;
1331                         break;
1332                 }
1333         }
1334
1335         if (ret)
1336                 return ret;
1337
1338         uuid_mod = &module->uuid;
1339         ret = -EIO;
1340         for (i = 0; i < skl->nr_modules; i++) {
1341                 skl_module = skl->modules[i];
1342                 uuid_tplg = &skl_module->uuid;
1343                 if (!uuid_le_cmp(*uuid_mod, *uuid_tplg)) {
1344                         mconfig->module = skl_module;
1345                         ret = 0;
1346                         break;
1347                 }
1348         }
1349         if (skl->nr_modules && ret)
1350                 return ret;
1351
1352         list_for_each_entry(module, &ctx->uuid_list, list) {
1353                 for (i = 0; i < MAX_IN_QUEUE; i++) {
1354                         pin_id = &mconfig->m_in_pin[i].id;
1355                         if (!uuid_le_cmp(pin_id->mod_uuid, module->uuid))
1356                                 pin_id->module_id = module->id;
1357                 }
1358
1359                 for (i = 0; i < MAX_OUT_QUEUE; i++) {
1360                         pin_id = &mconfig->m_out_pin[i].id;
1361                         if (!uuid_le_cmp(pin_id->mod_uuid, module->uuid))
1362                                 pin_id->module_id = module->id;
1363                 }
1364         }
1365
1366         return 0;
1367 }
1368
1369 static int skl_populate_modules(struct skl *skl)
1370 {
1371         struct skl_pipeline *p;
1372         struct skl_pipe_module *m;
1373         struct snd_soc_dapm_widget *w;
1374         struct skl_module_cfg *mconfig;
1375         int ret = 0;
1376
1377         list_for_each_entry(p, &skl->ppl_list, node) {
1378                 list_for_each_entry(m, &p->pipe->w_list, node) {
1379                         w = m->w;
1380                         mconfig = w->priv;
1381
1382                         ret = skl_get_module_info(skl, mconfig);
1383                         if (ret < 0) {
1384                                 dev_err(skl->skl_sst->dev,
1385                                         "query module info failed\n");
1386                                 return ret;
1387                         }
1388
1389                         skl_tplg_add_moduleid_in_bind_params(skl, w);
1390                 }
1391         }
1392
1393         return ret;
1394 }
1395
1396 static int skl_platform_soc_probe(struct snd_soc_component *component)
1397 {
1398         struct hdac_bus *bus = dev_get_drvdata(component->dev);
1399         struct skl *skl = bus_to_skl(bus);
1400         const struct skl_dsp_ops *ops;
1401         int ret;
1402
1403         pm_runtime_get_sync(component->dev);
1404         if (bus->ppcap) {
1405                 skl->component = component;
1406
1407                 /* init debugfs */
1408                 skl->debugfs = skl_debugfs_init(skl);
1409
1410                 ret = skl_tplg_init(component, bus);
1411                 if (ret < 0) {
1412                         dev_err(component->dev, "Failed to init topology!\n");
1413                         return ret;
1414                 }
1415
1416                 /* load the firmwares, since all is set */
1417                 ops = skl_get_dsp_ops(skl->pci->device);
1418                 if (!ops)
1419                         return -EIO;
1420
1421                 if (!skl->skl_sst->is_first_boot) {
1422                         dev_err(component->dev, "DSP reports first boot done!!!\n");
1423                         return -EIO;
1424                 }
1425
1426                 /*
1427                  * Disable dynamic clock and power gating during firmware
1428                  * and library download
1429                  */
1430                 skl->skl_sst->enable_miscbdcge(component->dev, false);
1431                 skl->skl_sst->clock_power_gating(component->dev, false);
1432
1433                 ret = ops->init_fw(component->dev, skl->skl_sst);
1434                 skl->skl_sst->enable_miscbdcge(component->dev, true);
1435                 skl->skl_sst->clock_power_gating(component->dev, true);
1436                 if (ret < 0) {
1437                         dev_err(component->dev, "Failed to boot first fw: %d\n", ret);
1438                         return ret;
1439                 }
1440                 skl_populate_modules(skl);
1441                 skl->skl_sst->update_d0i3c = skl_update_d0i3c;
1442                 skl_dsp_enable_notification(skl->skl_sst, false);
1443
1444                 if (skl->cfg.astate_cfg != NULL) {
1445                         skl_dsp_set_astate_cfg(skl->skl_sst,
1446                                         skl->cfg.astate_cfg->count,
1447                                         skl->cfg.astate_cfg);
1448                 }
1449         }
1450         pm_runtime_mark_last_busy(component->dev);
1451         pm_runtime_put_autosuspend(component->dev);
1452
1453         return 0;
1454 }
1455
1456 static const struct snd_soc_component_driver skl_component  = {
1457         .name           = "pcm",
1458         .probe          = skl_platform_soc_probe,
1459         .ops            = &skl_platform_ops,
1460         .pcm_new        = skl_pcm_new,
1461         .pcm_free       = skl_pcm_free,
1462         .ignore_module_refcount = 1, /* do not increase the refcount in core */
1463 };
1464
1465 int skl_platform_register(struct device *dev)
1466 {
1467         int ret;
1468         struct snd_soc_dai_driver *dais;
1469         int num_dais = ARRAY_SIZE(skl_platform_dai);
1470         struct hdac_bus *bus = dev_get_drvdata(dev);
1471         struct skl *skl = bus_to_skl(bus);
1472
1473         INIT_LIST_HEAD(&skl->ppl_list);
1474         INIT_LIST_HEAD(&skl->bind_list);
1475
1476         skl->dais = kmemdup(skl_platform_dai, sizeof(skl_platform_dai),
1477                             GFP_KERNEL);
1478         if (!skl->dais) {
1479                 ret = -ENOMEM;
1480                 goto err;
1481         }
1482
1483         if (!skl->use_tplg_pcm) {
1484                 dais = krealloc(skl->dais, sizeof(skl_fe_dai) +
1485                                 sizeof(skl_platform_dai), GFP_KERNEL);
1486                 if (!dais) {
1487                         ret = -ENOMEM;
1488                         goto err;
1489                 }
1490
1491                 skl->dais = dais;
1492                 memcpy(&skl->dais[ARRAY_SIZE(skl_platform_dai)], skl_fe_dai,
1493                        sizeof(skl_fe_dai));
1494                 num_dais += ARRAY_SIZE(skl_fe_dai);
1495         }
1496
1497         ret = devm_snd_soc_register_component(dev, &skl_component,
1498                                          skl->dais, num_dais);
1499         if (ret)
1500                 dev_err(dev, "soc component registration failed %d\n", ret);
1501 err:
1502         return ret;
1503 }
1504
1505 int skl_platform_unregister(struct device *dev)
1506 {
1507         struct hdac_bus *bus = dev_get_drvdata(dev);
1508         struct skl *skl = bus_to_skl(bus);
1509         struct skl_module_deferred_bind *modules, *tmp;
1510
1511         if (!list_empty(&skl->bind_list)) {
1512                 list_for_each_entry_safe(modules, tmp, &skl->bind_list, node) {
1513                         list_del(&modules->node);
1514                         kfree(modules);
1515                 }
1516         }
1517
1518         kfree(skl->dais);
1519
1520         return 0;
1521 }