1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel Smart Sound Technology (SST) DSP Core Driver
5 * Copyright (C) 2013, Intel Corporation. All rights reserved.
8 #include <linux/slab.h>
9 #include <linux/export.h>
10 #include <linux/interrupt.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/io-64-nonatomic-lo-hi.h>
14 #include <linux/delay.h>
17 #include "sst-dsp-priv.h"
19 #define CREATE_TRACE_POINTS
20 #include <trace/events/intel-sst.h>
22 /* Internal generic low-level SST IO functions - can be overidden */
23 void sst_shim32_write(void __iomem *addr, u32 offset, u32 value)
25 writel(value, addr + offset);
27 EXPORT_SYMBOL_GPL(sst_shim32_write);
29 u32 sst_shim32_read(void __iomem *addr, u32 offset)
31 return readl(addr + offset);
33 EXPORT_SYMBOL_GPL(sst_shim32_read);
35 void sst_shim32_write64(void __iomem *addr, u32 offset, u64 value)
37 writeq(value, addr + offset);
39 EXPORT_SYMBOL_GPL(sst_shim32_write64);
41 u64 sst_shim32_read64(void __iomem *addr, u32 offset)
43 return readq(addr + offset);
45 EXPORT_SYMBOL_GPL(sst_shim32_read64);
47 static inline void _sst_memcpy_toio_32(volatile u32 __iomem *dest,
48 u32 *src, size_t bytes)
50 int i, words = bytes >> 2;
52 for (i = 0; i < words; i++)
53 writel(src[i], dest + i);
56 static inline void _sst_memcpy_fromio_32(u32 *dest,
57 const volatile __iomem u32 *src, size_t bytes)
59 int i, words = bytes >> 2;
61 for (i = 0; i < words; i++)
62 dest[i] = readl(src + i);
65 void sst_memcpy_toio_32(struct sst_dsp *sst,
66 void __iomem *dest, void *src, size_t bytes)
68 _sst_memcpy_toio_32(dest, src, bytes);
70 EXPORT_SYMBOL_GPL(sst_memcpy_toio_32);
72 void sst_memcpy_fromio_32(struct sst_dsp *sst, void *dest,
73 void __iomem *src, size_t bytes)
75 _sst_memcpy_fromio_32(dest, src, bytes);
77 EXPORT_SYMBOL_GPL(sst_memcpy_fromio_32);
80 void sst_dsp_shim_write(struct sst_dsp *sst, u32 offset, u32 value)
84 spin_lock_irqsave(&sst->spinlock, flags);
85 sst->ops->write(sst->addr.shim, offset, value);
86 spin_unlock_irqrestore(&sst->spinlock, flags);
88 EXPORT_SYMBOL_GPL(sst_dsp_shim_write);
90 u32 sst_dsp_shim_read(struct sst_dsp *sst, u32 offset)
95 spin_lock_irqsave(&sst->spinlock, flags);
96 val = sst->ops->read(sst->addr.shim, offset);
97 spin_unlock_irqrestore(&sst->spinlock, flags);
101 EXPORT_SYMBOL_GPL(sst_dsp_shim_read);
103 void sst_dsp_shim_write64(struct sst_dsp *sst, u32 offset, u64 value)
107 spin_lock_irqsave(&sst->spinlock, flags);
108 sst->ops->write64(sst->addr.shim, offset, value);
109 spin_unlock_irqrestore(&sst->spinlock, flags);
111 EXPORT_SYMBOL_GPL(sst_dsp_shim_write64);
113 u64 sst_dsp_shim_read64(struct sst_dsp *sst, u32 offset)
118 spin_lock_irqsave(&sst->spinlock, flags);
119 val = sst->ops->read64(sst->addr.shim, offset);
120 spin_unlock_irqrestore(&sst->spinlock, flags);
124 EXPORT_SYMBOL_GPL(sst_dsp_shim_read64);
126 void sst_dsp_shim_write_unlocked(struct sst_dsp *sst, u32 offset, u32 value)
128 sst->ops->write(sst->addr.shim, offset, value);
130 EXPORT_SYMBOL_GPL(sst_dsp_shim_write_unlocked);
132 u32 sst_dsp_shim_read_unlocked(struct sst_dsp *sst, u32 offset)
134 return sst->ops->read(sst->addr.shim, offset);
136 EXPORT_SYMBOL_GPL(sst_dsp_shim_read_unlocked);
138 void sst_dsp_shim_write64_unlocked(struct sst_dsp *sst, u32 offset, u64 value)
140 sst->ops->write64(sst->addr.shim, offset, value);
142 EXPORT_SYMBOL_GPL(sst_dsp_shim_write64_unlocked);
144 u64 sst_dsp_shim_read64_unlocked(struct sst_dsp *sst, u32 offset)
146 return sst->ops->read64(sst->addr.shim, offset);
148 EXPORT_SYMBOL_GPL(sst_dsp_shim_read64_unlocked);
150 int sst_dsp_shim_update_bits_unlocked(struct sst_dsp *sst, u32 offset,
154 unsigned int old, new;
157 ret = sst_dsp_shim_read_unlocked(sst, offset);
160 new = (old & (~mask)) | (value & mask);
162 change = (old != new);
164 sst_dsp_shim_write_unlocked(sst, offset, new);
168 EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits_unlocked);
170 int sst_dsp_shim_update_bits64_unlocked(struct sst_dsp *sst, u32 offset,
176 old = sst_dsp_shim_read64_unlocked(sst, offset);
178 new = (old & (~mask)) | (value & mask);
180 change = (old != new);
182 sst_dsp_shim_write64_unlocked(sst, offset, new);
186 EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits64_unlocked);
188 /* This is for registers bits with attribute RWC */
189 void sst_dsp_shim_update_bits_forced_unlocked(struct sst_dsp *sst, u32 offset,
192 unsigned int old, new;
195 ret = sst_dsp_shim_read_unlocked(sst, offset);
198 new = (old & (~mask)) | (value & mask);
200 sst_dsp_shim_write_unlocked(sst, offset, new);
202 EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits_forced_unlocked);
204 int sst_dsp_shim_update_bits(struct sst_dsp *sst, u32 offset,
210 spin_lock_irqsave(&sst->spinlock, flags);
211 change = sst_dsp_shim_update_bits_unlocked(sst, offset, mask, value);
212 spin_unlock_irqrestore(&sst->spinlock, flags);
215 EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits);
217 int sst_dsp_shim_update_bits64(struct sst_dsp *sst, u32 offset,
223 spin_lock_irqsave(&sst->spinlock, flags);
224 change = sst_dsp_shim_update_bits64_unlocked(sst, offset, mask, value);
225 spin_unlock_irqrestore(&sst->spinlock, flags);
228 EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits64);
230 /* This is for registers bits with attribute RWC */
231 void sst_dsp_shim_update_bits_forced(struct sst_dsp *sst, u32 offset,
236 spin_lock_irqsave(&sst->spinlock, flags);
237 sst_dsp_shim_update_bits_forced_unlocked(sst, offset, mask, value);
238 spin_unlock_irqrestore(&sst->spinlock, flags);
240 EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits_forced);
242 int sst_dsp_register_poll(struct sst_dsp *ctx, u32 offset, u32 mask,
243 u32 target, u32 time, char *operation)
246 unsigned long timeout;
250 * split the loop into sleeps of varying resolution. more accurately,
251 * the range of wakeups are:
252 * Phase 1(first 5ms): min sleep 0.5ms; max sleep 1ms.
253 * Phase 2:( 5ms to 10ms) : min sleep 0.5ms; max sleep 10ms
254 * (usleep_range (500, 1000) and usleep_range(5000, 10000) are
255 * both possible in this phase depending on whether k > 10 or not).
256 * Phase 3: (beyond 10 ms) min sleep 5ms; max sleep 10ms.
259 timeout = jiffies + msecs_to_jiffies(time);
260 while ((((reg = sst_dsp_shim_read_unlocked(ctx, offset)) & mask) != target)
261 && time_before(jiffies, timeout)) {
266 usleep_range(s, 2*s);
269 if ((reg & mask) == target) {
270 dev_dbg(ctx->dev, "FW Poll Status: reg=%#x %s successful\n",
276 dev_dbg(ctx->dev, "FW Poll Status: reg=%#x %s timedout\n",
280 EXPORT_SYMBOL_GPL(sst_dsp_register_poll);
282 void sst_dsp_dump(struct sst_dsp *sst)
287 EXPORT_SYMBOL_GPL(sst_dsp_dump);
289 void sst_dsp_reset(struct sst_dsp *sst)
292 sst->ops->reset(sst);
294 EXPORT_SYMBOL_GPL(sst_dsp_reset);
296 int sst_dsp_boot(struct sst_dsp *sst)
303 EXPORT_SYMBOL_GPL(sst_dsp_boot);
305 int sst_dsp_wake(struct sst_dsp *sst)
308 return sst->ops->wake(sst);
312 EXPORT_SYMBOL_GPL(sst_dsp_wake);
314 void sst_dsp_sleep(struct sst_dsp *sst)
317 sst->ops->sleep(sst);
319 EXPORT_SYMBOL_GPL(sst_dsp_sleep);
321 void sst_dsp_stall(struct sst_dsp *sst)
324 sst->ops->stall(sst);
326 EXPORT_SYMBOL_GPL(sst_dsp_stall);
328 void sst_dsp_ipc_msg_tx(struct sst_dsp *dsp, u32 msg)
330 sst_dsp_shim_write_unlocked(dsp, SST_IPCX, msg | SST_IPCX_BUSY);
331 trace_sst_ipc_msg_tx(msg);
333 EXPORT_SYMBOL_GPL(sst_dsp_ipc_msg_tx);
335 u32 sst_dsp_ipc_msg_rx(struct sst_dsp *dsp)
339 msg = sst_dsp_shim_read_unlocked(dsp, SST_IPCX);
340 trace_sst_ipc_msg_rx(msg);
344 EXPORT_SYMBOL_GPL(sst_dsp_ipc_msg_rx);
346 int sst_dsp_mailbox_init(struct sst_dsp *sst, u32 inbox_offset, size_t inbox_size,
347 u32 outbox_offset, size_t outbox_size)
349 sst->mailbox.in_base = sst->addr.lpe + inbox_offset;
350 sst->mailbox.out_base = sst->addr.lpe + outbox_offset;
351 sst->mailbox.in_size = inbox_size;
352 sst->mailbox.out_size = outbox_size;
355 EXPORT_SYMBOL_GPL(sst_dsp_mailbox_init);
357 void sst_dsp_outbox_write(struct sst_dsp *sst, void *message, size_t bytes)
361 trace_sst_ipc_outbox_write(bytes);
363 memcpy_toio(sst->mailbox.out_base, message, bytes);
365 for (i = 0; i < bytes; i += 4)
366 trace_sst_ipc_outbox_wdata(i, *(u32 *)(message + i));
368 EXPORT_SYMBOL_GPL(sst_dsp_outbox_write);
370 void sst_dsp_outbox_read(struct sst_dsp *sst, void *message, size_t bytes)
374 trace_sst_ipc_outbox_read(bytes);
376 memcpy_fromio(message, sst->mailbox.out_base, bytes);
378 for (i = 0; i < bytes; i += 4)
379 trace_sst_ipc_outbox_rdata(i, *(u32 *)(message + i));
381 EXPORT_SYMBOL_GPL(sst_dsp_outbox_read);
383 void sst_dsp_inbox_write(struct sst_dsp *sst, void *message, size_t bytes)
387 trace_sst_ipc_inbox_write(bytes);
389 memcpy_toio(sst->mailbox.in_base, message, bytes);
391 for (i = 0; i < bytes; i += 4)
392 trace_sst_ipc_inbox_wdata(i, *(u32 *)(message + i));
394 EXPORT_SYMBOL_GPL(sst_dsp_inbox_write);
396 void sst_dsp_inbox_read(struct sst_dsp *sst, void *message, size_t bytes)
400 trace_sst_ipc_inbox_read(bytes);
402 memcpy_fromio(message, sst->mailbox.in_base, bytes);
404 for (i = 0; i < bytes; i += 4)
405 trace_sst_ipc_inbox_rdata(i, *(u32 *)(message + i));
407 EXPORT_SYMBOL_GPL(sst_dsp_inbox_read);
409 /* Module information */
410 MODULE_AUTHOR("Liam Girdwood");
411 MODULE_DESCRIPTION("Intel SST Core");
412 MODULE_LICENSE("GPL v2");