1 // SPDX-License-Identifier: GPL-2.0-only
3 // Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
5 // Authors: Cezary Rojewski <cezary.rojewski@intel.com>
6 // Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
9 #include <linux/module.h>
10 #include <sound/hdaudio_ext.h>
12 #include "registers.h"
14 #define AVS_ADSPCS_INTERVAL_US 500
15 #define AVS_ADSPCS_TIMEOUT_US 50000
17 int avs_dsp_core_power(struct avs_dev *adev, u32 core_mask, bool power)
22 mask = AVS_ADSPCS_SPA_MASK(core_mask);
23 value = power ? mask : 0;
25 snd_hdac_adsp_updatel(adev, AVS_ADSP_REG_ADSPCS, mask, value);
27 mask = AVS_ADSPCS_CPA_MASK(core_mask);
28 value = power ? mask : 0;
30 ret = snd_hdac_adsp_readl_poll(adev, AVS_ADSP_REG_ADSPCS,
31 reg, (reg & mask) == value,
32 AVS_ADSPCS_INTERVAL_US,
33 AVS_ADSPCS_TIMEOUT_US);
35 dev_err(adev->dev, "core_mask %d power %s failed: %d\n",
36 core_mask, power ? "on" : "off", ret);
41 int avs_dsp_core_reset(struct avs_dev *adev, u32 core_mask, bool reset)
46 mask = AVS_ADSPCS_CRST_MASK(core_mask);
47 value = reset ? mask : 0;
49 snd_hdac_adsp_updatel(adev, AVS_ADSP_REG_ADSPCS, mask, value);
51 ret = snd_hdac_adsp_readl_poll(adev, AVS_ADSP_REG_ADSPCS,
52 reg, (reg & mask) == value,
53 AVS_ADSPCS_INTERVAL_US,
54 AVS_ADSPCS_TIMEOUT_US);
56 dev_err(adev->dev, "core_mask %d %s reset failed: %d\n",
57 core_mask, reset ? "enter" : "exit", ret);
62 int avs_dsp_core_stall(struct avs_dev *adev, u32 core_mask, bool stall)
67 mask = AVS_ADSPCS_CSTALL_MASK(core_mask);
68 value = stall ? mask : 0;
70 snd_hdac_adsp_updatel(adev, AVS_ADSP_REG_ADSPCS, mask, value);
72 ret = snd_hdac_adsp_readl_poll(adev, AVS_ADSP_REG_ADSPCS,
73 reg, (reg & mask) == value,
74 AVS_ADSPCS_INTERVAL_US,
75 AVS_ADSPCS_TIMEOUT_US);
77 dev_err(adev->dev, "core_mask %d %sstall failed: %d\n",
78 core_mask, stall ? "" : "un", ret);
83 int avs_dsp_core_enable(struct avs_dev *adev, u32 core_mask)
87 ret = avs_dsp_op(adev, power, core_mask, true);
91 ret = avs_dsp_op(adev, reset, core_mask, false);
95 return avs_dsp_op(adev, stall, core_mask, false);
98 int avs_dsp_core_disable(struct avs_dev *adev, u32 core_mask)
100 /* No error checks to allow for complete DSP shutdown. */
101 avs_dsp_op(adev, stall, core_mask, true);
102 avs_dsp_op(adev, reset, core_mask, true);
104 return avs_dsp_op(adev, power, core_mask, false);
107 static int avs_dsp_enable(struct avs_dev *adev, u32 core_mask)
112 ret = avs_dsp_core_enable(adev, core_mask);
116 mask = core_mask & ~AVS_MAIN_CORE_MASK;
119 * without main core, fw is dead anyway
120 * so setting D0 for it is futile.
124 ret = avs_ipc_set_dx(adev, mask, true);
125 return AVS_IPC_RET(ret);
128 static int avs_dsp_disable(struct avs_dev *adev, u32 core_mask)
132 ret = avs_ipc_set_dx(adev, core_mask, false);
134 return AVS_IPC_RET(ret);
136 return avs_dsp_core_disable(adev, core_mask);
139 static int avs_dsp_get_core(struct avs_dev *adev, u32 core_id)
144 mask = BIT_MASK(core_id);
145 if (mask == AVS_MAIN_CORE_MASK)
146 /* nothing to do for main core */
148 if (core_id >= adev->hw_cfg.dsp_cores) {
153 adev->core_refs[core_id]++;
154 if (adev->core_refs[core_id] == 1) {
155 ret = avs_dsp_enable(adev, mask);
163 adev->core_refs[core_id]--;
165 dev_err(adev->dev, "get core %d failed: %d\n", core_id, ret);
169 static int avs_dsp_put_core(struct avs_dev *adev, u32 core_id)
174 mask = BIT_MASK(core_id);
175 if (mask == AVS_MAIN_CORE_MASK)
176 /* nothing to do for main core */
178 if (core_id >= adev->hw_cfg.dsp_cores) {
183 adev->core_refs[core_id]--;
184 if (!adev->core_refs[core_id]) {
185 ret = avs_dsp_disable(adev, mask);
192 dev_err(adev->dev, "put core %d failed: %d\n", core_id, ret);
196 int avs_dsp_init_module(struct avs_dev *adev, u16 module_id, u8 ppl_instance_id,
197 u8 core_id, u8 domain, void *param, u32 param_size,
200 struct avs_module_entry mentry;
201 bool was_loaded = false;
204 id = avs_module_id_alloc(adev, module_id);
208 ret = avs_get_module_id_entry(adev, module_id, &mentry);
212 ret = avs_dsp_get_core(adev, core_id);
216 /* Load code into memory if this is the first instance. */
217 if (!id && !avs_module_entry_is_loaded(&mentry)) {
218 ret = avs_dsp_op(adev, transfer_mods, true, &mentry, 1);
220 dev_err(adev->dev, "load modules failed: %d\n", ret);
226 ret = avs_ipc_init_instance(adev, module_id, id, ppl_instance_id,
227 core_id, domain, param, param_size);
229 ret = AVS_IPC_RET(ret);
238 avs_dsp_op(adev, transfer_mods, false, &mentry, 1);
239 avs_dsp_put_core(adev, core_id);
241 avs_module_id_free(adev, module_id, id);
245 void avs_dsp_delete_module(struct avs_dev *adev, u16 module_id, u16 instance_id,
246 u8 ppl_instance_id, u8 core_id)
248 struct avs_module_entry mentry;
251 /* Modules not owned by any pipeline need to be freed explicitly. */
252 if (ppl_instance_id == INVALID_PIPELINE_ID)
253 avs_ipc_delete_instance(adev, module_id, instance_id);
255 avs_module_id_free(adev, module_id, instance_id);
257 ret = avs_get_module_id_entry(adev, module_id, &mentry);
258 /* Unload occupied memory if this was the last instance. */
259 if (!ret && mentry.type.load_type == AVS_MODULE_LOAD_TYPE_LOADABLE) {
260 if (avs_is_module_ida_empty(adev, module_id)) {
261 ret = avs_dsp_op(adev, transfer_mods, false, &mentry, 1);
263 dev_err(adev->dev, "unload modules failed: %d\n", ret);
267 avs_dsp_put_core(adev, core_id);
270 int avs_dsp_create_pipeline(struct avs_dev *adev, u16 req_size, u8 priority,
271 bool lp, u16 attributes, u8 *instance_id)
273 struct avs_fw_cfg *fw_cfg = &adev->fw_cfg;
276 id = ida_alloc_max(&adev->ppl_ida, fw_cfg->max_ppl_count - 1, GFP_KERNEL);
280 ret = avs_ipc_create_pipeline(adev, req_size, priority, id, lp, attributes);
282 ida_free(&adev->ppl_ida, id);
283 return AVS_IPC_RET(ret);
290 int avs_dsp_delete_pipeline(struct avs_dev *adev, u8 instance_id)
294 ret = avs_ipc_delete_pipeline(adev, instance_id);
296 ret = AVS_IPC_RET(ret);
298 ida_free(&adev->ppl_ida, instance_id);
302 MODULE_LICENSE("GPL");