1 // SPDX-License-Identifier: GPL-2.0
3 // Freescale ESAI ALSA SoC Digital Audio Interface (DAI) driver
5 // Copyright (C) 2014 Freescale Semiconductor, Inc.
8 #include <linux/dmaengine.h>
9 #include <linux/module.h>
10 #include <linux/of_irq.h>
11 #include <linux/of_platform.h>
12 #include <linux/pm_runtime.h>
13 #include <sound/dmaengine_pcm.h>
14 #include <sound/pcm_params.h>
19 #define FSL_ESAI_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
20 SNDRV_PCM_FMTBIT_S16_LE | \
21 SNDRV_PCM_FMTBIT_S20_3LE | \
22 SNDRV_PCM_FMTBIT_S24_LE)
25 * struct fsl_esai_soc_data - soc specific data
26 * @imx: for imx platform
27 * @reset_at_xrun: flags for enable reset operaton
29 struct fsl_esai_soc_data {
35 * struct fsl_esai - ESAI private data
36 * @dma_params_rx: DMA parameters for receive channel
37 * @dma_params_tx: DMA parameters for transmit channel
38 * @pdev: platform device pointer
39 * @regmap: regmap handler
40 * @coreclk: clock source to access register
41 * @extalclk: esai clock source to derive HCK, SCK and FS
42 * @fsysclk: system clock source to derive HCK, SCK and FS
43 * @spbaclk: SPBA clock (optional, depending on SoC design)
44 * @work: work to handle the reset operation
45 * @soc: soc specific data
46 * @lock: spin lock between hw_reset() and trigger()
47 * @fifo_depth: depth of tx/rx FIFO
48 * @slot_width: width of each DAI slot
49 * @slots: number of slots
50 * @tx_mask: slot mask for TX
51 * @rx_mask: slot mask for RX
52 * @channels: channel num for tx or rx
53 * @hck_rate: clock rate of desired HCKx clock
54 * @sck_rate: clock rate of desired SCKx clock
55 * @hck_dir: the direction of HCKx pads
56 * @sck_div: if using PSR/PM dividers for SCKx clock
57 * @slave_mode: if fully using DAI slave mode
58 * @synchronous: if using tx/rx synchronous mode
62 struct snd_dmaengine_dai_dma_data dma_params_rx;
63 struct snd_dmaengine_dai_dma_data dma_params_tx;
64 struct platform_device *pdev;
65 struct regmap *regmap;
70 struct work_struct work;
71 const struct fsl_esai_soc_data *soc;
72 spinlock_t lock; /* Protect hw_reset and trigger */
88 static struct fsl_esai_soc_data fsl_esai_vf610 = {
90 .reset_at_xrun = true,
93 static struct fsl_esai_soc_data fsl_esai_imx35 = {
95 .reset_at_xrun = true,
98 static struct fsl_esai_soc_data fsl_esai_imx6ull = {
100 .reset_at_xrun = false,
103 static irqreturn_t esai_isr(int irq, void *devid)
105 struct fsl_esai *esai_priv = (struct fsl_esai *)devid;
106 struct platform_device *pdev = esai_priv->pdev;
110 regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr);
111 regmap_read(esai_priv->regmap, REG_ESAI_SAISR, &saisr);
113 if ((saisr & (ESAI_SAISR_TUE | ESAI_SAISR_ROE)) &&
114 esai_priv->soc->reset_at_xrun) {
115 dev_dbg(&pdev->dev, "reset module for xrun\n");
116 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
117 ESAI_xCR_xEIE_MASK, 0);
118 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR,
119 ESAI_xCR_xEIE_MASK, 0);
120 schedule_work(&esai_priv->work);
123 if (esr & ESAI_ESR_TINIT_MASK)
124 dev_dbg(&pdev->dev, "isr: Transmission Initialized\n");
126 if (esr & ESAI_ESR_RFF_MASK)
127 dev_warn(&pdev->dev, "isr: Receiving overrun\n");
129 if (esr & ESAI_ESR_TFE_MASK)
130 dev_warn(&pdev->dev, "isr: Transmission underrun\n");
132 if (esr & ESAI_ESR_TLS_MASK)
133 dev_dbg(&pdev->dev, "isr: Just transmitted the last slot\n");
135 if (esr & ESAI_ESR_TDE_MASK)
136 dev_dbg(&pdev->dev, "isr: Transmission data exception\n");
138 if (esr & ESAI_ESR_TED_MASK)
139 dev_dbg(&pdev->dev, "isr: Transmitting even slots\n");
141 if (esr & ESAI_ESR_TD_MASK)
142 dev_dbg(&pdev->dev, "isr: Transmitting data\n");
144 if (esr & ESAI_ESR_RLS_MASK)
145 dev_dbg(&pdev->dev, "isr: Just received the last slot\n");
147 if (esr & ESAI_ESR_RDE_MASK)
148 dev_dbg(&pdev->dev, "isr: Receiving data exception\n");
150 if (esr & ESAI_ESR_RED_MASK)
151 dev_dbg(&pdev->dev, "isr: Receiving even slots\n");
153 if (esr & ESAI_ESR_RD_MASK)
154 dev_dbg(&pdev->dev, "isr: Receiving data\n");
160 * fsl_esai_divisor_cal - This function is used to calculate the
161 * divisors of psr, pm, fp and it is supposed to be called in
162 * set_dai_sysclk() and set_bclk().
164 * @dai: pointer to DAI
165 * @tx: current setting is for playback or capture
166 * @ratio: desired overall ratio for the paticipating dividers
167 * @usefp: for HCK setting, there is no need to set fp divider
168 * @fp: bypass other dividers by setting fp directly if fp != 0
170 static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio,
173 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
174 u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j;
176 maxfp = usefp ? 16 : 1;
181 if (ratio > 2 * 8 * 256 * maxfp || ratio < 2) {
182 dev_err(dai->dev, "the ratio is out of range (2 ~ %d)\n",
183 2 * 8 * 256 * maxfp);
185 } else if (ratio % 2) {
186 dev_err(dai->dev, "the raio must be even if using upper divider\n");
192 psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8;
194 /* Do not loop-search if PM (1 ~ 256) alone can serve the ratio */
201 /* Set the max fluctuation -- 0.1% of the max devisor */
202 savesub = (psr ? 1 : 8) * 256 * maxfp / 1000;
204 /* Find the best value for PM */
205 for (i = 1; i <= 256; i++) {
206 for (j = 1; j <= maxfp; j++) {
207 /* PSR (1 or 8) * PM (1 ~ 256) * FP (1 ~ 16) */
208 prod = (psr ? 1 : 8) * i * j;
212 else if (prod / ratio == 1)
214 else if (ratio / prod == 1)
219 /* Calculate the fraction */
220 sub = sub * 1000 / ratio;
234 dev_err(dai->dev, "failed to calculate proper divisors\n");
239 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
240 ESAI_xCCR_xPSR_MASK | ESAI_xCCR_xPM_MASK,
241 psr | ESAI_xCCR_xPM(pm));
244 /* Bypass fp if not being required */
248 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
249 ESAI_xCCR_xFP_MASK, ESAI_xCCR_xFP(fp));
255 * fsl_esai_set_dai_sysclk - configure the clock frequency of MCLK (HCKT/HCKR)
256 * @dai: pointer to DAI
257 * @clk_id: The clock source of HCKT/HCKR
258 * (Input from outside; output from inside, FSYS or EXTAL)
259 * @freq: The required clock rate of HCKT/HCKR
260 * @dir: The clock direction of HCKT/HCKR
262 * Note: If the direction is input, we do not care about clk_id.
264 static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
265 unsigned int freq, int dir)
267 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
268 struct clk *clksrc = esai_priv->extalclk;
269 bool tx = (clk_id <= ESAI_HCKT_EXTAL || esai_priv->synchronous);
270 bool in = dir == SND_SOC_CLOCK_IN;
272 unsigned long clk_rate;
276 dev_err(dai->dev, "%sput freq of HCK%c should not be 0Hz\n",
277 in ? "in" : "out", tx ? 'T' : 'R');
281 /* Bypass divider settings if the requirement doesn't change */
282 if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx])
285 /* sck_div can be only bypassed if ETO/ERO=0 and SNC_SOC_CLOCK_OUT */
286 esai_priv->sck_div[tx] = true;
288 /* Set the direction of HCKT/HCKR pins */
289 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
290 ESAI_xCCR_xHCKD, in ? 0 : ESAI_xCCR_xHCKD);
298 clksrc = esai_priv->fsysclk;
300 case ESAI_HCKT_EXTAL:
303 case ESAI_HCKR_EXTAL:
304 ecr |= esai_priv->synchronous ? ESAI_ECR_ETI : ESAI_ECR_ERI;
310 if (IS_ERR(clksrc)) {
311 dev_err(dai->dev, "no assigned %s clock\n",
312 clk_id % 2 ? "extal" : "fsys");
313 return PTR_ERR(clksrc);
315 clk_rate = clk_get_rate(clksrc);
317 ratio = clk_rate / freq;
318 if (ratio * freq > clk_rate)
319 ret = ratio * freq - clk_rate;
320 else if (ratio * freq < clk_rate)
321 ret = clk_rate - ratio * freq;
325 /* Block if clock source can not be divided into the required rate */
326 if (ret != 0 && clk_rate / ret < 1000) {
327 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
332 /* Only EXTAL source can be output directly without using PSR and PM */
333 if (ratio == 1 && clksrc == esai_priv->extalclk) {
334 /* Bypass all the dividers if not being needed */
335 ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO;
337 } else if (ratio < 2) {
338 /* The ratio should be no less than 2 if using other sources */
339 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
344 ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0);
348 esai_priv->sck_div[tx] = false;
351 esai_priv->hck_dir[tx] = dir;
352 esai_priv->hck_rate[tx] = freq;
354 regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
355 tx ? ESAI_ECR_ETI | ESAI_ECR_ETO :
356 ESAI_ECR_ERI | ESAI_ECR_ERO, ecr);
362 * fsl_esai_set_bclk - configure the related dividers according to the bclk rate
363 * @dai: pointer to DAI
364 * @tx: direction boolean
367 static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
369 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
370 u32 hck_rate = esai_priv->hck_rate[tx];
371 u32 sub, ratio = hck_rate / freq;
374 /* Don't apply for fully slave mode or unchanged bclk */
375 if (esai_priv->slave_mode || esai_priv->sck_rate[tx] == freq)
378 if (ratio * freq > hck_rate)
379 sub = ratio * freq - hck_rate;
380 else if (ratio * freq < hck_rate)
381 sub = hck_rate - ratio * freq;
385 /* Block if clock source can not be divided into the required rate */
386 if (sub != 0 && hck_rate / sub < 1000) {
387 dev_err(dai->dev, "failed to derive required SCK%c rate\n",
392 /* The ratio should be contented by FP alone if bypassing PM and PSR */
393 if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) {
394 dev_err(dai->dev, "the ratio is out of range (1 ~ 16)\n");
398 ret = fsl_esai_divisor_cal(dai, tx, ratio, true,
399 esai_priv->sck_div[tx] ? 0 : ratio);
403 /* Save current bclk rate */
404 esai_priv->sck_rate[tx] = freq;
409 static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
410 u32 rx_mask, int slots, int slot_width)
412 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
414 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
415 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
417 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
418 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
420 esai_priv->slot_width = slot_width;
421 esai_priv->slots = slots;
422 esai_priv->tx_mask = tx_mask;
423 esai_priv->rx_mask = rx_mask;
428 static int fsl_esai_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
430 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
431 u32 xcr = 0, xccr = 0, mask;
434 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
435 case SND_SOC_DAIFMT_I2S:
436 /* Data on rising edge of bclk, frame low, 1clk before data */
437 xcr |= ESAI_xCR_xFSR;
438 xccr |= ESAI_xCCR_xFSP | ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
440 case SND_SOC_DAIFMT_LEFT_J:
441 /* Data on rising edge of bclk, frame high */
442 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
444 case SND_SOC_DAIFMT_RIGHT_J:
445 /* Data on rising edge of bclk, frame high, right aligned */
446 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
449 case SND_SOC_DAIFMT_DSP_A:
450 /* Data on rising edge of bclk, frame high, 1clk before data */
451 xcr |= ESAI_xCR_xFSL | ESAI_xCR_xFSR;
452 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
454 case SND_SOC_DAIFMT_DSP_B:
455 /* Data on rising edge of bclk, frame high */
456 xcr |= ESAI_xCR_xFSL;
457 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
463 /* DAI clock inversion */
464 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
465 case SND_SOC_DAIFMT_NB_NF:
466 /* Nothing to do for both normal cases */
468 case SND_SOC_DAIFMT_IB_NF:
469 /* Invert bit clock */
470 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
472 case SND_SOC_DAIFMT_NB_IF:
473 /* Invert frame clock */
474 xccr ^= ESAI_xCCR_xFSP;
476 case SND_SOC_DAIFMT_IB_IF:
477 /* Invert both clocks */
478 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP;
484 esai_priv->slave_mode = false;
486 /* DAI clock master masks */
487 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
488 case SND_SOC_DAIFMT_CBM_CFM:
489 esai_priv->slave_mode = true;
491 case SND_SOC_DAIFMT_CBS_CFM:
492 xccr |= ESAI_xCCR_xCKD;
494 case SND_SOC_DAIFMT_CBM_CFS:
495 xccr |= ESAI_xCCR_xFSD;
497 case SND_SOC_DAIFMT_CBS_CFS:
498 xccr |= ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
504 mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR | ESAI_xCR_xWA;
505 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr);
506 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr);
508 mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP |
509 ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
510 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr);
511 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr);
516 static int fsl_esai_startup(struct snd_pcm_substream *substream,
517 struct snd_soc_dai *dai)
519 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
521 if (!snd_soc_dai_active(dai)) {
522 /* Set synchronous mode */
523 regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR,
524 ESAI_SAICR_SYNC, esai_priv->synchronous ?
525 ESAI_SAICR_SYNC : 0);
527 /* Set a default slot number -- 2 */
528 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
529 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2));
530 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
531 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2));
538 static int fsl_esai_hw_params(struct snd_pcm_substream *substream,
539 struct snd_pcm_hw_params *params,
540 struct snd_soc_dai *dai)
542 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
543 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
544 u32 width = params_width(params);
545 u32 channels = params_channels(params);
546 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
547 u32 slot_width = width;
551 /* Override slot_width if being specifically set */
552 if (esai_priv->slot_width)
553 slot_width = esai_priv->slot_width;
555 bclk = params_rate(params) * slot_width * esai_priv->slots;
557 ret = fsl_esai_set_bclk(dai, esai_priv->synchronous || tx, bclk);
561 mask = ESAI_xCR_xSWS_MASK;
562 val = ESAI_xCR_xSWS(slot_width, width);
564 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val);
565 /* Recording in synchronous mode needs to set TCR also */
566 if (!tx && esai_priv->synchronous)
567 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, val);
569 /* Use Normal mode to support monaural audio */
570 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
571 ESAI_xCR_xMOD_MASK, params_channels(params) > 1 ?
572 ESAI_xCR_xMOD_NETWORK : 0);
574 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
575 ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR);
577 mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK |
578 (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK);
579 val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) |
580 (tx ? ESAI_xFCR_TE(pins) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(pins));
582 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val);
585 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
586 ESAI_xCR_PADC, ESAI_xCR_PADC);
588 /* Remove ESAI personal reset by configuring ESAI_PCRC and ESAI_PRRC */
589 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
590 ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO));
591 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
592 ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO));
596 static int fsl_esai_hw_init(struct fsl_esai *esai_priv)
598 struct platform_device *pdev = esai_priv->pdev;
601 /* Reset ESAI unit */
602 ret = regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
603 ESAI_ECR_ESAIEN_MASK | ESAI_ECR_ERST_MASK,
604 ESAI_ECR_ESAIEN | ESAI_ECR_ERST);
606 dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret);
611 * We need to enable ESAI so as to access some of its registers.
612 * Otherwise, we would fail to dump regmap from user space.
614 ret = regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
615 ESAI_ECR_ESAIEN_MASK | ESAI_ECR_ERST_MASK,
618 dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret);
622 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
623 ESAI_PRRC_PDC_MASK, 0);
624 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
625 ESAI_PCRC_PC_MASK, 0);
630 static int fsl_esai_register_restore(struct fsl_esai *esai_priv)
634 /* FIFO reset for safety */
635 regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR,
636 ESAI_xFCR_xFR, ESAI_xFCR_xFR);
637 regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR,
638 ESAI_xFCR_xFR, ESAI_xFCR_xFR);
640 regcache_mark_dirty(esai_priv->regmap);
641 ret = regcache_sync(esai_priv->regmap);
645 /* FIFO reset done */
646 regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0);
647 regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0);
652 static void fsl_esai_trigger_start(struct fsl_esai *esai_priv, bool tx)
654 u8 i, channels = esai_priv->channels[tx];
655 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
658 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
659 ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN);
661 /* Write initial words reqiured by ESAI as normal procedure */
662 for (i = 0; tx && i < channels; i++)
663 regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);
666 * When set the TE/RE in the end of enablement flow, there
667 * will be channel swap issue for multi data line case.
668 * In order to workaround this issue, we switch the bit
669 * enablement sequence to below sequence
670 * 1) clear the xSMB & xSMA: which is done in probe and
674 * 4) set xSMA: xSMA is the last one in this flow, which
675 * will trigger esai to start.
677 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
678 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,
679 tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins));
680 mask = tx ? esai_priv->tx_mask : esai_priv->rx_mask;
682 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
683 ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(mask));
684 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
685 ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(mask));
687 /* Enable Exception interrupt */
688 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
689 ESAI_xCR_xEIE_MASK, ESAI_xCR_xEIE);
692 static void fsl_esai_trigger_stop(struct fsl_esai *esai_priv, bool tx)
694 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
695 ESAI_xCR_xEIE_MASK, 0);
697 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
698 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);
699 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
700 ESAI_xSMA_xS_MASK, 0);
701 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
702 ESAI_xSMB_xS_MASK, 0);
704 /* Disable and reset FIFO */
705 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
706 ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR);
707 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
711 static void fsl_esai_hw_reset(struct work_struct *work)
713 struct fsl_esai *esai_priv = container_of(work, struct fsl_esai, work);
714 bool tx = true, rx = false, enabled[2];
715 unsigned long lock_flags;
718 spin_lock_irqsave(&esai_priv->lock, lock_flags);
719 /* Save the registers */
720 regmap_read(esai_priv->regmap, REG_ESAI_TFCR, &tfcr);
721 regmap_read(esai_priv->regmap, REG_ESAI_RFCR, &rfcr);
722 enabled[tx] = tfcr & ESAI_xFCR_xFEN;
723 enabled[rx] = rfcr & ESAI_xFCR_xFEN;
725 /* Stop the tx & rx */
726 fsl_esai_trigger_stop(esai_priv, tx);
727 fsl_esai_trigger_stop(esai_priv, rx);
729 /* Reset the esai, and ignore return value */
730 fsl_esai_hw_init(esai_priv);
732 /* Enforce ESAI personal resets for both TX and RX */
733 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
734 ESAI_xCR_xPR_MASK, ESAI_xCR_xPR);
735 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR,
736 ESAI_xCR_xPR_MASK, ESAI_xCR_xPR);
738 /* Restore registers by regcache_sync, and ignore return value */
739 fsl_esai_register_restore(esai_priv);
741 /* Remove ESAI personal resets by configuring PCRC and PRRC also */
742 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
743 ESAI_xCR_xPR_MASK, 0);
744 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR,
745 ESAI_xCR_xPR_MASK, 0);
746 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
747 ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO));
748 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
749 ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO));
751 /* Restart tx / rx, if they already enabled */
753 fsl_esai_trigger_start(esai_priv, tx);
755 fsl_esai_trigger_start(esai_priv, rx);
757 spin_unlock_irqrestore(&esai_priv->lock, lock_flags);
760 static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd,
761 struct snd_soc_dai *dai)
763 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
764 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
765 unsigned long lock_flags;
767 esai_priv->channels[tx] = substream->runtime->channels;
770 case SNDRV_PCM_TRIGGER_START:
771 case SNDRV_PCM_TRIGGER_RESUME:
772 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
773 spin_lock_irqsave(&esai_priv->lock, lock_flags);
774 fsl_esai_trigger_start(esai_priv, tx);
775 spin_unlock_irqrestore(&esai_priv->lock, lock_flags);
777 case SNDRV_PCM_TRIGGER_SUSPEND:
778 case SNDRV_PCM_TRIGGER_STOP:
779 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
780 spin_lock_irqsave(&esai_priv->lock, lock_flags);
781 fsl_esai_trigger_stop(esai_priv, tx);
782 spin_unlock_irqrestore(&esai_priv->lock, lock_flags);
791 static const struct snd_soc_dai_ops fsl_esai_dai_ops = {
792 .startup = fsl_esai_startup,
793 .trigger = fsl_esai_trigger,
794 .hw_params = fsl_esai_hw_params,
795 .set_sysclk = fsl_esai_set_dai_sysclk,
796 .set_fmt = fsl_esai_set_dai_fmt,
797 .set_tdm_slot = fsl_esai_set_dai_tdm_slot,
800 static int fsl_esai_dai_probe(struct snd_soc_dai *dai)
802 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
804 snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx,
805 &esai_priv->dma_params_rx);
810 static struct snd_soc_dai_driver fsl_esai_dai = {
811 .probe = fsl_esai_dai_probe,
813 .stream_name = "CPU-Playback",
816 .rates = SNDRV_PCM_RATE_8000_192000,
817 .formats = FSL_ESAI_FORMATS,
820 .stream_name = "CPU-Capture",
823 .rates = SNDRV_PCM_RATE_8000_192000,
824 .formats = FSL_ESAI_FORMATS,
826 .ops = &fsl_esai_dai_ops,
829 static const struct snd_soc_component_driver fsl_esai_component = {
833 static const struct reg_default fsl_esai_reg_defaults[] = {
834 {REG_ESAI_ETDR, 0x00000000},
835 {REG_ESAI_ECR, 0x00000000},
836 {REG_ESAI_TFCR, 0x00000000},
837 {REG_ESAI_RFCR, 0x00000000},
838 {REG_ESAI_TX0, 0x00000000},
839 {REG_ESAI_TX1, 0x00000000},
840 {REG_ESAI_TX2, 0x00000000},
841 {REG_ESAI_TX3, 0x00000000},
842 {REG_ESAI_TX4, 0x00000000},
843 {REG_ESAI_TX5, 0x00000000},
844 {REG_ESAI_TSR, 0x00000000},
845 {REG_ESAI_SAICR, 0x00000000},
846 {REG_ESAI_TCR, 0x00000000},
847 {REG_ESAI_TCCR, 0x00000000},
848 {REG_ESAI_RCR, 0x00000000},
849 {REG_ESAI_RCCR, 0x00000000},
850 {REG_ESAI_TSMA, 0x0000ffff},
851 {REG_ESAI_TSMB, 0x0000ffff},
852 {REG_ESAI_RSMA, 0x0000ffff},
853 {REG_ESAI_RSMB, 0x0000ffff},
854 {REG_ESAI_PRRC, 0x00000000},
855 {REG_ESAI_PCRC, 0x00000000},
858 static bool fsl_esai_readable_reg(struct device *dev, unsigned int reg)
890 static bool fsl_esai_volatile_reg(struct device *dev, unsigned int reg)
908 static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg)
939 static const struct regmap_config fsl_esai_regmap_config = {
944 .max_register = REG_ESAI_PCRC,
945 .reg_defaults = fsl_esai_reg_defaults,
946 .num_reg_defaults = ARRAY_SIZE(fsl_esai_reg_defaults),
947 .readable_reg = fsl_esai_readable_reg,
948 .volatile_reg = fsl_esai_volatile_reg,
949 .writeable_reg = fsl_esai_writeable_reg,
950 .cache_type = REGCACHE_FLAT,
953 static int fsl_esai_probe(struct platform_device *pdev)
955 struct device_node *np = pdev->dev.of_node;
956 struct fsl_esai *esai_priv;
957 struct resource *res;
962 esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL);
966 esai_priv->pdev = pdev;
967 snprintf(esai_priv->name, sizeof(esai_priv->name), "%pOFn", np);
969 esai_priv->soc = of_device_get_match_data(&pdev->dev);
970 if (!esai_priv->soc) {
971 dev_err(&pdev->dev, "failed to get soc data\n");
975 /* Get the addresses and IRQ */
976 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
977 regs = devm_ioremap_resource(&pdev->dev, res);
979 return PTR_ERR(regs);
981 esai_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
982 "core", regs, &fsl_esai_regmap_config);
983 if (IS_ERR(esai_priv->regmap)) {
984 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
985 PTR_ERR(esai_priv->regmap));
986 return PTR_ERR(esai_priv->regmap);
989 esai_priv->coreclk = devm_clk_get(&pdev->dev, "core");
990 if (IS_ERR(esai_priv->coreclk)) {
991 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
992 PTR_ERR(esai_priv->coreclk));
993 return PTR_ERR(esai_priv->coreclk);
996 esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal");
997 if (IS_ERR(esai_priv->extalclk))
998 dev_warn(&pdev->dev, "failed to get extal clock: %ld\n",
999 PTR_ERR(esai_priv->extalclk));
1001 esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys");
1002 if (IS_ERR(esai_priv->fsysclk))
1003 dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n",
1004 PTR_ERR(esai_priv->fsysclk));
1006 esai_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
1007 if (IS_ERR(esai_priv->spbaclk))
1008 dev_warn(&pdev->dev, "failed to get spba clock: %ld\n",
1009 PTR_ERR(esai_priv->spbaclk));
1011 irq = platform_get_irq(pdev, 0);
1015 ret = devm_request_irq(&pdev->dev, irq, esai_isr, IRQF_SHARED,
1016 esai_priv->name, esai_priv);
1018 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
1022 /* Set a default slot number */
1023 esai_priv->slots = 2;
1025 /* Set a default master/slave state */
1026 esai_priv->slave_mode = true;
1028 /* Determine the FIFO depth */
1029 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1031 esai_priv->fifo_depth = be32_to_cpup(iprop);
1033 esai_priv->fifo_depth = 64;
1035 esai_priv->dma_params_tx.maxburst = 16;
1036 esai_priv->dma_params_rx.maxburst = 16;
1037 esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR;
1038 esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR;
1040 esai_priv->synchronous =
1041 of_property_read_bool(np, "fsl,esai-synchronous");
1043 /* Implement full symmetry for synchronous mode */
1044 if (esai_priv->synchronous) {
1045 fsl_esai_dai.symmetric_rates = 1;
1046 fsl_esai_dai.symmetric_channels = 1;
1047 fsl_esai_dai.symmetric_samplebits = 1;
1050 dev_set_drvdata(&pdev->dev, esai_priv);
1052 spin_lock_init(&esai_priv->lock);
1053 ret = fsl_esai_hw_init(esai_priv);
1057 esai_priv->tx_mask = 0xFFFFFFFF;
1058 esai_priv->rx_mask = 0xFFFFFFFF;
1060 /* Clear the TSMA, TSMB, RSMA, RSMB */
1061 regmap_write(esai_priv->regmap, REG_ESAI_TSMA, 0);
1062 regmap_write(esai_priv->regmap, REG_ESAI_TSMB, 0);
1063 regmap_write(esai_priv->regmap, REG_ESAI_RSMA, 0);
1064 regmap_write(esai_priv->regmap, REG_ESAI_RSMB, 0);
1066 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_esai_component,
1069 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1073 INIT_WORK(&esai_priv->work, fsl_esai_hw_reset);
1075 pm_runtime_enable(&pdev->dev);
1077 regcache_cache_only(esai_priv->regmap, true);
1079 ret = imx_pcm_dma_init(pdev, IMX_ESAI_DMABUF_SIZE);
1081 dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret);
1086 static int fsl_esai_remove(struct platform_device *pdev)
1088 struct fsl_esai *esai_priv = platform_get_drvdata(pdev);
1090 pm_runtime_disable(&pdev->dev);
1091 cancel_work_sync(&esai_priv->work);
1096 static const struct of_device_id fsl_esai_dt_ids[] = {
1097 { .compatible = "fsl,imx35-esai", .data = &fsl_esai_imx35 },
1098 { .compatible = "fsl,vf610-esai", .data = &fsl_esai_vf610 },
1099 { .compatible = "fsl,imx6ull-esai", .data = &fsl_esai_imx6ull },
1102 MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids);
1105 static int fsl_esai_runtime_resume(struct device *dev)
1107 struct fsl_esai *esai = dev_get_drvdata(dev);
1111 * Some platforms might use the same bit to gate all three or two of
1112 * clocks, so keep all clocks open/close at the same time for safety
1114 ret = clk_prepare_enable(esai->coreclk);
1117 if (!IS_ERR(esai->spbaclk)) {
1118 ret = clk_prepare_enable(esai->spbaclk);
1122 if (!IS_ERR(esai->extalclk)) {
1123 ret = clk_prepare_enable(esai->extalclk);
1127 if (!IS_ERR(esai->fsysclk)) {
1128 ret = clk_prepare_enable(esai->fsysclk);
1133 regcache_cache_only(esai->regmap, false);
1135 ret = fsl_esai_register_restore(esai);
1137 goto err_regcache_sync;
1142 if (!IS_ERR(esai->fsysclk))
1143 clk_disable_unprepare(esai->fsysclk);
1145 if (!IS_ERR(esai->extalclk))
1146 clk_disable_unprepare(esai->extalclk);
1148 if (!IS_ERR(esai->spbaclk))
1149 clk_disable_unprepare(esai->spbaclk);
1151 clk_disable_unprepare(esai->coreclk);
1156 static int fsl_esai_runtime_suspend(struct device *dev)
1158 struct fsl_esai *esai = dev_get_drvdata(dev);
1160 regcache_cache_only(esai->regmap, true);
1162 if (!IS_ERR(esai->fsysclk))
1163 clk_disable_unprepare(esai->fsysclk);
1164 if (!IS_ERR(esai->extalclk))
1165 clk_disable_unprepare(esai->extalclk);
1166 if (!IS_ERR(esai->spbaclk))
1167 clk_disable_unprepare(esai->spbaclk);
1168 clk_disable_unprepare(esai->coreclk);
1172 #endif /* CONFIG_PM */
1174 static const struct dev_pm_ops fsl_esai_pm_ops = {
1175 SET_RUNTIME_PM_OPS(fsl_esai_runtime_suspend,
1176 fsl_esai_runtime_resume,
1178 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1179 pm_runtime_force_resume)
1182 static struct platform_driver fsl_esai_driver = {
1183 .probe = fsl_esai_probe,
1184 .remove = fsl_esai_remove,
1186 .name = "fsl-esai-dai",
1187 .pm = &fsl_esai_pm_ops,
1188 .of_match_table = fsl_esai_dt_ids,
1192 module_platform_driver(fsl_esai_driver);
1194 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1195 MODULE_DESCRIPTION("Freescale ESAI CPU DAI driver");
1196 MODULE_LICENSE("GPL v2");
1197 MODULE_ALIAS("platform:fsl-esai-dai");