2 * Freescale DMA ALSA SoC PCM driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
12 * This driver implements ASoC support for the Elo DMA controller, which is
13 * the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms,
14 * the PCM driver is what handles the DMA buffer.
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/platform_device.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/interrupt.h>
22 #include <linux/delay.h>
23 #include <linux/gfp.h>
24 #include <linux/of_platform.h>
25 #include <linux/list.h>
26 #include <linux/slab.h>
28 #include <sound/core.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/soc.h>
36 #include "fsl_ssi.h" /* For the offset of stx0 and srx0 */
39 * The formats that the DMA controller supports, which is anything
40 * that is 8, 16, or 32 bits.
42 #define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
43 SNDRV_PCM_FMTBIT_U8 | \
44 SNDRV_PCM_FMTBIT_S16_LE | \
45 SNDRV_PCM_FMTBIT_S16_BE | \
46 SNDRV_PCM_FMTBIT_U16_LE | \
47 SNDRV_PCM_FMTBIT_U16_BE | \
48 SNDRV_PCM_FMTBIT_S24_LE | \
49 SNDRV_PCM_FMTBIT_S24_BE | \
50 SNDRV_PCM_FMTBIT_U24_LE | \
51 SNDRV_PCM_FMTBIT_U24_BE | \
52 SNDRV_PCM_FMTBIT_S32_LE | \
53 SNDRV_PCM_FMTBIT_S32_BE | \
54 SNDRV_PCM_FMTBIT_U32_LE | \
55 SNDRV_PCM_FMTBIT_U32_BE)
57 #define FSLDMA_PCM_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \
58 SNDRV_PCM_RATE_CONTINUOUS)
61 struct snd_soc_platform_driver dai;
62 dma_addr_t ssi_stx_phys;
63 dma_addr_t ssi_srx_phys;
64 unsigned int ssi_fifo_depth;
65 struct ccsr_dma_channel __iomem *channel;
72 * The number of DMA links to use. Two is the bare minimum, but if you
73 * have really small links you might need more.
75 #define NUM_DMA_LINKS 2
77 /** fsl_dma_private: p-substream DMA data
79 * Each substream has a 1-to-1 association with a DMA channel.
81 * The link[] array is first because it needs to be aligned on a 32-byte
82 * boundary, so putting it first will ensure alignment without padding the
85 * @link[]: array of link descriptors
86 * @dma_channel: pointer to the DMA channel's registers
87 * @irq: IRQ for this DMA channel
88 * @substream: pointer to the substream object, needed by the ISR
89 * @ssi_sxx_phys: bus address of the STX or SRX register to use
90 * @ld_buf_phys: physical address of the LD buffer
91 * @current_link: index into link[] of the link currently being processed
92 * @dma_buf_phys: physical address of the DMA buffer
93 * @dma_buf_next: physical address of the next period to process
94 * @dma_buf_end: physical address of the byte after the end of the DMA
95 * @buffer period_size: the size of a single period
96 * @num_periods: the number of periods in the DMA buffer
98 struct fsl_dma_private {
99 struct fsl_dma_link_descriptor link[NUM_DMA_LINKS];
100 struct ccsr_dma_channel __iomem *dma_channel;
102 struct snd_pcm_substream *substream;
103 dma_addr_t ssi_sxx_phys;
104 unsigned int ssi_fifo_depth;
105 dma_addr_t ld_buf_phys;
106 unsigned int current_link;
107 dma_addr_t dma_buf_phys;
108 dma_addr_t dma_buf_next;
109 dma_addr_t dma_buf_end;
111 unsigned int num_periods;
115 * fsl_dma_hardare: define characteristics of the PCM hardware.
117 * The PCM hardware is the Freescale DMA controller. This structure defines
118 * the capabilities of that hardware.
120 * Since the sampling rate and data format are not controlled by the DMA
121 * controller, we specify no limits for those values. The only exception is
122 * period_bytes_min, which is set to a reasonably low value to prevent the
123 * DMA controller from generating too many interrupts per second.
125 * Since each link descriptor has a 32-bit byte count field, we set
126 * period_bytes_max to the largest 32-bit number. We also have no maximum
129 * Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a
130 * limitation in the SSI driver requires the sample rates for playback and
131 * capture to be the same.
133 static const struct snd_pcm_hardware fsl_dma_hardware = {
135 .info = SNDRV_PCM_INFO_INTERLEAVED |
136 SNDRV_PCM_INFO_MMAP |
137 SNDRV_PCM_INFO_MMAP_VALID |
138 SNDRV_PCM_INFO_JOINT_DUPLEX |
139 SNDRV_PCM_INFO_PAUSE,
140 .formats = FSLDMA_PCM_FORMATS,
141 .rates = FSLDMA_PCM_RATES,
144 .period_bytes_min = 512, /* A reasonable limit */
145 .period_bytes_max = (u32) -1,
146 .periods_min = NUM_DMA_LINKS,
147 .periods_max = (unsigned int) -1,
148 .buffer_bytes_max = 128 * 1024, /* A reasonable limit */
152 * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted
154 * This function should be called by the ISR whenever the DMA controller
155 * halts data transfer.
157 static void fsl_dma_abort_stream(struct snd_pcm_substream *substream)
161 snd_pcm_stream_lock_irqsave(substream, flags);
163 if (snd_pcm_running(substream))
164 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
166 snd_pcm_stream_unlock_irqrestore(substream, flags);
170 * fsl_dma_update_pointers - update LD pointers to point to the next period
172 * As each period is completed, this function changes the the link
173 * descriptor pointers for that period to point to the next period.
175 static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private)
177 struct fsl_dma_link_descriptor *link =
178 &dma_private->link[dma_private->current_link];
180 /* Update our link descriptors to point to the next period. On a 36-bit
181 * system, we also need to update the ESAD bits. We also set (keep) the
182 * snoop bits. See the comments in fsl_dma_hw_params() about snooping.
184 if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
185 link->source_addr = cpu_to_be32(dma_private->dma_buf_next);
186 #ifdef CONFIG_PHYS_64BIT
187 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
188 upper_32_bits(dma_private->dma_buf_next));
191 link->dest_addr = cpu_to_be32(dma_private->dma_buf_next);
192 #ifdef CONFIG_PHYS_64BIT
193 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
194 upper_32_bits(dma_private->dma_buf_next));
198 /* Update our variables for next time */
199 dma_private->dma_buf_next += dma_private->period_size;
201 if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
202 dma_private->dma_buf_next = dma_private->dma_buf_phys;
204 if (++dma_private->current_link >= NUM_DMA_LINKS)
205 dma_private->current_link = 0;
209 * fsl_dma_isr: interrupt handler for the DMA controller
211 * @irq: IRQ of the DMA channel
212 * @dev_id: pointer to the dma_private structure for this DMA channel
214 static irqreturn_t fsl_dma_isr(int irq, void *dev_id)
216 struct fsl_dma_private *dma_private = dev_id;
217 struct snd_pcm_substream *substream = dma_private->substream;
218 struct snd_soc_pcm_runtime *rtd = substream->private_data;
219 struct device *dev = rtd->platform->dev;
220 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
221 irqreturn_t ret = IRQ_NONE;
224 /* We got an interrupt, so read the status register to see what we
225 were interrupted for.
227 sr = in_be32(&dma_channel->sr);
229 if (sr & CCSR_DMA_SR_TE) {
230 dev_err(dev, "dma transmit error\n");
231 fsl_dma_abort_stream(substream);
232 sr2 |= CCSR_DMA_SR_TE;
236 if (sr & CCSR_DMA_SR_CH)
239 if (sr & CCSR_DMA_SR_PE) {
240 dev_err(dev, "dma programming error\n");
241 fsl_dma_abort_stream(substream);
242 sr2 |= CCSR_DMA_SR_PE;
246 if (sr & CCSR_DMA_SR_EOLNI) {
247 sr2 |= CCSR_DMA_SR_EOLNI;
251 if (sr & CCSR_DMA_SR_CB)
254 if (sr & CCSR_DMA_SR_EOSI) {
255 /* Tell ALSA we completed a period. */
256 snd_pcm_period_elapsed(substream);
259 * Update our link descriptors to point to the next period. We
260 * only need to do this if the number of periods is not equal to
261 * the number of links.
263 if (dma_private->num_periods != NUM_DMA_LINKS)
264 fsl_dma_update_pointers(dma_private);
266 sr2 |= CCSR_DMA_SR_EOSI;
270 if (sr & CCSR_DMA_SR_EOLSI) {
271 sr2 |= CCSR_DMA_SR_EOLSI;
275 /* Clear the bits that we set */
277 out_be32(&dma_channel->sr, sr2);
283 * fsl_dma_new: initialize this PCM driver.
285 * This function is called when the codec driver calls snd_soc_new_pcms(),
286 * once for each .dai_link in the machine driver's snd_soc_card
289 * snd_dma_alloc_pages() is just a front-end to dma_alloc_coherent(), which
290 * (currently) always allocates the DMA buffer in lowmem, even if GFP_HIGHMEM
291 * is specified. Therefore, any DMA buffers we allocate will always be in low
292 * memory, but we support for 36-bit physical addresses anyway.
294 * Regardless of where the memory is actually allocated, since the device can
295 * technically DMA to any 36-bit address, we do need to set the DMA mask to 36.
297 static int fsl_dma_new(struct snd_soc_pcm_runtime *rtd)
299 struct snd_card *card = rtd->card->snd_card;
300 struct snd_pcm *pcm = rtd->pcm;
303 ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(36));
307 /* Some codecs have separate DAIs for playback and capture, so we
308 * should allocate a DMA buffer only for the streams that are valid.
311 if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
312 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev,
313 fsl_dma_hardware.buffer_bytes_max,
314 &pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer);
316 dev_err(card->dev, "can't alloc playback dma buffer\n");
321 if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
322 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev,
323 fsl_dma_hardware.buffer_bytes_max,
324 &pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream->dma_buffer);
326 dev_err(card->dev, "can't alloc capture dma buffer\n");
327 snd_dma_free_pages(&pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer);
336 * fsl_dma_open: open a new substream.
338 * Each substream has its own DMA buffer.
340 * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link
341 * descriptors that ping-pong from one period to the next. For example, if
342 * there are six periods and two link descriptors, this is how they look
343 * before playback starts:
345 * The last link descriptor
346 * ____________ points back to the first
355 * _________________________________________
356 * | | | | | | | The DMA buffer is
357 * | | | | | | | divided into 6 parts
358 * |______|______|______|______|______|______|
360 * and here's how they look after the first period is finished playing:
372 * _________________________________________
375 * |______|______|______|______|______|______|
377 * The first link descriptor now points to the third period. The DMA
378 * controller is currently playing the second period. When it finishes, it
379 * will jump back to the first descriptor and play the third period.
381 * There are four reasons we do this:
383 * 1. The only way to get the DMA controller to automatically restart the
384 * transfer when it gets to the end of the buffer is to use chaining
385 * mode. Basic direct mode doesn't offer that feature.
386 * 2. We need to receive an interrupt at the end of every period. The DMA
387 * controller can generate an interrupt at the end of every link transfer
388 * (aka segment). Making each period into a DMA segment will give us the
389 * interrupts we need.
390 * 3. By creating only two link descriptors, regardless of the number of
391 * periods, we do not need to reallocate the link descriptors if the
392 * number of periods changes.
393 * 4. All of the audio data is still stored in a single, contiguous DMA
394 * buffer, which is what ALSA expects. We're just dividing it into
395 * contiguous parts, and creating a link descriptor for each one.
397 static int fsl_dma_open(struct snd_pcm_substream *substream)
399 struct snd_pcm_runtime *runtime = substream->runtime;
400 struct snd_soc_pcm_runtime *rtd = substream->private_data;
401 struct device *dev = rtd->platform->dev;
402 struct dma_object *dma =
403 container_of(rtd->platform->driver, struct dma_object, dai);
404 struct fsl_dma_private *dma_private;
405 struct ccsr_dma_channel __iomem *dma_channel;
406 dma_addr_t ld_buf_phys;
407 u64 temp_link; /* Pointer to next link descriptor */
409 unsigned int channel;
414 * Reject any DMA buffer whose size is not a multiple of the period
415 * size. We need to make sure that the DMA buffer can be evenly divided
418 ret = snd_pcm_hw_constraint_integer(runtime,
419 SNDRV_PCM_HW_PARAM_PERIODS);
421 dev_err(dev, "invalid buffer size\n");
425 channel = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
428 dev_err(dev, "dma channel already assigned\n");
432 dma_private = dma_alloc_coherent(dev, sizeof(struct fsl_dma_private),
433 &ld_buf_phys, GFP_KERNEL);
435 dev_err(dev, "can't allocate dma private data\n");
438 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
439 dma_private->ssi_sxx_phys = dma->ssi_stx_phys;
441 dma_private->ssi_sxx_phys = dma->ssi_srx_phys;
443 dma_private->ssi_fifo_depth = dma->ssi_fifo_depth;
444 dma_private->dma_channel = dma->channel;
445 dma_private->irq = dma->irq;
446 dma_private->substream = substream;
447 dma_private->ld_buf_phys = ld_buf_phys;
448 dma_private->dma_buf_phys = substream->dma_buffer.addr;
450 ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "fsldma-audio",
453 dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n",
454 dma_private->irq, ret);
455 dma_free_coherent(dev, sizeof(struct fsl_dma_private),
456 dma_private, dma_private->ld_buf_phys);
462 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
463 snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware);
464 runtime->private_data = dma_private;
466 /* Program the fixed DMA controller parameters */
468 dma_channel = dma_private->dma_channel;
470 temp_link = dma_private->ld_buf_phys +
471 sizeof(struct fsl_dma_link_descriptor);
473 for (i = 0; i < NUM_DMA_LINKS; i++) {
474 dma_private->link[i].next = cpu_to_be64(temp_link);
476 temp_link += sizeof(struct fsl_dma_link_descriptor);
478 /* The last link descriptor points to the first */
479 dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys);
481 /* Tell the DMA controller where the first link descriptor is */
482 out_be32(&dma_channel->clndar,
483 CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys));
484 out_be32(&dma_channel->eclndar,
485 CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys));
487 /* The manual says the BCR must be clear before enabling EMP */
488 out_be32(&dma_channel->bcr, 0);
491 * Program the mode register for interrupts, external master control,
492 * and source/destination hold. Also clear the Channel Abort bit.
494 mr = in_be32(&dma_channel->mr) &
495 ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE);
498 * We want External Master Start and External Master Pause enabled,
499 * because the SSI is controlling the DMA controller. We want the DMA
500 * controller to be set up in advance, and then we signal only the SSI
501 * to start transferring.
503 * We want End-Of-Segment Interrupts enabled, because this will generate
504 * an interrupt at the end of each segment (each link descriptor
505 * represents one segment). Each DMA segment is the same thing as an
506 * ALSA period, so this is how we get an interrupt at the end of every
509 * We want Error Interrupt enabled, so that we can get an error if
510 * the DMA controller is mis-programmed somehow.
512 mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN |
515 /* For playback, we want the destination address to be held. For
516 capture, set the source address to be held. */
517 mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
518 CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE;
520 out_be32(&dma_channel->mr, mr);
526 * fsl_dma_hw_params: continue initializing the DMA links
528 * This function obtains hardware parameters about the opened stream and
529 * programs the DMA controller accordingly.
531 * One drawback of big-endian is that when copying integers of different
532 * sizes to a fixed-sized register, the address to which the integer must be
533 * copied is dependent on the size of the integer.
535 * For example, if P is the address of a 32-bit register, and X is a 32-bit
536 * integer, then X should be copied to address P. However, if X is a 16-bit
537 * integer, then it should be copied to P+2. If X is an 8-bit register,
538 * then it should be copied to P+3.
540 * So for playback of 8-bit samples, the DMA controller must transfer single
541 * bytes from the DMA buffer to the last byte of the STX0 register, i.e.
542 * offset by 3 bytes. For 16-bit samples, the offset is two bytes.
544 * For 24-bit samples, the offset is 1 byte. However, the DMA controller
545 * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4,
546 * and 8 bytes at a time). So we do not support packed 24-bit samples.
547 * 24-bit data must be padded to 32 bits.
549 static int fsl_dma_hw_params(struct snd_pcm_substream *substream,
550 struct snd_pcm_hw_params *hw_params)
552 struct snd_pcm_runtime *runtime = substream->runtime;
553 struct fsl_dma_private *dma_private = runtime->private_data;
554 struct snd_soc_pcm_runtime *rtd = substream->private_data;
555 struct device *dev = rtd->platform->dev;
557 /* Number of bits per sample */
558 unsigned int sample_bits =
559 snd_pcm_format_physical_width(params_format(hw_params));
561 /* Number of bytes per frame */
562 unsigned int sample_bytes = sample_bits / 8;
564 /* Bus address of SSI STX register */
565 dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys;
567 /* Size of the DMA buffer, in bytes */
568 size_t buffer_size = params_buffer_bytes(hw_params);
570 /* Number of bytes per period */
571 size_t period_size = params_period_bytes(hw_params);
573 /* Pointer to next period */
574 dma_addr_t temp_addr = substream->dma_buffer.addr;
576 /* Pointer to DMA controller */
577 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
579 u32 mr; /* DMA Mode Register */
583 /* Initialize our DMA tracking variables */
584 dma_private->period_size = period_size;
585 dma_private->num_periods = params_periods(hw_params);
586 dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size;
587 dma_private->dma_buf_next = dma_private->dma_buf_phys +
588 (NUM_DMA_LINKS * period_size);
590 if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
591 /* This happens if the number of periods == NUM_DMA_LINKS */
592 dma_private->dma_buf_next = dma_private->dma_buf_phys;
594 mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK |
595 CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK);
597 /* Due to a quirk of the SSI's STX register, the target address
598 * for the DMA operations depends on the sample size. So we calculate
599 * that offset here. While we're at it, also tell the DMA controller
600 * how much data to transfer per sample.
602 switch (sample_bits) {
604 mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1;
608 mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2;
612 mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4;
615 /* We should never get here */
616 dev_err(dev, "unsupported sample size %u\n", sample_bits);
621 * BWC determines how many bytes are sent/received before the DMA
622 * controller checks the SSI to see if it needs to stop. BWC should
623 * always be a multiple of the frame size, so that we always transmit
624 * whole frames. Each frame occupies two slots in the FIFO. The
625 * parameter for CCSR_DMA_MR_BWC() is rounded down the next power of two
626 * (MR[BWC] can only represent even powers of two).
628 * To simplify the process, we set BWC to the largest value that is
629 * less than or equal to the FIFO watermark. For playback, this ensures
630 * that we transfer the maximum amount without overrunning the FIFO.
631 * For capture, this ensures that we transfer the maximum amount without
632 * underrunning the FIFO.
635 * w = SSI watermark value (which equals f - 2)
636 * b = DMA bandwidth count (in bytes)
637 * s = sample size (in bytes, which equals frame_size * 2)
639 * For playback, we never transmit more than the transmit FIFO
640 * watermark, otherwise we might write more data than the FIFO can hold.
641 * The watermark is equal to the FIFO depth minus two.
643 * For capture, two equations must hold:
647 * So, b > 2 * s, but b must also be <= s * w. To simplify, we set
648 * b = s * w, which is equal to
649 * (dma_private->ssi_fifo_depth - 2) * sample_bytes.
651 mr |= CCSR_DMA_MR_BWC((dma_private->ssi_fifo_depth - 2) * sample_bytes);
653 out_be32(&dma_channel->mr, mr);
655 for (i = 0; i < NUM_DMA_LINKS; i++) {
656 struct fsl_dma_link_descriptor *link = &dma_private->link[i];
658 link->count = cpu_to_be32(period_size);
660 /* The snoop bit tells the DMA controller whether it should tell
661 * the ECM to snoop during a read or write to an address. For
662 * audio, we use DMA to transfer data between memory and an I/O
663 * device (the SSI's STX0 or SRX0 register). Snooping is only
664 * needed if there is a cache, so we need to snoop memory
665 * addresses only. For playback, that means we snoop the source
666 * but not the destination. For capture, we snoop the
667 * destination but not the source.
669 * Note that failing to snoop properly is unlikely to cause
670 * cache incoherency if the period size is larger than the
671 * size of L1 cache. This is because filling in one period will
672 * flush out the data for the previous period. So if you
673 * increased period_bytes_min to a large enough size, you might
674 * get more performance by not snooping, and you'll still be
675 * okay. You'll need to update fsl_dma_update_pointers() also.
677 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
678 link->source_addr = cpu_to_be32(temp_addr);
679 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
680 upper_32_bits(temp_addr));
682 link->dest_addr = cpu_to_be32(ssi_sxx_phys);
683 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP |
684 upper_32_bits(ssi_sxx_phys));
686 link->source_addr = cpu_to_be32(ssi_sxx_phys);
687 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP |
688 upper_32_bits(ssi_sxx_phys));
690 link->dest_addr = cpu_to_be32(temp_addr);
691 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
692 upper_32_bits(temp_addr));
695 temp_addr += period_size;
702 * fsl_dma_pointer: determine the current position of the DMA transfer
704 * This function is called by ALSA when ALSA wants to know where in the
705 * stream buffer the hardware currently is.
707 * For playback, the SAR register contains the physical address of the most
708 * recent DMA transfer. For capture, the value is in the DAR register.
710 * The base address of the buffer is stored in the source_addr field of the
711 * first link descriptor.
713 static snd_pcm_uframes_t fsl_dma_pointer(struct snd_pcm_substream *substream)
715 struct snd_pcm_runtime *runtime = substream->runtime;
716 struct fsl_dma_private *dma_private = runtime->private_data;
717 struct snd_soc_pcm_runtime *rtd = substream->private_data;
718 struct device *dev = rtd->platform->dev;
719 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
721 snd_pcm_uframes_t frames;
723 /* Obtain the current DMA pointer, but don't read the ESAD bits if we
724 * only have 32-bit DMA addresses. This function is typically called
725 * in interrupt context, so we need to optimize it.
727 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
728 position = in_be32(&dma_channel->sar);
729 #ifdef CONFIG_PHYS_64BIT
730 position |= (u64)(in_be32(&dma_channel->satr) &
731 CCSR_DMA_ATR_ESAD_MASK) << 32;
734 position = in_be32(&dma_channel->dar);
735 #ifdef CONFIG_PHYS_64BIT
736 position |= (u64)(in_be32(&dma_channel->datr) &
737 CCSR_DMA_ATR_ESAD_MASK) << 32;
742 * When capture is started, the SSI immediately starts to fill its FIFO.
743 * This means that the DMA controller is not started until the FIFO is
744 * full. However, ALSA calls this function before that happens, when
745 * MR.DAR is still zero. In this case, just return zero to indicate
746 * that nothing has been received yet.
751 if ((position < dma_private->dma_buf_phys) ||
752 (position > dma_private->dma_buf_end)) {
753 dev_err(dev, "dma pointer is out of range, halting stream\n");
754 return SNDRV_PCM_POS_XRUN;
757 frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys);
760 * If the current address is just past the end of the buffer, wrap it
763 if (frames == runtime->buffer_size)
770 * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params()
772 * Release the resources allocated in fsl_dma_hw_params() and de-program the
775 * This function can be called multiple times.
777 static int fsl_dma_hw_free(struct snd_pcm_substream *substream)
779 struct snd_pcm_runtime *runtime = substream->runtime;
780 struct fsl_dma_private *dma_private = runtime->private_data;
783 struct ccsr_dma_channel __iomem *dma_channel;
785 dma_channel = dma_private->dma_channel;
788 out_be32(&dma_channel->mr, CCSR_DMA_MR_CA);
789 out_be32(&dma_channel->mr, 0);
791 /* Reset all the other registers */
792 out_be32(&dma_channel->sr, -1);
793 out_be32(&dma_channel->clndar, 0);
794 out_be32(&dma_channel->eclndar, 0);
795 out_be32(&dma_channel->satr, 0);
796 out_be32(&dma_channel->sar, 0);
797 out_be32(&dma_channel->datr, 0);
798 out_be32(&dma_channel->dar, 0);
799 out_be32(&dma_channel->bcr, 0);
800 out_be32(&dma_channel->nlndar, 0);
801 out_be32(&dma_channel->enlndar, 0);
808 * fsl_dma_close: close the stream.
810 static int fsl_dma_close(struct snd_pcm_substream *substream)
812 struct snd_pcm_runtime *runtime = substream->runtime;
813 struct fsl_dma_private *dma_private = runtime->private_data;
814 struct snd_soc_pcm_runtime *rtd = substream->private_data;
815 struct device *dev = rtd->platform->dev;
816 struct dma_object *dma =
817 container_of(rtd->platform->driver, struct dma_object, dai);
820 if (dma_private->irq)
821 free_irq(dma_private->irq, dma_private);
823 /* Deallocate the fsl_dma_private structure */
824 dma_free_coherent(dev, sizeof(struct fsl_dma_private),
825 dma_private, dma_private->ld_buf_phys);
826 substream->runtime->private_data = NULL;
835 * Remove this PCM driver.
837 static void fsl_dma_free_dma_buffers(struct snd_pcm *pcm)
839 struct snd_pcm_substream *substream;
842 for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) {
843 substream = pcm->streams[i].substream;
845 snd_dma_free_pages(&substream->dma_buffer);
846 substream->dma_buffer.area = NULL;
847 substream->dma_buffer.addr = 0;
853 * find_ssi_node -- returns the SSI node that points to his DMA channel node
855 * Although this DMA driver attempts to operate independently of the other
856 * devices, it still needs to determine some information about the SSI device
857 * that it's working with. Unfortunately, the device tree does not contain
858 * a pointer from the DMA channel node to the SSI node -- the pointer goes the
859 * other way. So we need to scan the device tree for SSI nodes until we find
860 * the one that points to the given DMA channel node. It's ugly, but at least
861 * it's contained in this one function.
863 static struct device_node *find_ssi_node(struct device_node *dma_channel_np)
865 struct device_node *ssi_np, *np;
867 for_each_compatible_node(ssi_np, NULL, "fsl,mpc8610-ssi") {
868 /* Check each DMA phandle to see if it points to us. We
869 * assume that device_node pointers are a valid comparison.
871 np = of_parse_phandle(ssi_np, "fsl,playback-dma", 0);
873 if (np == dma_channel_np)
876 np = of_parse_phandle(ssi_np, "fsl,capture-dma", 0);
878 if (np == dma_channel_np)
885 static struct snd_pcm_ops fsl_dma_ops = {
886 .open = fsl_dma_open,
887 .close = fsl_dma_close,
888 .ioctl = snd_pcm_lib_ioctl,
889 .hw_params = fsl_dma_hw_params,
890 .hw_free = fsl_dma_hw_free,
891 .pointer = fsl_dma_pointer,
894 static int fsl_soc_dma_probe(struct platform_device *pdev)
896 struct dma_object *dma;
897 struct device_node *np = pdev->dev.of_node;
898 struct device_node *ssi_np;
900 const uint32_t *iprop;
903 /* Find the SSI node that points to us. */
904 ssi_np = find_ssi_node(np);
906 dev_err(&pdev->dev, "cannot find parent SSI node\n");
910 ret = of_address_to_resource(ssi_np, 0, &res);
912 dev_err(&pdev->dev, "could not determine resources for %s\n",
918 dma = kzalloc(sizeof(*dma) + strlen(np->full_name), GFP_KERNEL);
920 dev_err(&pdev->dev, "could not allocate dma object\n");
925 strcpy(dma->path, np->full_name);
926 dma->dai.ops = &fsl_dma_ops;
927 dma->dai.pcm_new = fsl_dma_new;
928 dma->dai.pcm_free = fsl_dma_free_dma_buffers;
930 /* Store the SSI-specific information that we need */
931 dma->ssi_stx_phys = res.start + offsetof(struct ccsr_ssi, stx0);
932 dma->ssi_srx_phys = res.start + offsetof(struct ccsr_ssi, srx0);
934 iprop = of_get_property(ssi_np, "fsl,fifo-depth", NULL);
936 dma->ssi_fifo_depth = be32_to_cpup(iprop);
938 /* Older 8610 DTs didn't have the fifo-depth property */
939 dma->ssi_fifo_depth = 8;
943 ret = snd_soc_register_platform(&pdev->dev, &dma->dai);
945 dev_err(&pdev->dev, "could not register platform\n");
950 dma->channel = of_iomap(np, 0);
951 dma->irq = irq_of_parse_and_map(np, 0);
953 dev_set_drvdata(&pdev->dev, dma);
958 static int fsl_soc_dma_remove(struct platform_device *pdev)
960 struct dma_object *dma = dev_get_drvdata(&pdev->dev);
962 snd_soc_unregister_platform(&pdev->dev);
963 iounmap(dma->channel);
964 irq_dispose_mapping(dma->irq);
970 static const struct of_device_id fsl_soc_dma_ids[] = {
971 { .compatible = "fsl,ssi-dma-channel", },
974 MODULE_DEVICE_TABLE(of, fsl_soc_dma_ids);
976 static struct platform_driver fsl_soc_dma_driver = {
978 .name = "fsl-pcm-audio",
979 .owner = THIS_MODULE,
980 .of_match_table = fsl_soc_dma_ids,
982 .probe = fsl_soc_dma_probe,
983 .remove = fsl_soc_dma_remove,
986 module_platform_driver(fsl_soc_dma_driver);
988 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
989 MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM Driver");
990 MODULE_LICENSE("GPL v2");