2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
4 * Multi-channel Audio Serial Port Driver
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
24 #include <linux/clk.h>
25 #include <linux/pm_runtime.h>
27 #include <linux/of_platform.h>
28 #include <linux/of_device.h>
30 #include <sound/core.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/initval.h>
34 #include <sound/soc.h>
35 #include <sound/dmaengine_pcm.h>
37 #include "davinci-pcm.h"
38 #include "davinci-mcasp.h"
40 struct davinci_mcasp {
41 struct davinci_pcm_dma_params dma_params[2];
42 struct snd_dmaengine_dai_dma_data dma_data[2];
47 /* McASP specific data */
56 /* McASP FIFO related */
62 #ifdef CONFIG_PM_SLEEP
75 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
78 void __iomem *reg = mcasp->base + offset;
79 __raw_writel(__raw_readl(reg) | val, reg);
82 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
85 void __iomem *reg = mcasp->base + offset;
86 __raw_writel((__raw_readl(reg) & ~(val)), reg);
89 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
92 void __iomem *reg = mcasp->base + offset;
93 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
96 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
99 __raw_writel(val, mcasp->base + offset);
102 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
104 return (u32)__raw_readl(mcasp->base + offset);
107 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
111 mcasp_set_bits(mcasp, ctl_reg, val);
113 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
114 /* loop count is to avoid the lock-up */
115 for (i = 0; i < 1000; i++) {
116 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
120 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
121 printk(KERN_ERR "GBLCTL write error\n");
124 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
126 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
127 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
129 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
132 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
134 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
135 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
138 * When ASYNC == 0 the transmit and receive sections operate
139 * synchronously from the transmit clock and frame sync. We need to make
140 * sure that the TX signlas are enabled when starting reception.
142 if (mcasp_is_synchronous(mcasp)) {
143 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
144 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
147 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
148 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
150 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
151 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
152 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
154 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
155 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
157 if (mcasp_is_synchronous(mcasp))
158 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
161 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
166 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
167 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
168 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
169 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
171 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
172 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
173 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
174 for (i = 0; i < mcasp->num_serializer; i++) {
175 if (mcasp->serial_dir[i] == TX_MODE) {
181 /* wait for TX ready */
183 while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(offset)) &
184 TXSTATE) && (cnt < 100000))
187 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
190 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
196 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
197 if (mcasp->txnumevt) { /* enable FIFO */
198 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
199 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
200 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
202 mcasp_start_tx(mcasp);
204 if (mcasp->rxnumevt) { /* enable FIFO */
205 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
206 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
207 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
209 mcasp_start_rx(mcasp);
213 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
216 * In synchronous mode stop the TX clocks if no other stream is
219 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
220 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
222 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
223 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
226 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
231 * In synchronous mode keep TX clocks running if the capture stream is
234 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
235 val = TXHCLKRST | TXCLKRST | TXFSRST;
237 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
238 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
241 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
247 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
248 if (mcasp->txnumevt) { /* disable FIFO */
249 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
250 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
252 mcasp_stop_tx(mcasp);
254 if (mcasp->rxnumevt) { /* disable FIFO */
255 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
256 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
258 mcasp_stop_rx(mcasp);
262 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
265 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
268 pm_runtime_get_sync(mcasp->dev);
269 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
270 case SND_SOC_DAIFMT_DSP_B:
271 case SND_SOC_DAIFMT_AC97:
272 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
273 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
276 /* configure a full-word SYNC pulse (LRCLK) */
277 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
278 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
280 /* make 1st data bit occur one ACLK cycle after the frame sync */
281 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
282 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
286 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
287 case SND_SOC_DAIFMT_CBS_CFS:
288 /* codec is clock and frame slave */
289 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
290 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
292 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
293 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
295 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
296 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
298 case SND_SOC_DAIFMT_CBM_CFS:
299 /* codec is clock master and frame slave */
300 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
301 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
303 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
304 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
306 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
307 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
309 case SND_SOC_DAIFMT_CBM_CFM:
310 /* codec is clock and frame master */
311 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
312 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
314 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
315 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
317 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
318 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
326 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
327 case SND_SOC_DAIFMT_IB_NF:
328 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
329 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
331 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
332 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
335 case SND_SOC_DAIFMT_NB_IF:
336 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
337 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
339 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
340 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
343 case SND_SOC_DAIFMT_IB_IF:
344 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
345 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
347 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
348 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
351 case SND_SOC_DAIFMT_NB_NF:
352 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
353 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
355 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
356 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
364 pm_runtime_put_sync(mcasp->dev);
368 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
370 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
373 case 0: /* MCLK divider */
374 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
375 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
376 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
377 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
380 case 1: /* BCLK divider */
381 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
382 ACLKXDIV(div - 1), ACLKXDIV_MASK);
383 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
384 ACLKRDIV(div - 1), ACLKRDIV_MASK);
387 case 2: /* BCLK/LRCLK ratio */
388 mcasp->bclk_lrclk_ratio = div;
398 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
399 unsigned int freq, int dir)
401 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
403 if (dir == SND_SOC_CLOCK_OUT) {
404 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
405 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
406 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
408 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
409 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
410 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
416 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
420 u32 tx_rotate = (word_length / 4) & 0x7;
421 u32 rx_rotate = (32 - word_length) / 4;
422 u32 mask = (1ULL << word_length) - 1;
425 * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
426 * callback, take it into account here. That allows us to for example
427 * send 32 bits per channel to the codec, while only 16 of them carry
429 * The clock ratio is given for a full period of data (for I2S format
430 * both left and right channels), so it has to be divided by number of
431 * tdm-slots (for I2S - divided by 2).
433 if (mcasp->bclk_lrclk_ratio)
434 word_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots;
436 /* mapping of the XSSZ bit-field as described in the datasheet */
437 fmt = (word_length >> 1) - 1;
439 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
440 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
442 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
444 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
446 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
448 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
451 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
456 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
463 u8 slots = mcasp->tdm_slots;
464 u8 max_active_serializers = (channels + slots - 1) / slots;
466 /* Default configuration */
467 if (mcasp->version != MCASP_VERSION_4)
468 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
470 /* All PINS as McASP */
471 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
473 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
474 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
475 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
477 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
478 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
481 for (i = 0; i < mcasp->num_serializer; i++) {
482 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
483 mcasp->serial_dir[i]);
484 if (mcasp->serial_dir[i] == TX_MODE &&
485 tx_ser < max_active_serializers) {
486 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
488 } else if (mcasp->serial_dir[i] == RX_MODE &&
489 rx_ser < max_active_serializers) {
490 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
493 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
494 SRMOD_INACTIVE, SRMOD_MASK);
498 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
503 if (ser < max_active_serializers) {
504 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
505 "enabled in mcasp (%d)\n", channels, ser * slots);
509 if (mcasp->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
510 if (mcasp->txnumevt * tx_ser > 64)
513 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
514 mcasp_mod_bits(mcasp, reg, tx_ser, NUMDMA_MASK);
515 mcasp_mod_bits(mcasp, reg, ((mcasp->txnumevt * tx_ser) << 8),
519 if (mcasp->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
520 if (mcasp->rxnumevt * rx_ser > 64)
523 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
524 mcasp_mod_bits(mcasp, reg, rx_ser, NUMDMA_MASK);
525 mcasp_mod_bits(mcasp, reg, ((mcasp->rxnumevt * rx_ser) << 8),
532 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream)
538 if ((mcasp->tdm_slots < 2) || (mcasp->tdm_slots > 32)) {
539 dev_err(mcasp->dev, "tdm slot %d not supported\n",
544 active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots;
545 for (i = 0; i < active_slots; i++)
548 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
550 if (!mcasp->dat_port)
553 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
554 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
555 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
556 FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF));
558 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
559 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
560 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
561 FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF));
567 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp)
569 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
571 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
573 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
574 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
576 /* Set the TX tdm : for all the slots */
577 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
579 /* Set the TX clock controls : div = 1 and internal */
580 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
582 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
584 /* Only 44100 and 48000 are valid, both have the same setting */
585 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
588 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
593 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
594 struct snd_pcm_hw_params *params,
595 struct snd_soc_dai *cpu_dai)
597 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
598 struct davinci_pcm_dma_params *dma_params =
599 &mcasp->dma_params[substream->stream];
600 struct snd_dmaengine_dai_dma_data *dma_data =
601 &mcasp->dma_data[substream->stream];
604 u8 slots = mcasp->tdm_slots;
605 u8 active_serializers;
608 struct snd_interval *pcm_channels = hw_param_interval(params,
609 SNDRV_PCM_HW_PARAM_CHANNELS);
610 channels = pcm_channels->min;
612 active_serializers = (channels + slots - 1) / slots;
614 if (mcasp_common_hw_param(mcasp, substream->stream, channels) == -EINVAL)
616 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
617 fifo_level = mcasp->txnumevt * active_serializers;
619 fifo_level = mcasp->rxnumevt * active_serializers;
621 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
622 ret = mcasp_dit_hw_param(mcasp);
624 ret = mcasp_i2s_hw_param(mcasp, substream->stream);
629 switch (params_format(params)) {
630 case SNDRV_PCM_FORMAT_U8:
631 case SNDRV_PCM_FORMAT_S8:
632 dma_params->data_type = 1;
636 case SNDRV_PCM_FORMAT_U16_LE:
637 case SNDRV_PCM_FORMAT_S16_LE:
638 dma_params->data_type = 2;
642 case SNDRV_PCM_FORMAT_U24_3LE:
643 case SNDRV_PCM_FORMAT_S24_3LE:
644 dma_params->data_type = 3;
648 case SNDRV_PCM_FORMAT_U24_LE:
649 case SNDRV_PCM_FORMAT_S24_LE:
650 case SNDRV_PCM_FORMAT_U32_LE:
651 case SNDRV_PCM_FORMAT_S32_LE:
652 dma_params->data_type = 4;
657 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
661 if (mcasp->version == MCASP_VERSION_2 && !fifo_level)
662 dma_params->acnt = 4;
664 dma_params->acnt = dma_params->data_type;
666 dma_params->fifo_level = fifo_level;
667 dma_data->maxburst = fifo_level;
669 davinci_config_channel_size(mcasp, word_length);
674 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
675 int cmd, struct snd_soc_dai *cpu_dai)
677 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
681 case SNDRV_PCM_TRIGGER_RESUME:
682 case SNDRV_PCM_TRIGGER_START:
683 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
684 davinci_mcasp_start(mcasp, substream->stream);
686 case SNDRV_PCM_TRIGGER_SUSPEND:
687 case SNDRV_PCM_TRIGGER_STOP:
688 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
689 davinci_mcasp_stop(mcasp, substream->stream);
699 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
700 struct snd_soc_dai *dai)
702 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
704 if (mcasp->version == MCASP_VERSION_4)
705 snd_soc_dai_set_dma_data(dai, substream,
706 &mcasp->dma_data[substream->stream]);
708 snd_soc_dai_set_dma_data(dai, substream, mcasp->dma_params);
713 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
714 .startup = davinci_mcasp_startup,
715 .trigger = davinci_mcasp_trigger,
716 .hw_params = davinci_mcasp_hw_params,
717 .set_fmt = davinci_mcasp_set_dai_fmt,
718 .set_clkdiv = davinci_mcasp_set_clkdiv,
719 .set_sysclk = davinci_mcasp_set_sysclk,
722 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
724 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
725 SNDRV_PCM_FMTBIT_U8 | \
726 SNDRV_PCM_FMTBIT_S16_LE | \
727 SNDRV_PCM_FMTBIT_U16_LE | \
728 SNDRV_PCM_FMTBIT_S24_LE | \
729 SNDRV_PCM_FMTBIT_U24_LE | \
730 SNDRV_PCM_FMTBIT_S24_3LE | \
731 SNDRV_PCM_FMTBIT_U24_3LE | \
732 SNDRV_PCM_FMTBIT_S32_LE | \
733 SNDRV_PCM_FMTBIT_U32_LE)
735 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
737 .name = "davinci-mcasp.0",
740 .channels_max = 32 * 16,
741 .rates = DAVINCI_MCASP_RATES,
742 .formats = DAVINCI_MCASP_PCM_FMTS,
746 .channels_max = 32 * 16,
747 .rates = DAVINCI_MCASP_RATES,
748 .formats = DAVINCI_MCASP_PCM_FMTS,
750 .ops = &davinci_mcasp_dai_ops,
754 .name = "davinci-mcasp.1",
758 .rates = DAVINCI_MCASP_RATES,
759 .formats = DAVINCI_MCASP_PCM_FMTS,
761 .ops = &davinci_mcasp_dai_ops,
766 static const struct snd_soc_component_driver davinci_mcasp_component = {
767 .name = "davinci-mcasp",
770 /* Some HW specific values and defaults. The rest is filled in from DT. */
771 static struct snd_platform_data dm646x_mcasp_pdata = {
772 .tx_dma_offset = 0x400,
773 .rx_dma_offset = 0x400,
774 .asp_chan_q = EVENTQ_0,
775 .version = MCASP_VERSION_1,
778 static struct snd_platform_data da830_mcasp_pdata = {
779 .tx_dma_offset = 0x2000,
780 .rx_dma_offset = 0x2000,
781 .asp_chan_q = EVENTQ_0,
782 .version = MCASP_VERSION_2,
785 static struct snd_platform_data am33xx_mcasp_pdata = {
788 .asp_chan_q = EVENTQ_0,
789 .version = MCASP_VERSION_3,
792 static struct snd_platform_data dra7_mcasp_pdata = {
793 .tx_dma_offset = 0x200,
794 .rx_dma_offset = 0x284,
795 .asp_chan_q = EVENTQ_0,
796 .version = MCASP_VERSION_4,
799 static const struct of_device_id mcasp_dt_ids[] = {
801 .compatible = "ti,dm646x-mcasp-audio",
802 .data = &dm646x_mcasp_pdata,
805 .compatible = "ti,da830-mcasp-audio",
806 .data = &da830_mcasp_pdata,
809 .compatible = "ti,am33xx-mcasp-audio",
810 .data = &am33xx_mcasp_pdata,
813 .compatible = "ti,dra7-mcasp-audio",
814 .data = &dra7_mcasp_pdata,
818 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
820 static int mcasp_reparent_fck(struct platform_device *pdev)
822 struct device_node *node = pdev->dev.of_node;
823 struct clk *gfclk, *parent_clk;
824 const char *parent_name;
830 parent_name = of_get_property(node, "fck_parent", NULL);
834 gfclk = clk_get(&pdev->dev, "fck");
836 dev_err(&pdev->dev, "failed to get fck\n");
837 return PTR_ERR(gfclk);
840 parent_clk = clk_get(NULL, parent_name);
841 if (IS_ERR(parent_clk)) {
842 dev_err(&pdev->dev, "failed to get parent clock\n");
843 ret = PTR_ERR(parent_clk);
847 ret = clk_set_parent(gfclk, parent_clk);
849 dev_err(&pdev->dev, "failed to reparent fck\n");
860 static struct snd_platform_data *davinci_mcasp_set_pdata_from_of(
861 struct platform_device *pdev)
863 struct device_node *np = pdev->dev.of_node;
864 struct snd_platform_data *pdata = NULL;
865 const struct of_device_id *match =
866 of_match_device(mcasp_dt_ids, &pdev->dev);
867 struct of_phandle_args dma_spec;
869 const u32 *of_serial_dir32;
873 if (pdev->dev.platform_data) {
874 pdata = pdev->dev.platform_data;
877 pdata = (struct snd_platform_data *) match->data;
879 /* control shouldn't reach here. something is wrong */
884 ret = of_property_read_u32(np, "op-mode", &val);
886 pdata->op_mode = val;
888 ret = of_property_read_u32(np, "tdm-slots", &val);
890 if (val < 2 || val > 32) {
892 "tdm-slots must be in rage [2-32]\n");
897 pdata->tdm_slots = val;
900 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
902 if (of_serial_dir32) {
903 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
904 (sizeof(*of_serial_dir) * val),
906 if (!of_serial_dir) {
911 for (i = 0; i < val; i++)
912 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
914 pdata->num_serializer = val;
915 pdata->serial_dir = of_serial_dir;
918 ret = of_property_match_string(np, "dma-names", "tx");
922 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
927 pdata->tx_dma_channel = dma_spec.args[0];
929 ret = of_property_match_string(np, "dma-names", "rx");
933 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
938 pdata->rx_dma_channel = dma_spec.args[0];
940 ret = of_property_read_u32(np, "tx-num-evt", &val);
942 pdata->txnumevt = val;
944 ret = of_property_read_u32(np, "rx-num-evt", &val);
946 pdata->rxnumevt = val;
948 ret = of_property_read_u32(np, "sram-size-playback", &val);
950 pdata->sram_size_playback = val;
952 ret = of_property_read_u32(np, "sram-size-capture", &val);
954 pdata->sram_size_capture = val;
960 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
967 static int davinci_mcasp_probe(struct platform_device *pdev)
969 struct davinci_pcm_dma_params *dma_data;
970 struct resource *mem, *ioarea, *res, *dat;
971 struct snd_platform_data *pdata;
972 struct davinci_mcasp *mcasp;
975 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
976 dev_err(&pdev->dev, "No platform data supplied\n");
980 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
985 pdata = davinci_mcasp_set_pdata_from_of(pdev);
987 dev_err(&pdev->dev, "no platform data\n");
991 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
994 "\"mpu\" mem resource not found, using index 0\n");
995 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
997 dev_err(&pdev->dev, "no mem resource?\n");
1002 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
1003 resource_size(mem), pdev->name);
1005 dev_err(&pdev->dev, "Audio region already claimed\n");
1009 pm_runtime_enable(&pdev->dev);
1011 ret = pm_runtime_get_sync(&pdev->dev);
1012 if (IS_ERR_VALUE(ret)) {
1013 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
1017 mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
1019 dev_err(&pdev->dev, "ioremap failed\n");
1021 goto err_release_clk;
1024 mcasp->op_mode = pdata->op_mode;
1025 mcasp->tdm_slots = pdata->tdm_slots;
1026 mcasp->num_serializer = pdata->num_serializer;
1027 mcasp->serial_dir = pdata->serial_dir;
1028 mcasp->version = pdata->version;
1029 mcasp->txnumevt = pdata->txnumevt;
1030 mcasp->rxnumevt = pdata->rxnumevt;
1032 mcasp->dev = &pdev->dev;
1034 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1036 mcasp->dat_port = true;
1038 dma_data = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
1039 dma_data->asp_chan_q = pdata->asp_chan_q;
1040 dma_data->ram_chan_q = pdata->ram_chan_q;
1041 dma_data->sram_pool = pdata->sram_pool;
1042 dma_data->sram_size = pdata->sram_size_playback;
1044 dma_data->dma_addr = dat->start;
1046 dma_data->dma_addr = mem->start + pdata->tx_dma_offset;
1048 /* Unconditional dmaengine stuff */
1049 mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr = dma_data->dma_addr;
1051 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1053 dma_data->channel = res->start;
1055 dma_data->channel = pdata->tx_dma_channel;
1057 dma_data = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE];
1058 dma_data->asp_chan_q = pdata->asp_chan_q;
1059 dma_data->ram_chan_q = pdata->ram_chan_q;
1060 dma_data->sram_pool = pdata->sram_pool;
1061 dma_data->sram_size = pdata->sram_size_capture;
1063 dma_data->dma_addr = dat->start;
1065 dma_data->dma_addr = mem->start + pdata->rx_dma_offset;
1067 /* Unconditional dmaengine stuff */
1068 mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr = dma_data->dma_addr;
1070 if (mcasp->version < MCASP_VERSION_3) {
1071 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
1072 /* dma_data->dma_addr is pointing to the data port address */
1073 mcasp->dat_port = true;
1075 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1078 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1080 dma_data->channel = res->start;
1082 dma_data->channel = pdata->rx_dma_channel;
1084 /* Unconditional dmaengine stuff */
1085 mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data = "tx";
1086 mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE].filter_data = "rx";
1088 dev_set_drvdata(&pdev->dev, mcasp);
1090 mcasp_reparent_fck(pdev);
1092 ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component,
1093 &davinci_mcasp_dai[pdata->op_mode], 1);
1096 goto err_release_clk;
1098 if (mcasp->version != MCASP_VERSION_4) {
1099 ret = davinci_soc_platform_register(&pdev->dev);
1101 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1102 goto err_unregister_component;
1108 err_unregister_component:
1109 snd_soc_unregister_component(&pdev->dev);
1111 pm_runtime_put_sync(&pdev->dev);
1112 pm_runtime_disable(&pdev->dev);
1116 static int davinci_mcasp_remove(struct platform_device *pdev)
1118 struct davinci_mcasp *mcasp = dev_get_drvdata(&pdev->dev);
1120 snd_soc_unregister_component(&pdev->dev);
1121 if (mcasp->version != MCASP_VERSION_4)
1122 davinci_soc_platform_unregister(&pdev->dev);
1124 pm_runtime_put_sync(&pdev->dev);
1125 pm_runtime_disable(&pdev->dev);
1130 #ifdef CONFIG_PM_SLEEP
1131 static int davinci_mcasp_suspend(struct device *dev)
1133 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
1135 mcasp->context.txfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG);
1136 mcasp->context.rxfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
1137 mcasp->context.txfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMT_REG);
1138 mcasp->context.rxfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMT_REG);
1139 mcasp->context.aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
1140 mcasp->context.aclkrctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG);
1141 mcasp->context.pdir = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
1146 static int davinci_mcasp_resume(struct device *dev)
1148 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
1150 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, mcasp->context.txfmtctl);
1151 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG, mcasp->context.rxfmtctl);
1152 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMT_REG, mcasp->context.txfmt);
1153 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMT_REG, mcasp->context.rxfmt);
1154 mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, mcasp->context.aclkxctl);
1155 mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, mcasp->context.aclkrctl);
1156 mcasp_set_reg(mcasp, DAVINCI_MCASP_PDIR_REG, mcasp->context.pdir);
1162 SIMPLE_DEV_PM_OPS(davinci_mcasp_pm_ops,
1163 davinci_mcasp_suspend,
1164 davinci_mcasp_resume);
1166 static struct platform_driver davinci_mcasp_driver = {
1167 .probe = davinci_mcasp_probe,
1168 .remove = davinci_mcasp_remove,
1170 .name = "davinci-mcasp",
1171 .owner = THIS_MODULE,
1172 .pm = &davinci_mcasp_pm_ops,
1173 .of_match_table = mcasp_dt_ids,
1177 module_platform_driver(davinci_mcasp_driver);
1179 MODULE_AUTHOR("Steve Chen");
1180 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1181 MODULE_LICENSE("GPL");