sound/soc/codecs/wsa881x.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2015-2017, The Linux Foundation.
   3 // Copyright (c) 2019, Linaro Limited
   4
   5 #include <linux/bitops.h>
   6 #include <linux/gpio.h>
   7 #include <linux/gpio/consumer.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/of_gpio.h>
  12 #include <linux/regmap.h>
  13 #include <linux/slab.h>
  14 #include <linux/soundwire/sdw.h>
  15 #include <linux/soundwire/sdw_registers.h>
  16 #include <linux/soundwire/sdw_type.h>
  17 #include <sound/soc.h>
  18 #include <sound/tlv.h>
  19
  20 #define WSA881X_DIGITAL_BASE            0x3000
  21 #define WSA881X_ANALOG_BASE             0x3100
  22
  23 /* Digital register address space */
  24 #define WSA881X_CHIP_ID0                        (WSA881X_DIGITAL_BASE + 0x0000)
  25 #define WSA881X_CHIP_ID1                        (WSA881X_DIGITAL_BASE + 0x0001)
  26 #define WSA881X_CHIP_ID2                        (WSA881X_DIGITAL_BASE + 0x0002)
  27 #define WSA881X_CHIP_ID3                        (WSA881X_DIGITAL_BASE + 0x0003)
  28 #define WSA881X_BUS_ID                          (WSA881X_DIGITAL_BASE + 0x0004)
  29 #define WSA881X_CDC_RST_CTL                     (WSA881X_DIGITAL_BASE + 0x0005)
  30 #define WSA881X_CDC_TOP_CLK_CTL                 (WSA881X_DIGITAL_BASE + 0x0006)
  31 #define WSA881X_CDC_ANA_CLK_CTL                 (WSA881X_DIGITAL_BASE + 0x0007)
  32 #define WSA881X_CDC_DIG_CLK_CTL                 (WSA881X_DIGITAL_BASE + 0x0008)
  33 #define WSA881X_CLOCK_CONFIG                    (WSA881X_DIGITAL_BASE + 0x0009)
  34 #define WSA881X_ANA_CTL                         (WSA881X_DIGITAL_BASE + 0x000A)
  35 #define WSA881X_SWR_RESET_EN                    (WSA881X_DIGITAL_BASE + 0x000B)
  36 #define WSA881X_RESET_CTL                       (WSA881X_DIGITAL_BASE + 0x000C)
  37 #define WSA881X_TADC_VALUE_CTL                  (WSA881X_DIGITAL_BASE + 0x000F)
  38 #define WSA881X_TEMP_DETECT_CTL                 (WSA881X_DIGITAL_BASE + 0x0010)
  39 #define WSA881X_TEMP_MSB                        (WSA881X_DIGITAL_BASE + 0x0011)
  40 #define WSA881X_TEMP_LSB                        (WSA881X_DIGITAL_BASE + 0x0012)
  41 #define WSA881X_TEMP_CONFIG0                    (WSA881X_DIGITAL_BASE + 0x0013)
  42 #define WSA881X_TEMP_CONFIG1                    (WSA881X_DIGITAL_BASE + 0x0014)
  43 #define WSA881X_CDC_CLIP_CTL                    (WSA881X_DIGITAL_BASE + 0x0015)
  44 #define WSA881X_SDM_PDM9_LSB                    (WSA881X_DIGITAL_BASE + 0x0016)
  45 #define WSA881X_SDM_PDM9_MSB                    (WSA881X_DIGITAL_BASE + 0x0017)
  46 #define WSA881X_CDC_RX_CTL                      (WSA881X_DIGITAL_BASE + 0x0018)
  47 #define WSA881X_DEM_BYPASS_DATA0                (WSA881X_DIGITAL_BASE + 0x0019)
  48 #define WSA881X_DEM_BYPASS_DATA1                (WSA881X_DIGITAL_BASE + 0x001A)
  49 #define WSA881X_DEM_BYPASS_DATA2                (WSA881X_DIGITAL_BASE + 0x001B)
  50 #define WSA881X_DEM_BYPASS_DATA3                (WSA881X_DIGITAL_BASE + 0x001C)
  51 #define WSA881X_OTP_CTRL0                       (WSA881X_DIGITAL_BASE + 0x001D)
  52 #define WSA881X_OTP_CTRL1                       (WSA881X_DIGITAL_BASE + 0x001E)
  53 #define WSA881X_HDRIVE_CTL_GROUP1               (WSA881X_DIGITAL_BASE + 0x001F)
  54 #define WSA881X_INTR_MODE                       (WSA881X_DIGITAL_BASE + 0x0020)
  55 #define WSA881X_INTR_MASK                       (WSA881X_DIGITAL_BASE + 0x0021)
  56 #define WSA881X_INTR_STATUS                     (WSA881X_DIGITAL_BASE + 0x0022)
  57 #define WSA881X_INTR_CLEAR                      (WSA881X_DIGITAL_BASE + 0x0023)
  58 #define WSA881X_INTR_LEVEL                      (WSA881X_DIGITAL_BASE + 0x0024)
  59 #define WSA881X_INTR_SET                        (WSA881X_DIGITAL_BASE + 0x0025)
  60 #define WSA881X_INTR_TEST                       (WSA881X_DIGITAL_BASE + 0x0026)
  61 #define WSA881X_PDM_TEST_MODE                   (WSA881X_DIGITAL_BASE + 0x0030)
  62 #define WSA881X_ATE_TEST_MODE                   (WSA881X_DIGITAL_BASE + 0x0031)
  63 #define WSA881X_PIN_CTL_MODE                    (WSA881X_DIGITAL_BASE + 0x0032)
  64 #define WSA881X_PIN_CTL_OE                      (WSA881X_DIGITAL_BASE + 0x0033)
  65 #define WSA881X_PIN_WDATA_IOPAD                 (WSA881X_DIGITAL_BASE + 0x0034)
  66 #define WSA881X_PIN_STATUS                      (WSA881X_DIGITAL_BASE + 0x0035)
  67 #define WSA881X_DIG_DEBUG_MODE                  (WSA881X_DIGITAL_BASE + 0x0037)
  68 #define WSA881X_DIG_DEBUG_SEL                   (WSA881X_DIGITAL_BASE + 0x0038)
  69 #define WSA881X_DIG_DEBUG_EN                    (WSA881X_DIGITAL_BASE + 0x0039)
  70 #define WSA881X_SWR_HM_TEST1                    (WSA881X_DIGITAL_BASE + 0x003B)
  71 #define WSA881X_SWR_HM_TEST2                    (WSA881X_DIGITAL_BASE + 0x003C)
  72 #define WSA881X_TEMP_DETECT_DBG_CTL             (WSA881X_DIGITAL_BASE + 0x003D)
  73 #define WSA881X_TEMP_DEBUG_MSB                  (WSA881X_DIGITAL_BASE + 0x003E)
  74 #define WSA881X_TEMP_DEBUG_LSB                  (WSA881X_DIGITAL_BASE + 0x003F)
  75 #define WSA881X_SAMPLE_EDGE_SEL                 (WSA881X_DIGITAL_BASE + 0x0044)
  76 #define WSA881X_IOPAD_CTL                       (WSA881X_DIGITAL_BASE + 0x0045)
  77 #define WSA881X_SPARE_0                         (WSA881X_DIGITAL_BASE + 0x0050)
  78 #define WSA881X_SPARE_1                         (WSA881X_DIGITAL_BASE + 0x0051)
  79 #define WSA881X_SPARE_2                         (WSA881X_DIGITAL_BASE + 0x0052)
  80 #define WSA881X_OTP_REG_0                       (WSA881X_DIGITAL_BASE + 0x0080)
  81 #define WSA881X_OTP_REG_1                       (WSA881X_DIGITAL_BASE + 0x0081)
  82 #define WSA881X_OTP_REG_2                       (WSA881X_DIGITAL_BASE + 0x0082)
  83 #define WSA881X_OTP_REG_3                       (WSA881X_DIGITAL_BASE + 0x0083)
  84 #define WSA881X_OTP_REG_4                       (WSA881X_DIGITAL_BASE + 0x0084)
  85 #define WSA881X_OTP_REG_5                       (WSA881X_DIGITAL_BASE + 0x0085)
  86 #define WSA881X_OTP_REG_6                       (WSA881X_DIGITAL_BASE + 0x0086)
  87 #define WSA881X_OTP_REG_7                       (WSA881X_DIGITAL_BASE + 0x0087)
  88 #define WSA881X_OTP_REG_8                       (WSA881X_DIGITAL_BASE + 0x0088)
  89 #define WSA881X_OTP_REG_9                       (WSA881X_DIGITAL_BASE + 0x0089)
  90 #define WSA881X_OTP_REG_10                      (WSA881X_DIGITAL_BASE + 0x008A)
  91 #define WSA881X_OTP_REG_11                      (WSA881X_DIGITAL_BASE + 0x008B)
  92 #define WSA881X_OTP_REG_12                      (WSA881X_DIGITAL_BASE + 0x008C)
  93 #define WSA881X_OTP_REG_13                      (WSA881X_DIGITAL_BASE + 0x008D)
  94 #define WSA881X_OTP_REG_14                      (WSA881X_DIGITAL_BASE + 0x008E)
  95 #define WSA881X_OTP_REG_15                      (WSA881X_DIGITAL_BASE + 0x008F)
  96 #define WSA881X_OTP_REG_16                      (WSA881X_DIGITAL_BASE + 0x0090)
  97 #define WSA881X_OTP_REG_17                      (WSA881X_DIGITAL_BASE + 0x0091)
  98 #define WSA881X_OTP_REG_18                      (WSA881X_DIGITAL_BASE + 0x0092)
  99 #define WSA881X_OTP_REG_19                      (WSA881X_DIGITAL_BASE + 0x0093)
 100 #define WSA881X_OTP_REG_20                      (WSA881X_DIGITAL_BASE + 0x0094)
 101 #define WSA881X_OTP_REG_21                      (WSA881X_DIGITAL_BASE + 0x0095)
 102 #define WSA881X_OTP_REG_22                      (WSA881X_DIGITAL_BASE + 0x0096)
 103 #define WSA881X_OTP_REG_23                      (WSA881X_DIGITAL_BASE + 0x0097)
 104 #define WSA881X_OTP_REG_24                      (WSA881X_DIGITAL_BASE + 0x0098)
 105 #define WSA881X_OTP_REG_25                      (WSA881X_DIGITAL_BASE + 0x0099)
 106 #define WSA881X_OTP_REG_26                      (WSA881X_DIGITAL_BASE + 0x009A)
 107 #define WSA881X_OTP_REG_27                      (WSA881X_DIGITAL_BASE + 0x009B)
 108 #define WSA881X_OTP_REG_28                      (WSA881X_DIGITAL_BASE + 0x009C)
 109 #define WSA881X_OTP_REG_29                      (WSA881X_DIGITAL_BASE + 0x009D)
 110 #define WSA881X_OTP_REG_30                      (WSA881X_DIGITAL_BASE + 0x009E)
 111 #define WSA881X_OTP_REG_31                      (WSA881X_DIGITAL_BASE + 0x009F)
 112 #define WSA881X_OTP_REG_63                      (WSA881X_DIGITAL_BASE + 0x00BF)
 113
 114 /* Analog Register address space */
 115 #define WSA881X_BIAS_REF_CTRL                   (WSA881X_ANALOG_BASE + 0x0000)
 116 #define WSA881X_BIAS_TEST                       (WSA881X_ANALOG_BASE + 0x0001)
 117 #define WSA881X_BIAS_BIAS                       (WSA881X_ANALOG_BASE + 0x0002)
 118 #define WSA881X_TEMP_OP                         (WSA881X_ANALOG_BASE + 0x0003)
 119 #define WSA881X_TEMP_IREF_CTRL                  (WSA881X_ANALOG_BASE + 0x0004)
 120 #define WSA881X_TEMP_ISENS_CTRL                 (WSA881X_ANALOG_BASE + 0x0005)
 121 #define WSA881X_TEMP_CLK_CTRL                   (WSA881X_ANALOG_BASE + 0x0006)
 122 #define WSA881X_TEMP_TEST                       (WSA881X_ANALOG_BASE + 0x0007)
 123 #define WSA881X_TEMP_BIAS                       (WSA881X_ANALOG_BASE + 0x0008)
 124 #define WSA881X_TEMP_ADC_CTRL                   (WSA881X_ANALOG_BASE + 0x0009)
 125 #define WSA881X_TEMP_DOUT_MSB                   (WSA881X_ANALOG_BASE + 0x000A)
 126 #define WSA881X_TEMP_DOUT_LSB                   (WSA881X_ANALOG_BASE + 0x000B)
 127 #define WSA881X_ADC_EN_MODU_V                   (WSA881X_ANALOG_BASE + 0x0010)
 128 #define WSA881X_ADC_EN_MODU_I                   (WSA881X_ANALOG_BASE + 0x0011)
 129 #define WSA881X_ADC_EN_DET_TEST_V               (WSA881X_ANALOG_BASE + 0x0012)
 130 #define WSA881X_ADC_EN_DET_TEST_I               (WSA881X_ANALOG_BASE + 0x0013)
 131 #define WSA881X_ADC_SEL_IBIAS                   (WSA881X_ANALOG_BASE + 0x0014)
 132 #define WSA881X_ADC_EN_SEL_IBAIS                (WSA881X_ANALOG_BASE + 0x0015)
 133 #define WSA881X_SPKR_DRV_EN                     (WSA881X_ANALOG_BASE + 0x001A)
 134 #define WSA881X_SPKR_DRV_GAIN                   (WSA881X_ANALOG_BASE + 0x001B)
 135 #define WSA881X_PA_GAIN_SEL_MASK                BIT(3)
 136 #define WSA881X_PA_GAIN_SEL_REG                 BIT(3)
 137 #define WSA881X_PA_GAIN_SEL_DRE                 0
 138 #define WSA881X_SPKR_PAG_GAIN_MASK              GENMASK(7, 4)
 139 #define WSA881X_SPKR_DAC_CTL                    (WSA881X_ANALOG_BASE + 0x001C)
 140 #define WSA881X_SPKR_DRV_DBG                    (WSA881X_ANALOG_BASE + 0x001D)
 141 #define WSA881X_SPKR_PWRSTG_DBG                 (WSA881X_ANALOG_BASE + 0x001E)
 142 #define WSA881X_SPKR_OCP_CTL                    (WSA881X_ANALOG_BASE + 0x001F)
 143 #define WSA881X_SPKR_OCP_MASK                   GENMASK(7, 6)
 144 #define WSA881X_SPKR_OCP_EN                     BIT(7)
 145 #define WSA881X_SPKR_OCP_HOLD                   BIT(6)
 146 #define WSA881X_SPKR_CLIP_CTL                   (WSA881X_ANALOG_BASE + 0x0020)
 147 #define WSA881X_SPKR_BBM_CTL                    (WSA881X_ANALOG_BASE + 0x0021)
 148 #define WSA881X_SPKR_MISC_CTL1                  (WSA881X_ANALOG_BASE + 0x0022)
 149 #define WSA881X_SPKR_MISC_CTL2                  (WSA881X_ANALOG_BASE + 0x0023)
 150 #define WSA881X_SPKR_BIAS_INT                   (WSA881X_ANALOG_BASE + 0x0024)
 151 #define WSA881X_SPKR_PA_INT                     (WSA881X_ANALOG_BASE + 0x0025)
 152 #define WSA881X_SPKR_BIAS_CAL                   (WSA881X_ANALOG_BASE + 0x0026)
 153 #define WSA881X_SPKR_BIAS_PSRR                  (WSA881X_ANALOG_BASE + 0x0027)
 154 #define WSA881X_SPKR_STATUS1                    (WSA881X_ANALOG_BASE + 0x0028)
 155 #define WSA881X_SPKR_STATUS2                    (WSA881X_ANALOG_BASE + 0x0029)
 156 #define WSA881X_BOOST_EN_CTL                    (WSA881X_ANALOG_BASE + 0x002A)
 157 #define WSA881X_BOOST_EN_MASK                   BIT(7)
 158 #define WSA881X_BOOST_EN                        BIT(7)
 159 #define WSA881X_BOOST_CURRENT_LIMIT             (WSA881X_ANALOG_BASE + 0x002B)
 160 #define WSA881X_BOOST_PS_CTL                    (WSA881X_ANALOG_BASE + 0x002C)
 161 #define WSA881X_BOOST_PRESET_OUT1               (WSA881X_ANALOG_BASE + 0x002D)
 162 #define WSA881X_BOOST_PRESET_OUT2               (WSA881X_ANALOG_BASE + 0x002E)
 163 #define WSA881X_BOOST_FORCE_OUT                 (WSA881X_ANALOG_BASE + 0x002F)
 164 #define WSA881X_BOOST_LDO_PROG                  (WSA881X_ANALOG_BASE + 0x0030)
 165 #define WSA881X_BOOST_SLOPE_COMP_ISENSE_FB      (WSA881X_ANALOG_BASE + 0x0031)
 166 #define WSA881X_BOOST_RON_CTL                   (WSA881X_ANALOG_BASE + 0x0032)
 167 #define WSA881X_BOOST_LOOP_STABILITY            (WSA881X_ANALOG_BASE + 0x0033)
 168 #define WSA881X_BOOST_ZX_CTL                    (WSA881X_ANALOG_BASE + 0x0034)
 169 #define WSA881X_BOOST_START_CTL                 (WSA881X_ANALOG_BASE + 0x0035)
 170 #define WSA881X_BOOST_MISC1_CTL                 (WSA881X_ANALOG_BASE + 0x0036)
 171 #define WSA881X_BOOST_MISC2_CTL                 (WSA881X_ANALOG_BASE + 0x0037)
 172 #define WSA881X_BOOST_MISC3_CTL                 (WSA881X_ANALOG_BASE + 0x0038)
 173 #define WSA881X_BOOST_ATEST_CTL                 (WSA881X_ANALOG_BASE + 0x0039)
 174 #define WSA881X_SPKR_PROT_FE_GAIN               (WSA881X_ANALOG_BASE + 0x003A)
 175 #define WSA881X_SPKR_PROT_FE_CM_LDO_SET         (WSA881X_ANALOG_BASE + 0x003B)
 176 #define WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1   (WSA881X_ANALOG_BASE + 0x003C)
 177 #define WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2   (WSA881X_ANALOG_BASE + 0x003D)
 178 #define WSA881X_SPKR_PROT_ATEST1                (WSA881X_ANALOG_BASE + 0x003E)
 179 #define WSA881X_SPKR_PROT_ATEST2                (WSA881X_ANALOG_BASE + 0x003F)
 180 #define WSA881X_SPKR_PROT_FE_VSENSE_VCM         (WSA881X_ANALOG_BASE + 0x0040)
 181 #define WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1   (WSA881X_ANALOG_BASE + 0x0041)
 182 #define WSA881X_BONGO_RESRV_REG1                (WSA881X_ANALOG_BASE + 0x0042)
 183 #define WSA881X_BONGO_RESRV_REG2                (WSA881X_ANALOG_BASE + 0x0043)
 184 #define WSA881X_SPKR_PROT_SAR                   (WSA881X_ANALOG_BASE + 0x0044)
 185 #define WSA881X_SPKR_STATUS3                    (WSA881X_ANALOG_BASE + 0x0045)
 186
 187 #define SWRS_SCP_FRAME_CTRL_BANK(m)             (0x60 + 0x10 * (m))
 188 #define SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(m)      (0xE0 + 0x10 * (m))
 189 #define SWR_SLV_MAX_REG_ADDR    0x390
 190 #define SWR_SLV_START_REG_ADDR  0x40
 191 #define SWR_SLV_MAX_BUF_LEN     20
 192 #define BYTES_PER_LINE          12
 193 #define SWR_SLV_RD_BUF_LEN      8
 194 #define SWR_SLV_WR_BUF_LEN      32
 195 #define SWR_SLV_MAX_DEVICES     2
 196 #define WSA881X_MAX_SWR_PORTS   4
 197 #define WSA881X_VERSION_ENTRY_SIZE 27
 198 #define WSA881X_OCP_CTL_TIMER_SEC 2
 199 #define WSA881X_OCP_CTL_TEMP_CELSIUS 25
 200 #define WSA881X_OCP_CTL_POLL_TIMER_SEC 60
 201
 202 #define WSA881X_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
 203 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 204         .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
 205                  SNDRV_CTL_ELEM_ACCESS_READWRITE,\
 206         .tlv.p = (tlv_array), \
 207         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
 208         .put = wsa881x_put_pa_gain, \
 209         .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
 210
 211 static struct reg_default wsa881x_defaults[] = {
 212         { WSA881X_CHIP_ID0, 0x00 },
 213         { WSA881X_CHIP_ID1, 0x00 },
 214         { WSA881X_CHIP_ID2, 0x00 },
 215         { WSA881X_CHIP_ID3, 0x02 },
 216         { WSA881X_BUS_ID, 0x00 },
 217         { WSA881X_CDC_RST_CTL, 0x00 },
 218         { WSA881X_CDC_TOP_CLK_CTL, 0x03 },
 219         { WSA881X_CDC_ANA_CLK_CTL, 0x00 },
 220         { WSA881X_CDC_DIG_CLK_CTL, 0x00 },
 221         { WSA881X_CLOCK_CONFIG, 0x00 },
 222         { WSA881X_ANA_CTL, 0x08 },
 223         { WSA881X_SWR_RESET_EN, 0x00 },
 224         { WSA881X_TEMP_DETECT_CTL, 0x01 },
 225         { WSA881X_TEMP_MSB, 0x00 },
 226         { WSA881X_TEMP_LSB, 0x00 },
 227         { WSA881X_TEMP_CONFIG0, 0x00 },
 228         { WSA881X_TEMP_CONFIG1, 0x00 },
 229         { WSA881X_CDC_CLIP_CTL, 0x03 },
 230         { WSA881X_SDM_PDM9_LSB, 0x00 },
 231         { WSA881X_SDM_PDM9_MSB, 0x00 },
 232         { WSA881X_CDC_RX_CTL, 0x7E },
 233         { WSA881X_DEM_BYPASS_DATA0, 0x00 },
 234         { WSA881X_DEM_BYPASS_DATA1, 0x00 },
 235         { WSA881X_DEM_BYPASS_DATA2, 0x00 },
 236         { WSA881X_DEM_BYPASS_DATA3, 0x00 },
 237         { WSA881X_OTP_CTRL0, 0x00 },
 238         { WSA881X_OTP_CTRL1, 0x00 },
 239         { WSA881X_HDRIVE_CTL_GROUP1, 0x00 },
 240         { WSA881X_INTR_MODE, 0x00 },
 241         { WSA881X_INTR_STATUS, 0x00 },
 242         { WSA881X_INTR_CLEAR, 0x00 },
 243         { WSA881X_INTR_LEVEL, 0x00 },
 244         { WSA881X_INTR_SET, 0x00 },
 245         { WSA881X_INTR_TEST, 0x00 },
 246         { WSA881X_PDM_TEST_MODE, 0x00 },
 247         { WSA881X_ATE_TEST_MODE, 0x00 },
 248         { WSA881X_PIN_CTL_MODE, 0x00 },
 249         { WSA881X_PIN_CTL_OE, 0x00 },
 250         { WSA881X_PIN_WDATA_IOPAD, 0x00 },
 251         { WSA881X_PIN_STATUS, 0x00 },
 252         { WSA881X_DIG_DEBUG_MODE, 0x00 },
 253         { WSA881X_DIG_DEBUG_SEL, 0x00 },
 254         { WSA881X_DIG_DEBUG_EN, 0x00 },
 255         { WSA881X_SWR_HM_TEST1, 0x08 },
 256         { WSA881X_SWR_HM_TEST2, 0x00 },
 257         { WSA881X_TEMP_DETECT_DBG_CTL, 0x00 },
 258         { WSA881X_TEMP_DEBUG_MSB, 0x00 },
 259         { WSA881X_TEMP_DEBUG_LSB, 0x00 },
 260         { WSA881X_SAMPLE_EDGE_SEL, 0x0C },
 261         { WSA881X_SPARE_0, 0x00 },
 262         { WSA881X_SPARE_1, 0x00 },
 263         { WSA881X_SPARE_2, 0x00 },
 264         { WSA881X_OTP_REG_0, 0x01 },
 265         { WSA881X_OTP_REG_1, 0xFF },
 266         { WSA881X_OTP_REG_2, 0xC0 },
 267         { WSA881X_OTP_REG_3, 0xFF },
 268         { WSA881X_OTP_REG_4, 0xC0 },
 269         { WSA881X_OTP_REG_5, 0xFF },
 270         { WSA881X_OTP_REG_6, 0xFF },
 271         { WSA881X_OTP_REG_7, 0xFF },
 272         { WSA881X_OTP_REG_8, 0xFF },
 273         { WSA881X_OTP_REG_9, 0xFF },
 274         { WSA881X_OTP_REG_10, 0xFF },
 275         { WSA881X_OTP_REG_11, 0xFF },
 276         { WSA881X_OTP_REG_12, 0xFF },
 277         { WSA881X_OTP_REG_13, 0xFF },
 278         { WSA881X_OTP_REG_14, 0xFF },
 279         { WSA881X_OTP_REG_15, 0xFF },
 280         { WSA881X_OTP_REG_16, 0xFF },
 281         { WSA881X_OTP_REG_17, 0xFF },
 282         { WSA881X_OTP_REG_18, 0xFF },
 283         { WSA881X_OTP_REG_19, 0xFF },
 284         { WSA881X_OTP_REG_20, 0xFF },
 285         { WSA881X_OTP_REG_21, 0xFF },
 286         { WSA881X_OTP_REG_22, 0xFF },
 287         { WSA881X_OTP_REG_23, 0xFF },
 288         { WSA881X_OTP_REG_24, 0x03 },
 289         { WSA881X_OTP_REG_25, 0x01 },
 290         { WSA881X_OTP_REG_26, 0x03 },
 291         { WSA881X_OTP_REG_27, 0x11 },
 292         { WSA881X_OTP_REG_63, 0x40 },
 293         /* WSA881x Analog registers */
 294         { WSA881X_BIAS_REF_CTRL, 0x6C },
 295         { WSA881X_BIAS_TEST, 0x16 },
 296         { WSA881X_BIAS_BIAS, 0xF0 },
 297         { WSA881X_TEMP_OP, 0x00 },
 298         { WSA881X_TEMP_IREF_CTRL, 0x56 },
 299         { WSA881X_TEMP_ISENS_CTRL, 0x47 },
 300         { WSA881X_TEMP_CLK_CTRL, 0x87 },
 301         { WSA881X_TEMP_TEST, 0x00 },
 302         { WSA881X_TEMP_BIAS, 0x51 },
 303         { WSA881X_TEMP_DOUT_MSB, 0x00 },
 304         { WSA881X_TEMP_DOUT_LSB, 0x00 },
 305         { WSA881X_ADC_EN_MODU_V, 0x00 },
 306         { WSA881X_ADC_EN_MODU_I, 0x00 },
 307         { WSA881X_ADC_EN_DET_TEST_V, 0x00 },
 308         { WSA881X_ADC_EN_DET_TEST_I, 0x00 },
 309         { WSA881X_ADC_EN_SEL_IBAIS, 0x10 },
 310         { WSA881X_SPKR_DRV_EN, 0x74 },
 311         { WSA881X_SPKR_DRV_DBG, 0x15 },
 312         { WSA881X_SPKR_PWRSTG_DBG, 0x00 },
 313         { WSA881X_SPKR_OCP_CTL, 0xD4 },
 314         { WSA881X_SPKR_CLIP_CTL, 0x90 },
 315         { WSA881X_SPKR_PA_INT, 0x54 },
 316         { WSA881X_SPKR_BIAS_CAL, 0xAC },
 317         { WSA881X_SPKR_STATUS1, 0x00 },
 318         { WSA881X_SPKR_STATUS2, 0x00 },
 319         { WSA881X_BOOST_EN_CTL, 0x18 },
 320         { WSA881X_BOOST_CURRENT_LIMIT, 0x7A },
 321         { WSA881X_BOOST_PRESET_OUT2, 0x70 },
 322         { WSA881X_BOOST_FORCE_OUT, 0x0E },
 323         { WSA881X_BOOST_LDO_PROG, 0x16 },
 324         { WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x71 },
 325         { WSA881X_BOOST_RON_CTL, 0x0F },
 326         { WSA881X_BOOST_ZX_CTL, 0x34 },
 327         { WSA881X_BOOST_START_CTL, 0x23 },
 328         { WSA881X_BOOST_MISC1_CTL, 0x80 },
 329         { WSA881X_BOOST_MISC2_CTL, 0x00 },
 330         { WSA881X_BOOST_MISC3_CTL, 0x00 },
 331         { WSA881X_BOOST_ATEST_CTL, 0x00 },
 332         { WSA881X_SPKR_PROT_FE_GAIN, 0x46 },
 333         { WSA881X_SPKR_PROT_FE_CM_LDO_SET, 0x3B },
 334         { WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1, 0x8D },
 335         { WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2, 0x8D },
 336         { WSA881X_SPKR_PROT_ATEST1, 0x01 },
 337         { WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x8D },
 338         { WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1, 0x4D },
 339         { WSA881X_SPKR_PROT_SAR, 0x00 },
 340         { WSA881X_SPKR_STATUS3, 0x00 },
 341 };
 342
 343 static const struct reg_sequence wsa881x_pre_pmu_pa_2_0[] = {
 344         { WSA881X_SPKR_DRV_GAIN, 0x41, 0 },
 345         { WSA881X_SPKR_MISC_CTL1, 0x87, 0 },
 346 };
 347
 348 static const struct reg_sequence wsa881x_vi_txfe_en_2_0[] = {
 349         { WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x85, 0 },
 350         { WSA881X_SPKR_PROT_ATEST2, 0x0A, 0 },
 351         { WSA881X_SPKR_PROT_FE_GAIN, 0x47, 0 },
 352 };
 353
 354 /* Default register reset values for WSA881x rev 2.0 */
 355 static struct reg_sequence wsa881x_rev_2_0[] = {
 356         { WSA881X_RESET_CTL, 0x00, 0x00 },
 357         { WSA881X_TADC_VALUE_CTL, 0x01, 0x00 },
 358         { WSA881X_INTR_MASK, 0x1B, 0x00 },
 359         { WSA881X_IOPAD_CTL, 0x00, 0x00 },
 360         { WSA881X_OTP_REG_28, 0x3F, 0x00 },
 361         { WSA881X_OTP_REG_29, 0x3F, 0x00 },
 362         { WSA881X_OTP_REG_30, 0x01, 0x00 },
 363         { WSA881X_OTP_REG_31, 0x01, 0x00 },
 364         { WSA881X_TEMP_ADC_CTRL, 0x03, 0x00 },
 365         { WSA881X_ADC_SEL_IBIAS, 0x45, 0x00 },
 366         { WSA881X_SPKR_DRV_GAIN, 0xC1, 0x00 },
 367         { WSA881X_SPKR_DAC_CTL, 0x42, 0x00 },
 368         { WSA881X_SPKR_BBM_CTL, 0x02, 0x00 },
 369         { WSA881X_SPKR_MISC_CTL1, 0x40, 0x00 },
 370         { WSA881X_SPKR_MISC_CTL2, 0x07, 0x00 },
 371         { WSA881X_SPKR_BIAS_INT, 0x5F, 0x00 },
 372         { WSA881X_SPKR_BIAS_PSRR, 0x44, 0x00 },
 373         { WSA881X_BOOST_PS_CTL, 0xA0, 0x00 },
 374         { WSA881X_BOOST_PRESET_OUT1, 0xB7, 0x00 },
 375         { WSA881X_BOOST_LOOP_STABILITY, 0x8D, 0x00 },
 376         { WSA881X_SPKR_PROT_ATEST2, 0x02, 0x00 },
 377         { WSA881X_BONGO_RESRV_REG1, 0x5E, 0x00 },
 378         { WSA881X_BONGO_RESRV_REG2, 0x07, 0x00 },
 379 };
 380
 381 enum wsa_port_ids {
 382         WSA881X_PORT_DAC,
 383         WSA881X_PORT_COMP,
 384         WSA881X_PORT_BOOST,
 385         WSA881X_PORT_VISENSE,
 386 };
 387
 388 /* 4 ports */
 389 static struct sdw_dpn_prop wsa_sink_dpn_prop[WSA881X_MAX_SWR_PORTS] = {
 390         {
 391                 /* DAC */
 392                 .num = 1,
 393                 .type = SDW_DPN_SIMPLE,
 394                 .min_ch = 1,
 395                 .max_ch = 1,
 396                 .simple_ch_prep_sm = true,
 397         }, {
 398                 /* COMP */
 399                 .num = 2,
 400                 .type = SDW_DPN_SIMPLE,
 401                 .min_ch = 1,
 402                 .max_ch = 1,
 403                 .simple_ch_prep_sm = true,
 404         }, {
 405                 /* BOOST */
 406                 .num = 3,
 407                 .type = SDW_DPN_SIMPLE,
 408                 .min_ch = 1,
 409                 .max_ch = 1,
 410                 .simple_ch_prep_sm = true,
 411         }, {
 412                 /* VISENSE */
 413                 .num = 4,
 414                 .type = SDW_DPN_SIMPLE,
 415                 .min_ch = 1,
 416                 .max_ch = 1,
 417                 .simple_ch_prep_sm = true,
 418         }
 419 };
 420
 421 static struct sdw_port_config wsa881x_pconfig[WSA881X_MAX_SWR_PORTS] = {
 422         {
 423                 .num = 1,
 424                 .ch_mask = 0x1,
 425         }, {
 426                 .num = 2,
 427                 .ch_mask = 0xf,
 428         }, {
 429                 .num = 3,
 430                 .ch_mask = 0x3,
 431         }, {    /* IV feedback */
 432                 .num = 4,
 433                 .ch_mask = 0x3,
 434         },
 435 };
 436
 437 static bool wsa881x_readable_register(struct device *dev, unsigned int reg)
 438 {
 439         switch (reg) {
 440         case WSA881X_CHIP_ID0:
 441         case WSA881X_CHIP_ID1:
 442         case WSA881X_CHIP_ID2:
 443         case WSA881X_CHIP_ID3:
 444         case WSA881X_BUS_ID:
 445         case WSA881X_CDC_RST_CTL:
 446         case WSA881X_CDC_TOP_CLK_CTL:
 447         case WSA881X_CDC_ANA_CLK_CTL:
 448         case WSA881X_CDC_DIG_CLK_CTL:
 449         case WSA881X_CLOCK_CONFIG:
 450         case WSA881X_ANA_CTL:
 451         case WSA881X_SWR_RESET_EN:
 452         case WSA881X_RESET_CTL:
 453         case WSA881X_TADC_VALUE_CTL:
 454         case WSA881X_TEMP_DETECT_CTL:
 455         case WSA881X_TEMP_MSB:
 456         case WSA881X_TEMP_LSB:
 457         case WSA881X_TEMP_CONFIG0:
 458         case WSA881X_TEMP_CONFIG1:
 459         case WSA881X_CDC_CLIP_CTL:
 460         case WSA881X_SDM_PDM9_LSB:
 461         case WSA881X_SDM_PDM9_MSB:
 462         case WSA881X_CDC_RX_CTL:
 463         case WSA881X_DEM_BYPASS_DATA0:
 464         case WSA881X_DEM_BYPASS_DATA1:
 465         case WSA881X_DEM_BYPASS_DATA2:
 466         case WSA881X_DEM_BYPASS_DATA3:
 467         case WSA881X_OTP_CTRL0:
 468         case WSA881X_OTP_CTRL1:
 469         case WSA881X_HDRIVE_CTL_GROUP1:
 470         case WSA881X_INTR_MODE:
 471         case WSA881X_INTR_MASK:
 472         case WSA881X_INTR_STATUS:
 473         case WSA881X_INTR_CLEAR:
 474         case WSA881X_INTR_LEVEL:
 475         case WSA881X_INTR_SET:
 476         case WSA881X_INTR_TEST:
 477         case WSA881X_PDM_TEST_MODE:
 478         case WSA881X_ATE_TEST_MODE:
 479         case WSA881X_PIN_CTL_MODE:
 480         case WSA881X_PIN_CTL_OE:
 481         case WSA881X_PIN_WDATA_IOPAD:
 482         case WSA881X_PIN_STATUS:
 483         case WSA881X_DIG_DEBUG_MODE:
 484         case WSA881X_DIG_DEBUG_SEL:
 485         case WSA881X_DIG_DEBUG_EN:
 486         case WSA881X_SWR_HM_TEST1:
 487         case WSA881X_SWR_HM_TEST2:
 488         case WSA881X_TEMP_DETECT_DBG_CTL:
 489         case WSA881X_TEMP_DEBUG_MSB:
 490         case WSA881X_TEMP_DEBUG_LSB:
 491         case WSA881X_SAMPLE_EDGE_SEL:
 492         case WSA881X_IOPAD_CTL:
 493         case WSA881X_SPARE_0:
 494         case WSA881X_SPARE_1:
 495         case WSA881X_SPARE_2:
 496         case WSA881X_OTP_REG_0:
 497         case WSA881X_OTP_REG_1:
 498         case WSA881X_OTP_REG_2:
 499         case WSA881X_OTP_REG_3:
 500         case WSA881X_OTP_REG_4:
 501         case WSA881X_OTP_REG_5:
 502         case WSA881X_OTP_REG_6:
 503         case WSA881X_OTP_REG_7:
 504         case WSA881X_OTP_REG_8:
 505         case WSA881X_OTP_REG_9:
 506         case WSA881X_OTP_REG_10:
 507         case WSA881X_OTP_REG_11:
 508         case WSA881X_OTP_REG_12:
 509         case WSA881X_OTP_REG_13:
 510         case WSA881X_OTP_REG_14:
 511         case WSA881X_OTP_REG_15:
 512         case WSA881X_OTP_REG_16:
 513         case WSA881X_OTP_REG_17:
 514         case WSA881X_OTP_REG_18:
 515         case WSA881X_OTP_REG_19:
 516         case WSA881X_OTP_REG_20:
 517         case WSA881X_OTP_REG_21:
 518         case WSA881X_OTP_REG_22:
 519         case WSA881X_OTP_REG_23:
 520         case WSA881X_OTP_REG_24:
 521         case WSA881X_OTP_REG_25:
 522         case WSA881X_OTP_REG_26:
 523         case WSA881X_OTP_REG_27:
 524         case WSA881X_OTP_REG_28:
 525         case WSA881X_OTP_REG_29:
 526         case WSA881X_OTP_REG_30:
 527         case WSA881X_OTP_REG_31:
 528         case WSA881X_OTP_REG_63:
 529         case WSA881X_BIAS_REF_CTRL:
 530         case WSA881X_BIAS_TEST:
 531         case WSA881X_BIAS_BIAS:
 532         case WSA881X_TEMP_OP:
 533         case WSA881X_TEMP_IREF_CTRL:
 534         case WSA881X_TEMP_ISENS_CTRL:
 535         case WSA881X_TEMP_CLK_CTRL:
 536         case WSA881X_TEMP_TEST:
 537         case WSA881X_TEMP_BIAS:
 538         case WSA881X_TEMP_ADC_CTRL:
 539         case WSA881X_TEMP_DOUT_MSB:
 540         case WSA881X_TEMP_DOUT_LSB:
 541         case WSA881X_ADC_EN_MODU_V:
 542         case WSA881X_ADC_EN_MODU_I:
 543         case WSA881X_ADC_EN_DET_TEST_V:
 544         case WSA881X_ADC_EN_DET_TEST_I:
 545         case WSA881X_ADC_SEL_IBIAS:
 546         case WSA881X_ADC_EN_SEL_IBAIS:
 547         case WSA881X_SPKR_DRV_EN:
 548         case WSA881X_SPKR_DRV_GAIN:
 549         case WSA881X_SPKR_DAC_CTL:
 550         case WSA881X_SPKR_DRV_DBG:
 551         case WSA881X_SPKR_PWRSTG_DBG:
 552         case WSA881X_SPKR_OCP_CTL:
 553         case WSA881X_SPKR_CLIP_CTL:
 554         case WSA881X_SPKR_BBM_CTL:
 555         case WSA881X_SPKR_MISC_CTL1:
 556         case WSA881X_SPKR_MISC_CTL2:
 557         case WSA881X_SPKR_BIAS_INT:
 558         case WSA881X_SPKR_PA_INT:
 559         case WSA881X_SPKR_BIAS_CAL:
 560         case WSA881X_SPKR_BIAS_PSRR:
 561         case WSA881X_SPKR_STATUS1:
 562         case WSA881X_SPKR_STATUS2:
 563         case WSA881X_BOOST_EN_CTL:
 564         case WSA881X_BOOST_CURRENT_LIMIT:
 565         case WSA881X_BOOST_PS_CTL:
 566         case WSA881X_BOOST_PRESET_OUT1:
 567         case WSA881X_BOOST_PRESET_OUT2:
 568         case WSA881X_BOOST_FORCE_OUT:
 569         case WSA881X_BOOST_LDO_PROG:
 570         case WSA881X_BOOST_SLOPE_COMP_ISENSE_FB:
 571         case WSA881X_BOOST_RON_CTL:
 572         case WSA881X_BOOST_LOOP_STABILITY:
 573         case WSA881X_BOOST_ZX_CTL:
 574         case WSA881X_BOOST_START_CTL:
 575         case WSA881X_BOOST_MISC1_CTL:
 576         case WSA881X_BOOST_MISC2_CTL:
 577         case WSA881X_BOOST_MISC3_CTL:
 578         case WSA881X_BOOST_ATEST_CTL:
 579         case WSA881X_SPKR_PROT_FE_GAIN:
 580         case WSA881X_SPKR_PROT_FE_CM_LDO_SET:
 581         case WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1:
 582         case WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2:
 583         case WSA881X_SPKR_PROT_ATEST1:
 584         case WSA881X_SPKR_PROT_ATEST2:
 585         case WSA881X_SPKR_PROT_FE_VSENSE_VCM:
 586         case WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1:
 587         case WSA881X_BONGO_RESRV_REG1:
 588         case WSA881X_BONGO_RESRV_REG2:
 589         case WSA881X_SPKR_PROT_SAR:
 590         case WSA881X_SPKR_STATUS3:
 591                 return true;
 592         default:
 593                 return false;
 594         }
 595 }
 596
 597 static bool wsa881x_volatile_register(struct device *dev, unsigned int reg)
 598 {
 599         switch (reg) {
 600         case WSA881X_CHIP_ID0:
 601         case WSA881X_CHIP_ID1:
 602         case WSA881X_CHIP_ID2:
 603         case WSA881X_CHIP_ID3:
 604         case WSA881X_BUS_ID:
 605         case WSA881X_TEMP_MSB:
 606         case WSA881X_TEMP_LSB:
 607         case WSA881X_SDM_PDM9_LSB:
 608         case WSA881X_SDM_PDM9_MSB:
 609         case WSA881X_OTP_CTRL1:
 610         case WSA881X_INTR_STATUS:
 611         case WSA881X_ATE_TEST_MODE:
 612         case WSA881X_PIN_STATUS:
 613         case WSA881X_SWR_HM_TEST2:
 614         case WSA881X_SPKR_STATUS1:
 615         case WSA881X_SPKR_STATUS2:
 616         case WSA881X_SPKR_STATUS3:
 617         case WSA881X_OTP_REG_0:
 618         case WSA881X_OTP_REG_1:
 619         case WSA881X_OTP_REG_2:
 620         case WSA881X_OTP_REG_3:
 621         case WSA881X_OTP_REG_4:
 622         case WSA881X_OTP_REG_5:
 623         case WSA881X_OTP_REG_31:
 624         case WSA881X_TEMP_DOUT_MSB:
 625         case WSA881X_TEMP_DOUT_LSB:
 626         case WSA881X_TEMP_OP:
 627         case WSA881X_SPKR_PROT_SAR:
 628                 return true;
 629         default:
 630                 return false;
 631         }
 632 }
 633
 634 static struct regmap_config wsa881x_regmap_config = {
 635         .reg_bits = 32,
 636         .val_bits = 8,
 637         .cache_type = REGCACHE_RBTREE,
 638         .reg_defaults = wsa881x_defaults,
 639         .num_reg_defaults = ARRAY_SIZE(wsa881x_defaults),
 640         .volatile_reg = wsa881x_volatile_register,
 641         .readable_reg = wsa881x_readable_register,
 642         .reg_format_endian = REGMAP_ENDIAN_NATIVE,
 643         .val_format_endian = REGMAP_ENDIAN_NATIVE,
 644         .can_multi_write = true,
 645 };
 646
 647 enum {
 648         G_18DB = 0,
 649         G_16P5DB,
 650         G_15DB,
 651         G_13P5DB,
 652         G_12DB,
 653         G_10P5DB,
 654         G_9DB,
 655         G_7P5DB,
 656         G_6DB,
 657         G_4P5DB,
 658         G_3DB,
 659         G_1P5DB,
 660         G_0DB,
 661 };
 662
 663 /*
 664  * Private data Structure for wsa881x. All parameters related to
 665  * WSA881X codec needs to be defined here.
 666  */
 667 struct wsa881x_priv {
 668         struct regmap *regmap;
 669         struct device *dev;
 670         struct sdw_slave *slave;
 671         struct sdw_stream_config sconfig;
 672         struct sdw_stream_runtime *sruntime;
 673         struct sdw_port_config port_config[WSA881X_MAX_SWR_PORTS];
 674         struct gpio_desc *sd_n;
 675         int version;
 676         int active_ports;
 677         bool port_prepared[WSA881X_MAX_SWR_PORTS];
 678         bool port_enable[WSA881X_MAX_SWR_PORTS];
 679         bool stream_prepared;
 680 };
 681
 682 static void wsa881x_init(struct wsa881x_priv *wsa881x)
 683 {
 684         struct regmap *rm = wsa881x->regmap;
 685         unsigned int val = 0;
 686
 687         regmap_read(rm, WSA881X_CHIP_ID1, &wsa881x->version);
 688         regmap_register_patch(wsa881x->regmap, wsa881x_rev_2_0,
 689                               ARRAY_SIZE(wsa881x_rev_2_0));
 690
 691         /* Enable software reset output from soundwire slave */
 692         regmap_update_bits(rm, WSA881X_SWR_RESET_EN, 0x07, 0x07);
 693
 694         /* Bring out of analog reset */
 695         regmap_update_bits(rm, WSA881X_CDC_RST_CTL, 0x02, 0x02);
 696
 697         /* Bring out of digital reset */
 698         regmap_update_bits(rm, WSA881X_CDC_RST_CTL, 0x01, 0x01);
 699         regmap_update_bits(rm, WSA881X_CLOCK_CONFIG, 0x10, 0x10);
 700         regmap_update_bits(rm, WSA881X_SPKR_OCP_CTL, 0x02, 0x02);
 701         regmap_update_bits(rm, WSA881X_SPKR_MISC_CTL1, 0xC0, 0x80);
 702         regmap_update_bits(rm, WSA881X_SPKR_MISC_CTL1, 0x06, 0x06);
 703         regmap_update_bits(rm, WSA881X_SPKR_BIAS_INT, 0xFF, 0x00);
 704         regmap_update_bits(rm, WSA881X_SPKR_PA_INT, 0xF0, 0x40);
 705         regmap_update_bits(rm, WSA881X_SPKR_PA_INT, 0x0E, 0x0E);
 706         regmap_update_bits(rm, WSA881X_BOOST_LOOP_STABILITY, 0x03, 0x03);
 707         regmap_update_bits(rm, WSA881X_BOOST_MISC2_CTL, 0xFF, 0x14);
 708         regmap_update_bits(rm, WSA881X_BOOST_START_CTL, 0x80, 0x80);
 709         regmap_update_bits(rm, WSA881X_BOOST_START_CTL, 0x03, 0x00);
 710         regmap_update_bits(rm, WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x0C, 0x04);
 711         regmap_update_bits(rm, WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x03, 0x00);
 712
 713         regmap_read(rm, WSA881X_OTP_REG_0, &val);
 714         if (val)
 715                 regmap_update_bits(rm, WSA881X_BOOST_PRESET_OUT1, 0xF0, 0x70);
 716
 717         regmap_update_bits(rm, WSA881X_BOOST_PRESET_OUT2, 0xF0, 0x30);
 718         regmap_update_bits(rm, WSA881X_SPKR_DRV_EN, 0x08, 0x08);
 719         regmap_update_bits(rm, WSA881X_BOOST_CURRENT_LIMIT, 0x0F, 0x08);
 720         regmap_update_bits(rm, WSA881X_SPKR_OCP_CTL, 0x30, 0x30);
 721         regmap_update_bits(rm, WSA881X_SPKR_OCP_CTL, 0x0C, 0x00);
 722         regmap_update_bits(rm, WSA881X_OTP_REG_28, 0x3F, 0x3A);
 723         regmap_update_bits(rm, WSA881X_BONGO_RESRV_REG1, 0xFF, 0xB2);
 724         regmap_update_bits(rm, WSA881X_BONGO_RESRV_REG2, 0xFF, 0x05);
 725 }
 726
 727 static int wsa881x_component_probe(struct snd_soc_component *comp)
 728 {
 729         struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);
 730
 731         snd_soc_component_init_regmap(comp, wsa881x->regmap);
 732
 733         return 0;
 734 }
 735
 736 static int wsa881x_put_pa_gain(struct snd_kcontrol *kc,
 737                                struct snd_ctl_elem_value *ucontrol)
 738 {
 739         struct snd_soc_component *comp = snd_soc_kcontrol_component(kc);
 740         struct soc_mixer_control *mc =
 741                         (struct soc_mixer_control *)kc->private_value;
 742         int max = mc->max;
 743         unsigned int mask = (1 << fls(max)) - 1;
 744         int val, ret, min_gain, max_gain;
 745
 746         max_gain = (max - ucontrol->value.integer.value[0]) & mask;
 747         /*
 748          * Gain has to set incrementally in 4 steps
 749          * as per HW sequence
 750          */
 751         if (max_gain > G_4P5DB)
 752                 min_gain = G_0DB;
 753         else
 754                 min_gain = max_gain + 3;
 755         /*
 756          * 1ms delay is needed before change in gain
 757          * as per HW requirement.
 758          */
 759         usleep_range(1000, 1010);
 760
 761         for (val = min_gain; max_gain <= val; val--) {
 762                 ret = snd_soc_component_update_bits(comp,
 763                               WSA881X_SPKR_DRV_GAIN,
 764                               WSA881X_SPKR_PAG_GAIN_MASK,
 765                               val << 4);
 766                 if (ret < 0)
 767                         dev_err(comp->dev, "Failed to change PA gain");
 768
 769                 usleep_range(1000, 1010);
 770         }
 771         return 0;
 772 }
 773
 774 static int wsa881x_get_port(struct snd_kcontrol *kcontrol,
 775                             struct snd_ctl_elem_value *ucontrol)
 776 {
 777         struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
 778         struct wsa881x_priv *data = snd_soc_component_get_drvdata(comp);
 779         struct soc_mixer_control *mixer =
 780                 (struct soc_mixer_control *)kcontrol->private_value;
 781         int portidx = mixer->reg;
 782
 783         ucontrol->value.integer.value[0] = data->port_enable[portidx];
 784
 785
 786         return 0;
 787 }
 788
 789 static int wsa881x_boost_ctrl(struct snd_soc_component *comp, bool enable)
 790 {
 791         if (enable)
 792                 snd_soc_component_update_bits(comp, WSA881X_BOOST_EN_CTL,
 793                                               WSA881X_BOOST_EN_MASK,
 794                                               WSA881X_BOOST_EN);
 795         else
 796                 snd_soc_component_update_bits(comp, WSA881X_BOOST_EN_CTL,
 797                                               WSA881X_BOOST_EN_MASK, 0);
 798         /*
 799          * 1.5ms sleep is needed after boost enable/disable as per
 800          * HW requirement
 801          */
 802         usleep_range(1500, 1510);
 803         return 0;
 804 }
 805
 806 static int wsa881x_set_port(struct snd_kcontrol *kcontrol,
 807                             struct snd_ctl_elem_value *ucontrol)
 808 {
 809         struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
 810         struct wsa881x_priv *data = snd_soc_component_get_drvdata(comp);
 811         struct soc_mixer_control *mixer =
 812                 (struct soc_mixer_control *)kcontrol->private_value;
 813         int portidx = mixer->reg;
 814
 815         if (ucontrol->value.integer.value[0])
 816                 data->port_enable[portidx] = true;
 817         else
 818                 data->port_enable[portidx] = false;
 819
 820         if (portidx == WSA881X_PORT_BOOST) /* Boost Switch */
 821                 wsa881x_boost_ctrl(comp, data->port_enable[portidx]);
 822
 823         return 0;
 824 }
 825
 826 static const char * const smart_boost_lvl_text[] = {
 827         "6.625 V", "6.750 V", "6.875 V", "7.000 V",
 828         "7.125 V", "7.250 V", "7.375 V", "7.500 V",
 829         "7.625 V", "7.750 V", "7.875 V", "8.000 V",
 830         "8.125 V", "8.250 V", "8.375 V", "8.500 V"
 831 };
 832
 833 static const struct soc_enum smart_boost_lvl_enum =
 834         SOC_ENUM_SINGLE(WSA881X_BOOST_PRESET_OUT1, 0,
 835                         ARRAY_SIZE(smart_boost_lvl_text),
 836                         smart_boost_lvl_text);
 837
 838 static const DECLARE_TLV_DB_SCALE(pa_gain, 0, 150, 0);
 839
 840 static const struct snd_kcontrol_new wsa881x_snd_controls[] = {
 841         SOC_ENUM("Smart Boost Level", smart_boost_lvl_enum),
 842         WSA881X_PA_GAIN_TLV("PA Volume", WSA881X_SPKR_DRV_GAIN,
 843                             4, 0xC, 1, pa_gain),
 844         SOC_SINGLE_EXT("DAC Switch", WSA881X_PORT_DAC, 0, 1, 0,
 845                        wsa881x_get_port, wsa881x_set_port),
 846         SOC_SINGLE_EXT("COMP Switch", WSA881X_PORT_COMP, 0, 1, 0,
 847                        wsa881x_get_port, wsa881x_set_port),
 848         SOC_SINGLE_EXT("BOOST Switch", WSA881X_PORT_BOOST, 0, 1, 0,
 849                        wsa881x_get_port, wsa881x_set_port),
 850         SOC_SINGLE_EXT("VISENSE Switch", WSA881X_PORT_VISENSE, 0, 1, 0,
 851                        wsa881x_get_port, wsa881x_set_port),
 852 };
 853
 854 static const struct snd_soc_dapm_route wsa881x_audio_map[] = {
 855         { "RDAC", NULL, "IN" },
 856         { "RDAC", NULL, "DCLK" },
 857         { "RDAC", NULL, "ACLK" },
 858         { "RDAC", NULL, "Bandgap" },
 859         { "SPKR PGA", NULL, "RDAC" },
 860         { "SPKR", NULL, "SPKR PGA" },
 861 };
 862
 863 static int wsa881x_visense_txfe_ctrl(struct snd_soc_component *comp,
 864                                      bool enable)
 865 {
 866         struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);
 867
 868         if (enable) {
 869                 regmap_multi_reg_write(wsa881x->regmap, wsa881x_vi_txfe_en_2_0,
 870                                        ARRAY_SIZE(wsa881x_vi_txfe_en_2_0));
 871         } else {
 872                 snd_soc_component_update_bits(comp,
 873                                               WSA881X_SPKR_PROT_FE_VSENSE_VCM,
 874                                               0x08, 0x08);
 875                 /*
 876                  * 200us sleep is needed after visense txfe disable as per
 877                  * HW requirement.
 878                  */
 879                 usleep_range(200, 210);
 880                 snd_soc_component_update_bits(comp, WSA881X_SPKR_PROT_FE_GAIN,
 881                                               0x01, 0x00);
 882         }
 883         return 0;
 884 }
 885
 886 static int wsa881x_visense_adc_ctrl(struct snd_soc_component *comp,
 887                                     bool enable)
 888 {
 889         snd_soc_component_update_bits(comp, WSA881X_ADC_EN_MODU_V, BIT(7),
 890                                       (enable << 7));
 891         snd_soc_component_update_bits(comp, WSA881X_ADC_EN_MODU_I, BIT(7),
 892                                       (enable << 7));
 893         return 0;
 894 }
 895
 896 static int wsa881x_spkr_pa_event(struct snd_soc_dapm_widget *w,
 897                                  struct snd_kcontrol *kcontrol, int event)
 898 {
 899         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
 900         struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);
 901
 902         switch (event) {
 903         case SND_SOC_DAPM_PRE_PMU:
 904                 snd_soc_component_update_bits(comp, WSA881X_SPKR_OCP_CTL,
 905                                               WSA881X_SPKR_OCP_MASK,
 906                                               WSA881X_SPKR_OCP_EN);
 907                 regmap_multi_reg_write(wsa881x->regmap, wsa881x_pre_pmu_pa_2_0,
 908                                        ARRAY_SIZE(wsa881x_pre_pmu_pa_2_0));
 909
 910                 snd_soc_component_update_bits(comp, WSA881X_SPKR_DRV_GAIN,
 911                                               WSA881X_PA_GAIN_SEL_MASK,
 912                                               WSA881X_PA_GAIN_SEL_REG);
 913                 break;
 914         case SND_SOC_DAPM_POST_PMU:
 915                 if (wsa881x->port_prepared[WSA881X_PORT_VISENSE]) {
 916                         wsa881x_visense_txfe_ctrl(comp, true);
 917                         snd_soc_component_update_bits(comp,
 918                                                       WSA881X_ADC_EN_SEL_IBAIS,
 919                                                       0x07, 0x01);
 920                         wsa881x_visense_adc_ctrl(comp, true);
 921                 }
 922
 923                 break;
 924         case SND_SOC_DAPM_POST_PMD:
 925                 if (wsa881x->port_prepared[WSA881X_PORT_VISENSE]) {
 926                         wsa881x_visense_adc_ctrl(comp, false);
 927                         wsa881x_visense_txfe_ctrl(comp, false);
 928                 }
 929
 930                 snd_soc_component_update_bits(comp, WSA881X_SPKR_OCP_CTL,
 931                                               WSA881X_SPKR_OCP_MASK,
 932                                               WSA881X_SPKR_OCP_EN |
 933                                               WSA881X_SPKR_OCP_HOLD);
 934                 break;
 935         }
 936         return 0;
 937 }
 938
 939 static const struct snd_soc_dapm_widget wsa881x_dapm_widgets[] = {
 940         SND_SOC_DAPM_INPUT("IN"),
 941         SND_SOC_DAPM_DAC_E("RDAC", NULL, WSA881X_SPKR_DAC_CTL, 7, 0,
 942                            NULL,
 943                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 944         SND_SOC_DAPM_PGA_E("SPKR PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
 945                            wsa881x_spkr_pa_event, SND_SOC_DAPM_PRE_PMU |
 946                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 947         SND_SOC_DAPM_SUPPLY("DCLK", WSA881X_CDC_DIG_CLK_CTL, 0, 0, NULL,
 948                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 949         SND_SOC_DAPM_SUPPLY("ACLK", WSA881X_CDC_ANA_CLK_CTL, 0, 0, NULL,
 950                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 951         SND_SOC_DAPM_SUPPLY("Bandgap", WSA881X_TEMP_OP, 3, 0,
 952                             NULL,
 953                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 954         SND_SOC_DAPM_OUTPUT("SPKR"),
 955 };
 956
 957 static int wsa881x_prepare(struct snd_pcm_substream *substream,
 958                            struct snd_soc_dai *dai)
 959 {
 960         struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);
 961         int ret;
 962
 963         if (wsa881x->stream_prepared) {
 964                 sdw_disable_stream(wsa881x->sruntime);
 965                 sdw_deprepare_stream(wsa881x->sruntime);
 966                 wsa881x->stream_prepared = false;
 967         }
 968
 969
 970         ret = sdw_prepare_stream(wsa881x->sruntime);
 971         if (ret)
 972                 return ret;
 973
 974         /**
 975          * NOTE: there is a strict hw requirement about the ordering of port
 976          * enables and actual PA enable. PA enable should only happen after
 977          * soundwire ports are enabled if not DC on the line is accumulated
 978          * resulting in Click/Pop Noise
 979          * PA enable/mute are handled as part of DAPM and digital mute.
 980          */
 981
 982         ret = sdw_enable_stream(wsa881x->sruntime);
 983         if (ret) {
 984                 sdw_deprepare_stream(wsa881x->sruntime);
 985                 return ret;
 986         }
 987         wsa881x->stream_prepared = true;
 988
 989         return ret;
 990 }
 991
 992 static int wsa881x_hw_params(struct snd_pcm_substream *substream,
 993                              struct snd_pcm_hw_params *params,
 994                              struct snd_soc_dai *dai)
 995 {
 996         struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);
 997         int i;
 998
 999         wsa881x->active_ports = 0;
1000         for (i = 0; i < WSA881X_MAX_SWR_PORTS; i++) {
1001                 if (!wsa881x->port_enable[i])
1002                         continue;
1003
1004                 wsa881x->port_config[wsa881x->active_ports] =
1005                                                         wsa881x_pconfig[i];
1006                 wsa881x->active_ports++;
1007         }
1008
1009         return sdw_stream_add_slave(wsa881x->slave, &wsa881x->sconfig,
1010                                     wsa881x->port_config, wsa881x->active_ports,
1011                                     wsa881x->sruntime);
1012 }
1013
1014 static int wsa881x_hw_free(struct snd_pcm_substream *substream,
1015                            struct snd_soc_dai *dai)
1016 {
1017         struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);
1018
1019         if (wsa881x->stream_prepared) {
1020                 sdw_disable_stream(wsa881x->sruntime);
1021                 sdw_deprepare_stream(wsa881x->sruntime);
1022                 sdw_stream_remove_slave(wsa881x->slave, wsa881x->sruntime);
1023                 wsa881x->stream_prepared = false;
1024         }
1025
1026         return 0;
1027 }
1028
1029 static int wsa881x_set_sdw_stream(struct snd_soc_dai *dai,
1030                                   void *stream, int direction)
1031 {
1032         struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);
1033
1034         wsa881x->sruntime = stream;
1035
1036         return 0;
1037 }
1038
1039 static int wsa881x_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
1040 {
1041         struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);
1042
1043         if (mute)
1044                 regmap_update_bits(wsa881x->regmap, WSA881X_SPKR_DRV_EN, 0x80,
1045                                    0x00);
1046         else
1047                 regmap_update_bits(wsa881x->regmap, WSA881X_SPKR_DRV_EN, 0x80,
1048                                    0x80);
1049
1050         return 0;
1051 }
1052
1053 static struct snd_soc_dai_ops wsa881x_dai_ops = {
1054         .hw_params = wsa881x_hw_params,
1055         .prepare = wsa881x_prepare,
1056         .hw_free = wsa881x_hw_free,
1057         .mute_stream = wsa881x_digital_mute,
1058         .set_sdw_stream = wsa881x_set_sdw_stream,
1059 };
1060
1061 static struct snd_soc_dai_driver wsa881x_dais[] = {
1062         {
1063                 .name = "SPKR",
1064                 .id = 0,
1065                 .playback = {
1066                         .stream_name = "SPKR Playback",
1067                         .rate_max = 48000,
1068                         .rate_min = 48000,
1069                         .channels_min = 1,
1070                         .channels_max = 1,
1071                 },
1072                 .ops = &wsa881x_dai_ops,
1073         },
1074 };
1075
1076 static const struct snd_soc_component_driver wsa881x_component_drv = {
1077         .name = "WSA881x",
1078         .probe = wsa881x_component_probe,
1079         .controls = wsa881x_snd_controls,
1080         .num_controls = ARRAY_SIZE(wsa881x_snd_controls),
1081         .dapm_widgets = wsa881x_dapm_widgets,
1082         .num_dapm_widgets = ARRAY_SIZE(wsa881x_dapm_widgets),
1083         .dapm_routes = wsa881x_audio_map,
1084         .num_dapm_routes = ARRAY_SIZE(wsa881x_audio_map),
1085 };
1086
1087 static int wsa881x_update_status(struct sdw_slave *slave,
1088                                  enum sdw_slave_status status)
1089 {
1090         struct wsa881x_priv *wsa881x = dev_get_drvdata(&slave->dev);
1091
1092         if (status == SDW_SLAVE_ATTACHED && slave->dev_num > 0)
1093                 wsa881x_init(wsa881x);
1094
1095         return 0;
1096 }
1097
1098 static int wsa881x_port_prep(struct sdw_slave *slave,
1099                              struct sdw_prepare_ch *prepare_ch,
1100                              enum sdw_port_prep_ops state)
1101 {
1102         struct wsa881x_priv *wsa881x = dev_get_drvdata(&slave->dev);
1103
1104         if (state == SDW_OPS_PORT_POST_PREP)
1105                 wsa881x->port_prepared[prepare_ch->num - 1] = true;
1106         else
1107                 wsa881x->port_prepared[prepare_ch->num - 1] = false;
1108
1109         return 0;
1110 }
1111
1112 static int wsa881x_bus_config(struct sdw_slave *slave,
1113                               struct sdw_bus_params *params)
1114 {
1115         sdw_write(slave, SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(params->next_bank),
1116                   0x01);
1117
1118         return 0;
1119 }
1120
1121 static struct sdw_slave_ops wsa881x_slave_ops = {
1122         .update_status = wsa881x_update_status,
1123         .bus_config = wsa881x_bus_config,
1124         .port_prep = wsa881x_port_prep,
1125 };
1126
1127 static int wsa881x_probe(struct sdw_slave *pdev,
1128                          const struct sdw_device_id *id)
1129 {
1130         struct wsa881x_priv *wsa881x;
1131
1132         wsa881x = devm_kzalloc(&pdev->dev, sizeof(*wsa881x), GFP_KERNEL);
1133         if (!wsa881x)
1134                 return -ENOMEM;
1135
1136         wsa881x->sd_n = devm_gpiod_get_optional(&pdev->dev, "powerdown",
1137                                                 GPIOD_FLAGS_BIT_NONEXCLUSIVE);
1138         if (IS_ERR(wsa881x->sd_n)) {
1139                 dev_err(&pdev->dev, "Shutdown Control GPIO not found\n");
1140                 return PTR_ERR(wsa881x->sd_n);
1141         }
1142
1143         dev_set_drvdata(&pdev->dev, wsa881x);
1144         wsa881x->slave = pdev;
1145         wsa881x->dev = &pdev->dev;
1146         wsa881x->sconfig.ch_count = 1;
1147         wsa881x->sconfig.bps = 1;
1148         wsa881x->sconfig.frame_rate = 48000;
1149         wsa881x->sconfig.direction = SDW_DATA_DIR_RX;
1150         wsa881x->sconfig.type = SDW_STREAM_PDM;
1151         pdev->prop.sink_ports = GENMASK(WSA881X_MAX_SWR_PORTS, 0);
1152         pdev->prop.sink_dpn_prop = wsa_sink_dpn_prop;
1153         gpiod_set_value(wsa881x->sd_n, 1);
1154
1155         wsa881x->regmap = devm_regmap_init_sdw(pdev, &wsa881x_regmap_config);
1156         if (IS_ERR(wsa881x->regmap)) {
1157                 dev_err(&pdev->dev, "regmap_init failed\n");
1158                 return PTR_ERR(wsa881x->regmap);
1159         }
1160
1161         return devm_snd_soc_register_component(&pdev->dev,
1162                                                &wsa881x_component_drv,
1163                                                wsa881x_dais,
1164                                                ARRAY_SIZE(wsa881x_dais));
1165 }
1166
1167 static const struct sdw_device_id wsa881x_slave_id[] = {
1168         SDW_SLAVE_ENTRY(0x0217, 0x2010, 0),
1169         SDW_SLAVE_ENTRY(0x0217, 0x2110, 0),
1170         {},
1171 };
1172 MODULE_DEVICE_TABLE(sdw, wsa881x_slave_id);
1173
1174 static struct sdw_driver wsa881x_codec_driver = {
1175         .probe  = wsa881x_probe,
1176         .ops = &wsa881x_slave_ops,
1177         .id_table = wsa881x_slave_id,
1178         .driver = {
1179                 .name   = "wsa881x-codec",
1180         }
1181 };
1182 module_sdw_driver(wsa881x_codec_driver);
1183
1184 MODULE_DESCRIPTION("WSA881x codec driver");
1185 MODULE_LICENSE("GPL v2");