sound/soc/codecs/wsa881x.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2015-2017, The Linux Foundation.
   3 // Copyright (c) 2019, Linaro Limited
   4
   5 #include <linux/bitops.h>
   6 #include <linux/gpio.h>
   7 #include <linux/gpio/consumer.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/of_gpio.h>
  12 #include <linux/regmap.h>
  13 #include <linux/slab.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/soundwire/sdw.h>
  16 #include <linux/soundwire/sdw_registers.h>
  17 #include <linux/soundwire/sdw_type.h>
  18 #include <sound/soc.h>
  19 #include <sound/tlv.h>
  20
  21 #define WSA881X_DIGITAL_BASE            0x3000
  22 #define WSA881X_ANALOG_BASE             0x3100
  23
  24 /* Digital register address space */
  25 #define WSA881X_CHIP_ID0                        (WSA881X_DIGITAL_BASE + 0x0000)
  26 #define WSA881X_CHIP_ID1                        (WSA881X_DIGITAL_BASE + 0x0001)
  27 #define WSA881X_CHIP_ID2                        (WSA881X_DIGITAL_BASE + 0x0002)
  28 #define WSA881X_CHIP_ID3                        (WSA881X_DIGITAL_BASE + 0x0003)
  29 #define WSA881X_BUS_ID                          (WSA881X_DIGITAL_BASE + 0x0004)
  30 #define WSA881X_CDC_RST_CTL                     (WSA881X_DIGITAL_BASE + 0x0005)
  31 #define WSA881X_CDC_TOP_CLK_CTL                 (WSA881X_DIGITAL_BASE + 0x0006)
  32 #define WSA881X_CDC_ANA_CLK_CTL                 (WSA881X_DIGITAL_BASE + 0x0007)
  33 #define WSA881X_CDC_DIG_CLK_CTL                 (WSA881X_DIGITAL_BASE + 0x0008)
  34 #define WSA881X_CLOCK_CONFIG                    (WSA881X_DIGITAL_BASE + 0x0009)
  35 #define WSA881X_ANA_CTL                         (WSA881X_DIGITAL_BASE + 0x000A)
  36 #define WSA881X_SWR_RESET_EN                    (WSA881X_DIGITAL_BASE + 0x000B)
  37 #define WSA881X_RESET_CTL                       (WSA881X_DIGITAL_BASE + 0x000C)
  38 #define WSA881X_TADC_VALUE_CTL                  (WSA881X_DIGITAL_BASE + 0x000F)
  39 #define WSA881X_TEMP_DETECT_CTL                 (WSA881X_DIGITAL_BASE + 0x0010)
  40 #define WSA881X_TEMP_MSB                        (WSA881X_DIGITAL_BASE + 0x0011)
  41 #define WSA881X_TEMP_LSB                        (WSA881X_DIGITAL_BASE + 0x0012)
  42 #define WSA881X_TEMP_CONFIG0                    (WSA881X_DIGITAL_BASE + 0x0013)
  43 #define WSA881X_TEMP_CONFIG1                    (WSA881X_DIGITAL_BASE + 0x0014)
  44 #define WSA881X_CDC_CLIP_CTL                    (WSA881X_DIGITAL_BASE + 0x0015)
  45 #define WSA881X_SDM_PDM9_LSB                    (WSA881X_DIGITAL_BASE + 0x0016)
  46 #define WSA881X_SDM_PDM9_MSB                    (WSA881X_DIGITAL_BASE + 0x0017)
  47 #define WSA881X_CDC_RX_CTL                      (WSA881X_DIGITAL_BASE + 0x0018)
  48 #define WSA881X_DEM_BYPASS_DATA0                (WSA881X_DIGITAL_BASE + 0x0019)
  49 #define WSA881X_DEM_BYPASS_DATA1                (WSA881X_DIGITAL_BASE + 0x001A)
  50 #define WSA881X_DEM_BYPASS_DATA2                (WSA881X_DIGITAL_BASE + 0x001B)
  51 #define WSA881X_DEM_BYPASS_DATA3                (WSA881X_DIGITAL_BASE + 0x001C)
  52 #define WSA881X_OTP_CTRL0                       (WSA881X_DIGITAL_BASE + 0x001D)
  53 #define WSA881X_OTP_CTRL1                       (WSA881X_DIGITAL_BASE + 0x001E)
  54 #define WSA881X_HDRIVE_CTL_GROUP1               (WSA881X_DIGITAL_BASE + 0x001F)
  55 #define WSA881X_INTR_MODE                       (WSA881X_DIGITAL_BASE + 0x0020)
  56 #define WSA881X_INTR_MASK                       (WSA881X_DIGITAL_BASE + 0x0021)
  57 #define WSA881X_INTR_STATUS                     (WSA881X_DIGITAL_BASE + 0x0022)
  58 #define WSA881X_INTR_CLEAR                      (WSA881X_DIGITAL_BASE + 0x0023)
  59 #define WSA881X_INTR_LEVEL                      (WSA881X_DIGITAL_BASE + 0x0024)
  60 #define WSA881X_INTR_SET                        (WSA881X_DIGITAL_BASE + 0x0025)
  61 #define WSA881X_INTR_TEST                       (WSA881X_DIGITAL_BASE + 0x0026)
  62 #define WSA881X_PDM_TEST_MODE                   (WSA881X_DIGITAL_BASE + 0x0030)
  63 #define WSA881X_ATE_TEST_MODE                   (WSA881X_DIGITAL_BASE + 0x0031)
  64 #define WSA881X_PIN_CTL_MODE                    (WSA881X_DIGITAL_BASE + 0x0032)
  65 #define WSA881X_PIN_CTL_OE                      (WSA881X_DIGITAL_BASE + 0x0033)
  66 #define WSA881X_PIN_WDATA_IOPAD                 (WSA881X_DIGITAL_BASE + 0x0034)
  67 #define WSA881X_PIN_STATUS                      (WSA881X_DIGITAL_BASE + 0x0035)
  68 #define WSA881X_DIG_DEBUG_MODE                  (WSA881X_DIGITAL_BASE + 0x0037)
  69 #define WSA881X_DIG_DEBUG_SEL                   (WSA881X_DIGITAL_BASE + 0x0038)
  70 #define WSA881X_DIG_DEBUG_EN                    (WSA881X_DIGITAL_BASE + 0x0039)
  71 #define WSA881X_SWR_HM_TEST1                    (WSA881X_DIGITAL_BASE + 0x003B)
  72 #define WSA881X_SWR_HM_TEST2                    (WSA881X_DIGITAL_BASE + 0x003C)
  73 #define WSA881X_TEMP_DETECT_DBG_CTL             (WSA881X_DIGITAL_BASE + 0x003D)
  74 #define WSA881X_TEMP_DEBUG_MSB                  (WSA881X_DIGITAL_BASE + 0x003E)
  75 #define WSA881X_TEMP_DEBUG_LSB                  (WSA881X_DIGITAL_BASE + 0x003F)
  76 #define WSA881X_SAMPLE_EDGE_SEL                 (WSA881X_DIGITAL_BASE + 0x0044)
  77 #define WSA881X_IOPAD_CTL                       (WSA881X_DIGITAL_BASE + 0x0045)
  78 #define WSA881X_SPARE_0                         (WSA881X_DIGITAL_BASE + 0x0050)
  79 #define WSA881X_SPARE_1                         (WSA881X_DIGITAL_BASE + 0x0051)
  80 #define WSA881X_SPARE_2                         (WSA881X_DIGITAL_BASE + 0x0052)
  81 #define WSA881X_OTP_REG_0                       (WSA881X_DIGITAL_BASE + 0x0080)
  82 #define WSA881X_OTP_REG_1                       (WSA881X_DIGITAL_BASE + 0x0081)
  83 #define WSA881X_OTP_REG_2                       (WSA881X_DIGITAL_BASE + 0x0082)
  84 #define WSA881X_OTP_REG_3                       (WSA881X_DIGITAL_BASE + 0x0083)
  85 #define WSA881X_OTP_REG_4                       (WSA881X_DIGITAL_BASE + 0x0084)
  86 #define WSA881X_OTP_REG_5                       (WSA881X_DIGITAL_BASE + 0x0085)
  87 #define WSA881X_OTP_REG_6                       (WSA881X_DIGITAL_BASE + 0x0086)
  88 #define WSA881X_OTP_REG_7                       (WSA881X_DIGITAL_BASE + 0x0087)
  89 #define WSA881X_OTP_REG_8                       (WSA881X_DIGITAL_BASE + 0x0088)
  90 #define WSA881X_OTP_REG_9                       (WSA881X_DIGITAL_BASE + 0x0089)
  91 #define WSA881X_OTP_REG_10                      (WSA881X_DIGITAL_BASE + 0x008A)
  92 #define WSA881X_OTP_REG_11                      (WSA881X_DIGITAL_BASE + 0x008B)
  93 #define WSA881X_OTP_REG_12                      (WSA881X_DIGITAL_BASE + 0x008C)
  94 #define WSA881X_OTP_REG_13                      (WSA881X_DIGITAL_BASE + 0x008D)
  95 #define WSA881X_OTP_REG_14                      (WSA881X_DIGITAL_BASE + 0x008E)
  96 #define WSA881X_OTP_REG_15                      (WSA881X_DIGITAL_BASE + 0x008F)
  97 #define WSA881X_OTP_REG_16                      (WSA881X_DIGITAL_BASE + 0x0090)
  98 #define WSA881X_OTP_REG_17                      (WSA881X_DIGITAL_BASE + 0x0091)
  99 #define WSA881X_OTP_REG_18                      (WSA881X_DIGITAL_BASE + 0x0092)
 100 #define WSA881X_OTP_REG_19                      (WSA881X_DIGITAL_BASE + 0x0093)
 101 #define WSA881X_OTP_REG_20                      (WSA881X_DIGITAL_BASE + 0x0094)
 102 #define WSA881X_OTP_REG_21                      (WSA881X_DIGITAL_BASE + 0x0095)
 103 #define WSA881X_OTP_REG_22                      (WSA881X_DIGITAL_BASE + 0x0096)
 104 #define WSA881X_OTP_REG_23                      (WSA881X_DIGITAL_BASE + 0x0097)
 105 #define WSA881X_OTP_REG_24                      (WSA881X_DIGITAL_BASE + 0x0098)
 106 #define WSA881X_OTP_REG_25                      (WSA881X_DIGITAL_BASE + 0x0099)
 107 #define WSA881X_OTP_REG_26                      (WSA881X_DIGITAL_BASE + 0x009A)
 108 #define WSA881X_OTP_REG_27                      (WSA881X_DIGITAL_BASE + 0x009B)
 109 #define WSA881X_OTP_REG_28                      (WSA881X_DIGITAL_BASE + 0x009C)
 110 #define WSA881X_OTP_REG_29                      (WSA881X_DIGITAL_BASE + 0x009D)
 111 #define WSA881X_OTP_REG_30                      (WSA881X_DIGITAL_BASE + 0x009E)
 112 #define WSA881X_OTP_REG_31                      (WSA881X_DIGITAL_BASE + 0x009F)
 113 #define WSA881X_OTP_REG_63                      (WSA881X_DIGITAL_BASE + 0x00BF)
 114
 115 /* Analog Register address space */
 116 #define WSA881X_BIAS_REF_CTRL                   (WSA881X_ANALOG_BASE + 0x0000)
 117 #define WSA881X_BIAS_TEST                       (WSA881X_ANALOG_BASE + 0x0001)
 118 #define WSA881X_BIAS_BIAS                       (WSA881X_ANALOG_BASE + 0x0002)
 119 #define WSA881X_TEMP_OP                         (WSA881X_ANALOG_BASE + 0x0003)
 120 #define WSA881X_TEMP_IREF_CTRL                  (WSA881X_ANALOG_BASE + 0x0004)
 121 #define WSA881X_TEMP_ISENS_CTRL                 (WSA881X_ANALOG_BASE + 0x0005)
 122 #define WSA881X_TEMP_CLK_CTRL                   (WSA881X_ANALOG_BASE + 0x0006)
 123 #define WSA881X_TEMP_TEST                       (WSA881X_ANALOG_BASE + 0x0007)
 124 #define WSA881X_TEMP_BIAS                       (WSA881X_ANALOG_BASE + 0x0008)
 125 #define WSA881X_TEMP_ADC_CTRL                   (WSA881X_ANALOG_BASE + 0x0009)
 126 #define WSA881X_TEMP_DOUT_MSB                   (WSA881X_ANALOG_BASE + 0x000A)
 127 #define WSA881X_TEMP_DOUT_LSB                   (WSA881X_ANALOG_BASE + 0x000B)
 128 #define WSA881X_ADC_EN_MODU_V                   (WSA881X_ANALOG_BASE + 0x0010)
 129 #define WSA881X_ADC_EN_MODU_I                   (WSA881X_ANALOG_BASE + 0x0011)
 130 #define WSA881X_ADC_EN_DET_TEST_V               (WSA881X_ANALOG_BASE + 0x0012)
 131 #define WSA881X_ADC_EN_DET_TEST_I               (WSA881X_ANALOG_BASE + 0x0013)
 132 #define WSA881X_ADC_SEL_IBIAS                   (WSA881X_ANALOG_BASE + 0x0014)
 133 #define WSA881X_ADC_EN_SEL_IBAIS                (WSA881X_ANALOG_BASE + 0x0015)
 134 #define WSA881X_SPKR_DRV_EN                     (WSA881X_ANALOG_BASE + 0x001A)
 135 #define WSA881X_SPKR_DRV_GAIN                   (WSA881X_ANALOG_BASE + 0x001B)
 136 #define WSA881X_PA_GAIN_SEL_MASK                BIT(3)
 137 #define WSA881X_PA_GAIN_SEL_REG                 BIT(3)
 138 #define WSA881X_PA_GAIN_SEL_DRE                 0
 139 #define WSA881X_SPKR_PAG_GAIN_MASK              GENMASK(7, 4)
 140 #define WSA881X_SPKR_DAC_CTL                    (WSA881X_ANALOG_BASE + 0x001C)
 141 #define WSA881X_SPKR_DRV_DBG                    (WSA881X_ANALOG_BASE + 0x001D)
 142 #define WSA881X_SPKR_PWRSTG_DBG                 (WSA881X_ANALOG_BASE + 0x001E)
 143 #define WSA881X_SPKR_OCP_CTL                    (WSA881X_ANALOG_BASE + 0x001F)
 144 #define WSA881X_SPKR_OCP_MASK                   GENMASK(7, 6)
 145 #define WSA881X_SPKR_OCP_EN                     BIT(7)
 146 #define WSA881X_SPKR_OCP_HOLD                   BIT(6)
 147 #define WSA881X_SPKR_CLIP_CTL                   (WSA881X_ANALOG_BASE + 0x0020)
 148 #define WSA881X_SPKR_BBM_CTL                    (WSA881X_ANALOG_BASE + 0x0021)
 149 #define WSA881X_SPKR_MISC_CTL1                  (WSA881X_ANALOG_BASE + 0x0022)
 150 #define WSA881X_SPKR_MISC_CTL2                  (WSA881X_ANALOG_BASE + 0x0023)
 151 #define WSA881X_SPKR_BIAS_INT                   (WSA881X_ANALOG_BASE + 0x0024)
 152 #define WSA881X_SPKR_PA_INT                     (WSA881X_ANALOG_BASE + 0x0025)
 153 #define WSA881X_SPKR_BIAS_CAL                   (WSA881X_ANALOG_BASE + 0x0026)
 154 #define WSA881X_SPKR_BIAS_PSRR                  (WSA881X_ANALOG_BASE + 0x0027)
 155 #define WSA881X_SPKR_STATUS1                    (WSA881X_ANALOG_BASE + 0x0028)
 156 #define WSA881X_SPKR_STATUS2                    (WSA881X_ANALOG_BASE + 0x0029)
 157 #define WSA881X_BOOST_EN_CTL                    (WSA881X_ANALOG_BASE + 0x002A)
 158 #define WSA881X_BOOST_EN_MASK                   BIT(7)
 159 #define WSA881X_BOOST_EN                        BIT(7)
 160 #define WSA881X_BOOST_CURRENT_LIMIT             (WSA881X_ANALOG_BASE + 0x002B)
 161 #define WSA881X_BOOST_PS_CTL                    (WSA881X_ANALOG_BASE + 0x002C)
 162 #define WSA881X_BOOST_PRESET_OUT1               (WSA881X_ANALOG_BASE + 0x002D)
 163 #define WSA881X_BOOST_PRESET_OUT2               (WSA881X_ANALOG_BASE + 0x002E)
 164 #define WSA881X_BOOST_FORCE_OUT                 (WSA881X_ANALOG_BASE + 0x002F)
 165 #define WSA881X_BOOST_LDO_PROG                  (WSA881X_ANALOG_BASE + 0x0030)
 166 #define WSA881X_BOOST_SLOPE_COMP_ISENSE_FB      (WSA881X_ANALOG_BASE + 0x0031)
 167 #define WSA881X_BOOST_RON_CTL                   (WSA881X_ANALOG_BASE + 0x0032)
 168 #define WSA881X_BOOST_LOOP_STABILITY            (WSA881X_ANALOG_BASE + 0x0033)
 169 #define WSA881X_BOOST_ZX_CTL                    (WSA881X_ANALOG_BASE + 0x0034)
 170 #define WSA881X_BOOST_START_CTL                 (WSA881X_ANALOG_BASE + 0x0035)
 171 #define WSA881X_BOOST_MISC1_CTL                 (WSA881X_ANALOG_BASE + 0x0036)
 172 #define WSA881X_BOOST_MISC2_CTL                 (WSA881X_ANALOG_BASE + 0x0037)
 173 #define WSA881X_BOOST_MISC3_CTL                 (WSA881X_ANALOG_BASE + 0x0038)
 174 #define WSA881X_BOOST_ATEST_CTL                 (WSA881X_ANALOG_BASE + 0x0039)
 175 #define WSA881X_SPKR_PROT_FE_GAIN               (WSA881X_ANALOG_BASE + 0x003A)
 176 #define WSA881X_SPKR_PROT_FE_CM_LDO_SET         (WSA881X_ANALOG_BASE + 0x003B)
 177 #define WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1   (WSA881X_ANALOG_BASE + 0x003C)
 178 #define WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2   (WSA881X_ANALOG_BASE + 0x003D)
 179 #define WSA881X_SPKR_PROT_ATEST1                (WSA881X_ANALOG_BASE + 0x003E)
 180 #define WSA881X_SPKR_PROT_ATEST2                (WSA881X_ANALOG_BASE + 0x003F)
 181 #define WSA881X_SPKR_PROT_FE_VSENSE_VCM         (WSA881X_ANALOG_BASE + 0x0040)
 182 #define WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1   (WSA881X_ANALOG_BASE + 0x0041)
 183 #define WSA881X_BONGO_RESRV_REG1                (WSA881X_ANALOG_BASE + 0x0042)
 184 #define WSA881X_BONGO_RESRV_REG2                (WSA881X_ANALOG_BASE + 0x0043)
 185 #define WSA881X_SPKR_PROT_SAR                   (WSA881X_ANALOG_BASE + 0x0044)
 186 #define WSA881X_SPKR_STATUS3                    (WSA881X_ANALOG_BASE + 0x0045)
 187
 188 #define SWRS_SCP_FRAME_CTRL_BANK(m)             (0x60 + 0x10 * (m))
 189 #define SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(m)      (0xE0 + 0x10 * (m))
 190 #define SWR_SLV_MAX_REG_ADDR    0x390
 191 #define SWR_SLV_START_REG_ADDR  0x40
 192 #define SWR_SLV_MAX_BUF_LEN     20
 193 #define BYTES_PER_LINE          12
 194 #define SWR_SLV_RD_BUF_LEN      8
 195 #define SWR_SLV_WR_BUF_LEN      32
 196 #define SWR_SLV_MAX_DEVICES     2
 197 #define WSA881X_MAX_SWR_PORTS   4
 198 #define WSA881X_VERSION_ENTRY_SIZE 27
 199 #define WSA881X_OCP_CTL_TIMER_SEC 2
 200 #define WSA881X_OCP_CTL_TEMP_CELSIUS 25
 201 #define WSA881X_OCP_CTL_POLL_TIMER_SEC 60
 202 #define WSA881X_PROBE_TIMEOUT 1000
 203
 204 #define WSA881X_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
 205 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 206         .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
 207                  SNDRV_CTL_ELEM_ACCESS_READWRITE,\
 208         .tlv.p = (tlv_array), \
 209         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
 210         .put = wsa881x_put_pa_gain, \
 211         .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
 212
 213 static struct reg_default wsa881x_defaults[] = {
 214         { WSA881X_CHIP_ID0, 0x00 },
 215         { WSA881X_CHIP_ID1, 0x00 },
 216         { WSA881X_CHIP_ID2, 0x00 },
 217         { WSA881X_CHIP_ID3, 0x02 },
 218         { WSA881X_BUS_ID, 0x00 },
 219         { WSA881X_CDC_RST_CTL, 0x00 },
 220         { WSA881X_CDC_TOP_CLK_CTL, 0x03 },
 221         { WSA881X_CDC_ANA_CLK_CTL, 0x00 },
 222         { WSA881X_CDC_DIG_CLK_CTL, 0x00 },
 223         { WSA881X_CLOCK_CONFIG, 0x00 },
 224         { WSA881X_ANA_CTL, 0x08 },
 225         { WSA881X_SWR_RESET_EN, 0x00 },
 226         { WSA881X_TEMP_DETECT_CTL, 0x01 },
 227         { WSA881X_TEMP_MSB, 0x00 },
 228         { WSA881X_TEMP_LSB, 0x00 },
 229         { WSA881X_TEMP_CONFIG0, 0x00 },
 230         { WSA881X_TEMP_CONFIG1, 0x00 },
 231         { WSA881X_CDC_CLIP_CTL, 0x03 },
 232         { WSA881X_SDM_PDM9_LSB, 0x00 },
 233         { WSA881X_SDM_PDM9_MSB, 0x00 },
 234         { WSA881X_CDC_RX_CTL, 0x7E },
 235         { WSA881X_DEM_BYPASS_DATA0, 0x00 },
 236         { WSA881X_DEM_BYPASS_DATA1, 0x00 },
 237         { WSA881X_DEM_BYPASS_DATA2, 0x00 },
 238         { WSA881X_DEM_BYPASS_DATA3, 0x00 },
 239         { WSA881X_OTP_CTRL0, 0x00 },
 240         { WSA881X_OTP_CTRL1, 0x00 },
 241         { WSA881X_HDRIVE_CTL_GROUP1, 0x00 },
 242         { WSA881X_INTR_MODE, 0x00 },
 243         { WSA881X_INTR_STATUS, 0x00 },
 244         { WSA881X_INTR_CLEAR, 0x00 },
 245         { WSA881X_INTR_LEVEL, 0x00 },
 246         { WSA881X_INTR_SET, 0x00 },
 247         { WSA881X_INTR_TEST, 0x00 },
 248         { WSA881X_PDM_TEST_MODE, 0x00 },
 249         { WSA881X_ATE_TEST_MODE, 0x00 },
 250         { WSA881X_PIN_CTL_MODE, 0x00 },
 251         { WSA881X_PIN_CTL_OE, 0x00 },
 252         { WSA881X_PIN_WDATA_IOPAD, 0x00 },
 253         { WSA881X_PIN_STATUS, 0x00 },
 254         { WSA881X_DIG_DEBUG_MODE, 0x00 },
 255         { WSA881X_DIG_DEBUG_SEL, 0x00 },
 256         { WSA881X_DIG_DEBUG_EN, 0x00 },
 257         { WSA881X_SWR_HM_TEST1, 0x08 },
 258         { WSA881X_SWR_HM_TEST2, 0x00 },
 259         { WSA881X_TEMP_DETECT_DBG_CTL, 0x00 },
 260         { WSA881X_TEMP_DEBUG_MSB, 0x00 },
 261         { WSA881X_TEMP_DEBUG_LSB, 0x00 },
 262         { WSA881X_SAMPLE_EDGE_SEL, 0x0C },
 263         { WSA881X_SPARE_0, 0x00 },
 264         { WSA881X_SPARE_1, 0x00 },
 265         { WSA881X_SPARE_2, 0x00 },
 266         { WSA881X_OTP_REG_0, 0x01 },
 267         { WSA881X_OTP_REG_1, 0xFF },
 268         { WSA881X_OTP_REG_2, 0xC0 },
 269         { WSA881X_OTP_REG_3, 0xFF },
 270         { WSA881X_OTP_REG_4, 0xC0 },
 271         { WSA881X_OTP_REG_5, 0xFF },
 272         { WSA881X_OTP_REG_6, 0xFF },
 273         { WSA881X_OTP_REG_7, 0xFF },
 274         { WSA881X_OTP_REG_8, 0xFF },
 275         { WSA881X_OTP_REG_9, 0xFF },
 276         { WSA881X_OTP_REG_10, 0xFF },
 277         { WSA881X_OTP_REG_11, 0xFF },
 278         { WSA881X_OTP_REG_12, 0xFF },
 279         { WSA881X_OTP_REG_13, 0xFF },
 280         { WSA881X_OTP_REG_14, 0xFF },
 281         { WSA881X_OTP_REG_15, 0xFF },
 282         { WSA881X_OTP_REG_16, 0xFF },
 283         { WSA881X_OTP_REG_17, 0xFF },
 284         { WSA881X_OTP_REG_18, 0xFF },
 285         { WSA881X_OTP_REG_19, 0xFF },
 286         { WSA881X_OTP_REG_20, 0xFF },
 287         { WSA881X_OTP_REG_21, 0xFF },
 288         { WSA881X_OTP_REG_22, 0xFF },
 289         { WSA881X_OTP_REG_23, 0xFF },
 290         { WSA881X_OTP_REG_24, 0x03 },
 291         { WSA881X_OTP_REG_25, 0x01 },
 292         { WSA881X_OTP_REG_26, 0x03 },
 293         { WSA881X_OTP_REG_27, 0x11 },
 294         { WSA881X_OTP_REG_63, 0x40 },
 295         /* WSA881x Analog registers */
 296         { WSA881X_BIAS_REF_CTRL, 0x6C },
 297         { WSA881X_BIAS_TEST, 0x16 },
 298         { WSA881X_BIAS_BIAS, 0xF0 },
 299         { WSA881X_TEMP_OP, 0x00 },
 300         { WSA881X_TEMP_IREF_CTRL, 0x56 },
 301         { WSA881X_TEMP_ISENS_CTRL, 0x47 },
 302         { WSA881X_TEMP_CLK_CTRL, 0x87 },
 303         { WSA881X_TEMP_TEST, 0x00 },
 304         { WSA881X_TEMP_BIAS, 0x51 },
 305         { WSA881X_TEMP_DOUT_MSB, 0x00 },
 306         { WSA881X_TEMP_DOUT_LSB, 0x00 },
 307         { WSA881X_ADC_EN_MODU_V, 0x00 },
 308         { WSA881X_ADC_EN_MODU_I, 0x00 },
 309         { WSA881X_ADC_EN_DET_TEST_V, 0x00 },
 310         { WSA881X_ADC_EN_DET_TEST_I, 0x00 },
 311         { WSA881X_ADC_EN_SEL_IBAIS, 0x10 },
 312         { WSA881X_SPKR_DRV_EN, 0x74 },
 313         { WSA881X_SPKR_DRV_DBG, 0x15 },
 314         { WSA881X_SPKR_PWRSTG_DBG, 0x00 },
 315         { WSA881X_SPKR_OCP_CTL, 0xD4 },
 316         { WSA881X_SPKR_CLIP_CTL, 0x90 },
 317         { WSA881X_SPKR_PA_INT, 0x54 },
 318         { WSA881X_SPKR_BIAS_CAL, 0xAC },
 319         { WSA881X_SPKR_STATUS1, 0x00 },
 320         { WSA881X_SPKR_STATUS2, 0x00 },
 321         { WSA881X_BOOST_EN_CTL, 0x18 },
 322         { WSA881X_BOOST_CURRENT_LIMIT, 0x7A },
 323         { WSA881X_BOOST_PRESET_OUT2, 0x70 },
 324         { WSA881X_BOOST_FORCE_OUT, 0x0E },
 325         { WSA881X_BOOST_LDO_PROG, 0x16 },
 326         { WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x71 },
 327         { WSA881X_BOOST_RON_CTL, 0x0F },
 328         { WSA881X_BOOST_ZX_CTL, 0x34 },
 329         { WSA881X_BOOST_START_CTL, 0x23 },
 330         { WSA881X_BOOST_MISC1_CTL, 0x80 },
 331         { WSA881X_BOOST_MISC2_CTL, 0x00 },
 332         { WSA881X_BOOST_MISC3_CTL, 0x00 },
 333         { WSA881X_BOOST_ATEST_CTL, 0x00 },
 334         { WSA881X_SPKR_PROT_FE_GAIN, 0x46 },
 335         { WSA881X_SPKR_PROT_FE_CM_LDO_SET, 0x3B },
 336         { WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1, 0x8D },
 337         { WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2, 0x8D },
 338         { WSA881X_SPKR_PROT_ATEST1, 0x01 },
 339         { WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x8D },
 340         { WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1, 0x4D },
 341         { WSA881X_SPKR_PROT_SAR, 0x00 },
 342         { WSA881X_SPKR_STATUS3, 0x00 },
 343 };
 344
 345 static const struct reg_sequence wsa881x_pre_pmu_pa_2_0[] = {
 346         { WSA881X_SPKR_DRV_GAIN, 0x41, 0 },
 347         { WSA881X_SPKR_MISC_CTL1, 0x87, 0 },
 348 };
 349
 350 static const struct reg_sequence wsa881x_vi_txfe_en_2_0[] = {
 351         { WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x85, 0 },
 352         { WSA881X_SPKR_PROT_ATEST2, 0x0A, 0 },
 353         { WSA881X_SPKR_PROT_FE_GAIN, 0x47, 0 },
 354 };
 355
 356 /* Default register reset values for WSA881x rev 2.0 */
 357 static struct reg_sequence wsa881x_rev_2_0[] = {
 358         { WSA881X_RESET_CTL, 0x00, 0x00 },
 359         { WSA881X_TADC_VALUE_CTL, 0x01, 0x00 },
 360         { WSA881X_INTR_MASK, 0x1B, 0x00 },
 361         { WSA881X_IOPAD_CTL, 0x00, 0x00 },
 362         { WSA881X_OTP_REG_28, 0x3F, 0x00 },
 363         { WSA881X_OTP_REG_29, 0x3F, 0x00 },
 364         { WSA881X_OTP_REG_30, 0x01, 0x00 },
 365         { WSA881X_OTP_REG_31, 0x01, 0x00 },
 366         { WSA881X_TEMP_ADC_CTRL, 0x03, 0x00 },
 367         { WSA881X_ADC_SEL_IBIAS, 0x45, 0x00 },
 368         { WSA881X_SPKR_DRV_GAIN, 0xC1, 0x00 },
 369         { WSA881X_SPKR_DAC_CTL, 0x42, 0x00 },
 370         { WSA881X_SPKR_BBM_CTL, 0x02, 0x00 },
 371         { WSA881X_SPKR_MISC_CTL1, 0x40, 0x00 },
 372         { WSA881X_SPKR_MISC_CTL2, 0x07, 0x00 },
 373         { WSA881X_SPKR_BIAS_INT, 0x5F, 0x00 },
 374         { WSA881X_SPKR_BIAS_PSRR, 0x44, 0x00 },
 375         { WSA881X_BOOST_PS_CTL, 0xA0, 0x00 },
 376         { WSA881X_BOOST_PRESET_OUT1, 0xB7, 0x00 },
 377         { WSA881X_BOOST_LOOP_STABILITY, 0x8D, 0x00 },
 378         { WSA881X_SPKR_PROT_ATEST2, 0x02, 0x00 },
 379         { WSA881X_BONGO_RESRV_REG1, 0x5E, 0x00 },
 380         { WSA881X_BONGO_RESRV_REG2, 0x07, 0x00 },
 381 };
 382
 383 enum wsa_port_ids {
 384         WSA881X_PORT_DAC,
 385         WSA881X_PORT_COMP,
 386         WSA881X_PORT_BOOST,
 387         WSA881X_PORT_VISENSE,
 388 };
 389
 390 /* 4 ports */
 391 static struct sdw_dpn_prop wsa_sink_dpn_prop[WSA881X_MAX_SWR_PORTS] = {
 392         {
 393                 /* DAC */
 394                 .num = 1,
 395                 .type = SDW_DPN_SIMPLE,
 396                 .min_ch = 1,
 397                 .max_ch = 1,
 398                 .simple_ch_prep_sm = true,
 399                 .read_only_wordlength = true,
 400         }, {
 401                 /* COMP */
 402                 .num = 2,
 403                 .type = SDW_DPN_SIMPLE,
 404                 .min_ch = 1,
 405                 .max_ch = 1,
 406                 .simple_ch_prep_sm = true,
 407                 .read_only_wordlength = true,
 408         }, {
 409                 /* BOOST */
 410                 .num = 3,
 411                 .type = SDW_DPN_SIMPLE,
 412                 .min_ch = 1,
 413                 .max_ch = 1,
 414                 .simple_ch_prep_sm = true,
 415                 .read_only_wordlength = true,
 416         }, {
 417                 /* VISENSE */
 418                 .num = 4,
 419                 .type = SDW_DPN_SIMPLE,
 420                 .min_ch = 1,
 421                 .max_ch = 1,
 422                 .simple_ch_prep_sm = true,
 423                 .read_only_wordlength = true,
 424         }
 425 };
 426
 427 static struct sdw_port_config wsa881x_pconfig[WSA881X_MAX_SWR_PORTS] = {
 428         {
 429                 .num = 1,
 430                 .ch_mask = 0x1,
 431         }, {
 432                 .num = 2,
 433                 .ch_mask = 0xf,
 434         }, {
 435                 .num = 3,
 436                 .ch_mask = 0x3,
 437         }, {    /* IV feedback */
 438                 .num = 4,
 439                 .ch_mask = 0x3,
 440         },
 441 };
 442
 443 static bool wsa881x_readable_register(struct device *dev, unsigned int reg)
 444 {
 445         switch (reg) {
 446         case WSA881X_CHIP_ID0:
 447         case WSA881X_CHIP_ID1:
 448         case WSA881X_CHIP_ID2:
 449         case WSA881X_CHIP_ID3:
 450         case WSA881X_BUS_ID:
 451         case WSA881X_CDC_RST_CTL:
 452         case WSA881X_CDC_TOP_CLK_CTL:
 453         case WSA881X_CDC_ANA_CLK_CTL:
 454         case WSA881X_CDC_DIG_CLK_CTL:
 455         case WSA881X_CLOCK_CONFIG:
 456         case WSA881X_ANA_CTL:
 457         case WSA881X_SWR_RESET_EN:
 458         case WSA881X_RESET_CTL:
 459         case WSA881X_TADC_VALUE_CTL:
 460         case WSA881X_TEMP_DETECT_CTL:
 461         case WSA881X_TEMP_MSB:
 462         case WSA881X_TEMP_LSB:
 463         case WSA881X_TEMP_CONFIG0:
 464         case WSA881X_TEMP_CONFIG1:
 465         case WSA881X_CDC_CLIP_CTL:
 466         case WSA881X_SDM_PDM9_LSB:
 467         case WSA881X_SDM_PDM9_MSB:
 468         case WSA881X_CDC_RX_CTL:
 469         case WSA881X_DEM_BYPASS_DATA0:
 470         case WSA881X_DEM_BYPASS_DATA1:
 471         case WSA881X_DEM_BYPASS_DATA2:
 472         case WSA881X_DEM_BYPASS_DATA3:
 473         case WSA881X_OTP_CTRL0:
 474         case WSA881X_OTP_CTRL1:
 475         case WSA881X_HDRIVE_CTL_GROUP1:
 476         case WSA881X_INTR_MODE:
 477         case WSA881X_INTR_MASK:
 478         case WSA881X_INTR_STATUS:
 479         case WSA881X_INTR_CLEAR:
 480         case WSA881X_INTR_LEVEL:
 481         case WSA881X_INTR_SET:
 482         case WSA881X_INTR_TEST:
 483         case WSA881X_PDM_TEST_MODE:
 484         case WSA881X_ATE_TEST_MODE:
 485         case WSA881X_PIN_CTL_MODE:
 486         case WSA881X_PIN_CTL_OE:
 487         case WSA881X_PIN_WDATA_IOPAD:
 488         case WSA881X_PIN_STATUS:
 489         case WSA881X_DIG_DEBUG_MODE:
 490         case WSA881X_DIG_DEBUG_SEL:
 491         case WSA881X_DIG_DEBUG_EN:
 492         case WSA881X_SWR_HM_TEST1:
 493         case WSA881X_SWR_HM_TEST2:
 494         case WSA881X_TEMP_DETECT_DBG_CTL:
 495         case WSA881X_TEMP_DEBUG_MSB:
 496         case WSA881X_TEMP_DEBUG_LSB:
 497         case WSA881X_SAMPLE_EDGE_SEL:
 498         case WSA881X_IOPAD_CTL:
 499         case WSA881X_SPARE_0:
 500         case WSA881X_SPARE_1:
 501         case WSA881X_SPARE_2:
 502         case WSA881X_OTP_REG_0:
 503         case WSA881X_OTP_REG_1:
 504         case WSA881X_OTP_REG_2:
 505         case WSA881X_OTP_REG_3:
 506         case WSA881X_OTP_REG_4:
 507         case WSA881X_OTP_REG_5:
 508         case WSA881X_OTP_REG_6:
 509         case WSA881X_OTP_REG_7:
 510         case WSA881X_OTP_REG_8:
 511         case WSA881X_OTP_REG_9:
 512         case WSA881X_OTP_REG_10:
 513         case WSA881X_OTP_REG_11:
 514         case WSA881X_OTP_REG_12:
 515         case WSA881X_OTP_REG_13:
 516         case WSA881X_OTP_REG_14:
 517         case WSA881X_OTP_REG_15:
 518         case WSA881X_OTP_REG_16:
 519         case WSA881X_OTP_REG_17:
 520         case WSA881X_OTP_REG_18:
 521         case WSA881X_OTP_REG_19:
 522         case WSA881X_OTP_REG_20:
 523         case WSA881X_OTP_REG_21:
 524         case WSA881X_OTP_REG_22:
 525         case WSA881X_OTP_REG_23:
 526         case WSA881X_OTP_REG_24:
 527         case WSA881X_OTP_REG_25:
 528         case WSA881X_OTP_REG_26:
 529         case WSA881X_OTP_REG_27:
 530         case WSA881X_OTP_REG_28:
 531         case WSA881X_OTP_REG_29:
 532         case WSA881X_OTP_REG_30:
 533         case WSA881X_OTP_REG_31:
 534         case WSA881X_OTP_REG_63:
 535         case WSA881X_BIAS_REF_CTRL:
 536         case WSA881X_BIAS_TEST:
 537         case WSA881X_BIAS_BIAS:
 538         case WSA881X_TEMP_OP:
 539         case WSA881X_TEMP_IREF_CTRL:
 540         case WSA881X_TEMP_ISENS_CTRL:
 541         case WSA881X_TEMP_CLK_CTRL:
 542         case WSA881X_TEMP_TEST:
 543         case WSA881X_TEMP_BIAS:
 544         case WSA881X_TEMP_ADC_CTRL:
 545         case WSA881X_TEMP_DOUT_MSB:
 546         case WSA881X_TEMP_DOUT_LSB:
 547         case WSA881X_ADC_EN_MODU_V:
 548         case WSA881X_ADC_EN_MODU_I:
 549         case WSA881X_ADC_EN_DET_TEST_V:
 550         case WSA881X_ADC_EN_DET_TEST_I:
 551         case WSA881X_ADC_SEL_IBIAS:
 552         case WSA881X_ADC_EN_SEL_IBAIS:
 553         case WSA881X_SPKR_DRV_EN:
 554         case WSA881X_SPKR_DRV_GAIN:
 555         case WSA881X_SPKR_DAC_CTL:
 556         case WSA881X_SPKR_DRV_DBG:
 557         case WSA881X_SPKR_PWRSTG_DBG:
 558         case WSA881X_SPKR_OCP_CTL:
 559         case WSA881X_SPKR_CLIP_CTL:
 560         case WSA881X_SPKR_BBM_CTL:
 561         case WSA881X_SPKR_MISC_CTL1:
 562         case WSA881X_SPKR_MISC_CTL2:
 563         case WSA881X_SPKR_BIAS_INT:
 564         case WSA881X_SPKR_PA_INT:
 565         case WSA881X_SPKR_BIAS_CAL:
 566         case WSA881X_SPKR_BIAS_PSRR:
 567         case WSA881X_SPKR_STATUS1:
 568         case WSA881X_SPKR_STATUS2:
 569         case WSA881X_BOOST_EN_CTL:
 570         case WSA881X_BOOST_CURRENT_LIMIT:
 571         case WSA881X_BOOST_PS_CTL:
 572         case WSA881X_BOOST_PRESET_OUT1:
 573         case WSA881X_BOOST_PRESET_OUT2:
 574         case WSA881X_BOOST_FORCE_OUT:
 575         case WSA881X_BOOST_LDO_PROG:
 576         case WSA881X_BOOST_SLOPE_COMP_ISENSE_FB:
 577         case WSA881X_BOOST_RON_CTL:
 578         case WSA881X_BOOST_LOOP_STABILITY:
 579         case WSA881X_BOOST_ZX_CTL:
 580         case WSA881X_BOOST_START_CTL:
 581         case WSA881X_BOOST_MISC1_CTL:
 582         case WSA881X_BOOST_MISC2_CTL:
 583         case WSA881X_BOOST_MISC3_CTL:
 584         case WSA881X_BOOST_ATEST_CTL:
 585         case WSA881X_SPKR_PROT_FE_GAIN:
 586         case WSA881X_SPKR_PROT_FE_CM_LDO_SET:
 587         case WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1:
 588         case WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2:
 589         case WSA881X_SPKR_PROT_ATEST1:
 590         case WSA881X_SPKR_PROT_ATEST2:
 591         case WSA881X_SPKR_PROT_FE_VSENSE_VCM:
 592         case WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1:
 593         case WSA881X_BONGO_RESRV_REG1:
 594         case WSA881X_BONGO_RESRV_REG2:
 595         case WSA881X_SPKR_PROT_SAR:
 596         case WSA881X_SPKR_STATUS3:
 597                 return true;
 598         default:
 599                 return false;
 600         }
 601 }
 602
 603 static bool wsa881x_volatile_register(struct device *dev, unsigned int reg)
 604 {
 605         switch (reg) {
 606         case WSA881X_CHIP_ID0:
 607         case WSA881X_CHIP_ID1:
 608         case WSA881X_CHIP_ID2:
 609         case WSA881X_CHIP_ID3:
 610         case WSA881X_BUS_ID:
 611         case WSA881X_TEMP_MSB:
 612         case WSA881X_TEMP_LSB:
 613         case WSA881X_SDM_PDM9_LSB:
 614         case WSA881X_SDM_PDM9_MSB:
 615         case WSA881X_OTP_CTRL1:
 616         case WSA881X_INTR_STATUS:
 617         case WSA881X_ATE_TEST_MODE:
 618         case WSA881X_PIN_STATUS:
 619         case WSA881X_SWR_HM_TEST2:
 620         case WSA881X_SPKR_STATUS1:
 621         case WSA881X_SPKR_STATUS2:
 622         case WSA881X_SPKR_STATUS3:
 623         case WSA881X_OTP_REG_0:
 624         case WSA881X_OTP_REG_1:
 625         case WSA881X_OTP_REG_2:
 626         case WSA881X_OTP_REG_3:
 627         case WSA881X_OTP_REG_4:
 628         case WSA881X_OTP_REG_5:
 629         case WSA881X_OTP_REG_31:
 630         case WSA881X_TEMP_DOUT_MSB:
 631         case WSA881X_TEMP_DOUT_LSB:
 632         case WSA881X_TEMP_OP:
 633         case WSA881X_SPKR_PROT_SAR:
 634                 return true;
 635         default:
 636                 return false;
 637         }
 638 }
 639
 640 static struct regmap_config wsa881x_regmap_config = {
 641         .reg_bits = 32,
 642         .val_bits = 8,
 643         .cache_type = REGCACHE_RBTREE,
 644         .reg_defaults = wsa881x_defaults,
 645         .max_register = WSA881X_SPKR_STATUS3,
 646         .num_reg_defaults = ARRAY_SIZE(wsa881x_defaults),
 647         .volatile_reg = wsa881x_volatile_register,
 648         .readable_reg = wsa881x_readable_register,
 649         .reg_format_endian = REGMAP_ENDIAN_NATIVE,
 650         .val_format_endian = REGMAP_ENDIAN_NATIVE,
 651         .can_multi_write = true,
 652 };
 653
 654 enum {
 655         G_18DB = 0,
 656         G_16P5DB,
 657         G_15DB,
 658         G_13P5DB,
 659         G_12DB,
 660         G_10P5DB,
 661         G_9DB,
 662         G_7P5DB,
 663         G_6DB,
 664         G_4P5DB,
 665         G_3DB,
 666         G_1P5DB,
 667         G_0DB,
 668 };
 669
 670 /*
 671  * Private data Structure for wsa881x. All parameters related to
 672  * WSA881X codec needs to be defined here.
 673  */
 674 struct wsa881x_priv {
 675         struct regmap *regmap;
 676         struct device *dev;
 677         struct sdw_slave *slave;
 678         struct sdw_stream_config sconfig;
 679         struct sdw_stream_runtime *sruntime;
 680         struct sdw_port_config port_config[WSA881X_MAX_SWR_PORTS];
 681         struct gpio_desc *sd_n;
 682         int version;
 683         int active_ports;
 684         bool port_prepared[WSA881X_MAX_SWR_PORTS];
 685         bool port_enable[WSA881X_MAX_SWR_PORTS];
 686 };
 687
 688 static void wsa881x_init(struct wsa881x_priv *wsa881x)
 689 {
 690         struct regmap *rm = wsa881x->regmap;
 691         unsigned int val = 0;
 692
 693         regmap_read(rm, WSA881X_CHIP_ID1, &wsa881x->version);
 694         regmap_register_patch(wsa881x->regmap, wsa881x_rev_2_0,
 695                               ARRAY_SIZE(wsa881x_rev_2_0));
 696
 697         /* Enable software reset output from soundwire slave */
 698         regmap_update_bits(rm, WSA881X_SWR_RESET_EN, 0x07, 0x07);
 699
 700         /* Bring out of analog reset */
 701         regmap_update_bits(rm, WSA881X_CDC_RST_CTL, 0x02, 0x02);
 702
 703         /* Bring out of digital reset */
 704         regmap_update_bits(rm, WSA881X_CDC_RST_CTL, 0x01, 0x01);
 705         regmap_update_bits(rm, WSA881X_CLOCK_CONFIG, 0x10, 0x10);
 706         regmap_update_bits(rm, WSA881X_SPKR_OCP_CTL, 0x02, 0x02);
 707         regmap_update_bits(rm, WSA881X_SPKR_MISC_CTL1, 0xC0, 0x80);
 708         regmap_update_bits(rm, WSA881X_SPKR_MISC_CTL1, 0x06, 0x06);
 709         regmap_update_bits(rm, WSA881X_SPKR_BIAS_INT, 0xFF, 0x00);
 710         regmap_update_bits(rm, WSA881X_SPKR_PA_INT, 0xF0, 0x40);
 711         regmap_update_bits(rm, WSA881X_SPKR_PA_INT, 0x0E, 0x0E);
 712         regmap_update_bits(rm, WSA881X_BOOST_LOOP_STABILITY, 0x03, 0x03);
 713         regmap_update_bits(rm, WSA881X_BOOST_MISC2_CTL, 0xFF, 0x14);
 714         regmap_update_bits(rm, WSA881X_BOOST_START_CTL, 0x80, 0x80);
 715         regmap_update_bits(rm, WSA881X_BOOST_START_CTL, 0x03, 0x00);
 716         regmap_update_bits(rm, WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x0C, 0x04);
 717         regmap_update_bits(rm, WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x03, 0x00);
 718
 719         regmap_read(rm, WSA881X_OTP_REG_0, &val);
 720         if (val)
 721                 regmap_update_bits(rm, WSA881X_BOOST_PRESET_OUT1, 0xF0, 0x70);
 722
 723         regmap_update_bits(rm, WSA881X_BOOST_PRESET_OUT2, 0xF0, 0x30);
 724         regmap_update_bits(rm, WSA881X_SPKR_DRV_EN, 0x08, 0x08);
 725         regmap_update_bits(rm, WSA881X_BOOST_CURRENT_LIMIT, 0x0F, 0x08);
 726         regmap_update_bits(rm, WSA881X_SPKR_OCP_CTL, 0x30, 0x30);
 727         regmap_update_bits(rm, WSA881X_SPKR_OCP_CTL, 0x0C, 0x00);
 728         regmap_update_bits(rm, WSA881X_OTP_REG_28, 0x3F, 0x3A);
 729         regmap_update_bits(rm, WSA881X_BONGO_RESRV_REG1, 0xFF, 0xB2);
 730         regmap_update_bits(rm, WSA881X_BONGO_RESRV_REG2, 0xFF, 0x05);
 731 }
 732
 733 static int wsa881x_component_probe(struct snd_soc_component *comp)
 734 {
 735         struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);
 736
 737         snd_soc_component_init_regmap(comp, wsa881x->regmap);
 738
 739         return 0;
 740 }
 741
 742 static int wsa881x_put_pa_gain(struct snd_kcontrol *kc,
 743                                struct snd_ctl_elem_value *ucontrol)
 744 {
 745         struct snd_soc_component *comp = snd_soc_kcontrol_component(kc);
 746         struct soc_mixer_control *mc =
 747                         (struct soc_mixer_control *)kc->private_value;
 748         int max = mc->max;
 749         unsigned int mask = (1 << fls(max)) - 1;
 750         int val, ret, min_gain, max_gain;
 751
 752         ret = pm_runtime_get_sync(comp->dev);
 753         if (ret < 0 && ret != -EACCES) {
 754                 pm_runtime_put_noidle(comp->dev);
 755                 return ret;
 756         }
 757
 758         max_gain = (max - ucontrol->value.integer.value[0]) & mask;
 759         /*
 760          * Gain has to set incrementally in 4 steps
 761          * as per HW sequence
 762          */
 763         if (max_gain > G_4P5DB)
 764                 min_gain = G_0DB;
 765         else
 766                 min_gain = max_gain + 3;
 767         /*
 768          * 1ms delay is needed before change in gain
 769          * as per HW requirement.
 770          */
 771         usleep_range(1000, 1010);
 772
 773         for (val = min_gain; max_gain <= val; val--) {
 774                 ret = snd_soc_component_update_bits(comp,
 775                               WSA881X_SPKR_DRV_GAIN,
 776                               WSA881X_SPKR_PAG_GAIN_MASK,
 777                               val << 4);
 778                 if (ret < 0)
 779                         dev_err(comp->dev, "Failed to change PA gain");
 780
 781                 usleep_range(1000, 1010);
 782         }
 783
 784         pm_runtime_mark_last_busy(comp->dev);
 785         pm_runtime_put_autosuspend(comp->dev);
 786
 787         return 1;
 788 }
 789
 790 static int wsa881x_get_port(struct snd_kcontrol *kcontrol,
 791                             struct snd_ctl_elem_value *ucontrol)
 792 {
 793         struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
 794         struct wsa881x_priv *data = snd_soc_component_get_drvdata(comp);
 795         struct soc_mixer_control *mixer =
 796                 (struct soc_mixer_control *)kcontrol->private_value;
 797         int portidx = mixer->reg;
 798
 799         ucontrol->value.integer.value[0] = data->port_enable[portidx];
 800
 801
 802         return 0;
 803 }
 804
 805 static int wsa881x_boost_ctrl(struct snd_soc_component *comp, bool enable)
 806 {
 807         if (enable)
 808                 snd_soc_component_update_bits(comp, WSA881X_BOOST_EN_CTL,
 809                                               WSA881X_BOOST_EN_MASK,
 810                                               WSA881X_BOOST_EN);
 811         else
 812                 snd_soc_component_update_bits(comp, WSA881X_BOOST_EN_CTL,
 813                                               WSA881X_BOOST_EN_MASK, 0);
 814         /*
 815          * 1.5ms sleep is needed after boost enable/disable as per
 816          * HW requirement
 817          */
 818         usleep_range(1500, 1510);
 819         return 0;
 820 }
 821
 822 static int wsa881x_set_port(struct snd_kcontrol *kcontrol,
 823                             struct snd_ctl_elem_value *ucontrol)
 824 {
 825         struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
 826         struct wsa881x_priv *data = snd_soc_component_get_drvdata(comp);
 827         struct soc_mixer_control *mixer =
 828                 (struct soc_mixer_control *)kcontrol->private_value;
 829         int portidx = mixer->reg;
 830
 831         if (ucontrol->value.integer.value[0]) {
 832                 if (data->port_enable[portidx])
 833                         return 0;
 834
 835                 data->port_enable[portidx] = true;
 836         } else {
 837                 if (!data->port_enable[portidx])
 838                         return 0;
 839
 840                 data->port_enable[portidx] = false;
 841         }
 842
 843         if (portidx == WSA881X_PORT_BOOST) /* Boost Switch */
 844                 wsa881x_boost_ctrl(comp, data->port_enable[portidx]);
 845
 846         return 1;
 847 }
 848
 849 static const char * const smart_boost_lvl_text[] = {
 850         "6.625 V", "6.750 V", "6.875 V", "7.000 V",
 851         "7.125 V", "7.250 V", "7.375 V", "7.500 V",
 852         "7.625 V", "7.750 V", "7.875 V", "8.000 V",
 853         "8.125 V", "8.250 V", "8.375 V", "8.500 V"
 854 };
 855
 856 static const struct soc_enum smart_boost_lvl_enum =
 857         SOC_ENUM_SINGLE(WSA881X_BOOST_PRESET_OUT1, 0,
 858                         ARRAY_SIZE(smart_boost_lvl_text),
 859                         smart_boost_lvl_text);
 860
 861 static const DECLARE_TLV_DB_SCALE(pa_gain, 0, 150, 0);
 862
 863 static const struct snd_kcontrol_new wsa881x_snd_controls[] = {
 864         SOC_ENUM("Smart Boost Level", smart_boost_lvl_enum),
 865         WSA881X_PA_GAIN_TLV("PA Volume", WSA881X_SPKR_DRV_GAIN,
 866                             4, 0xC, 1, pa_gain),
 867         SOC_SINGLE_EXT("DAC Switch", WSA881X_PORT_DAC, 0, 1, 0,
 868                        wsa881x_get_port, wsa881x_set_port),
 869         SOC_SINGLE_EXT("COMP Switch", WSA881X_PORT_COMP, 0, 1, 0,
 870                        wsa881x_get_port, wsa881x_set_port),
 871         SOC_SINGLE_EXT("BOOST Switch", WSA881X_PORT_BOOST, 0, 1, 0,
 872                        wsa881x_get_port, wsa881x_set_port),
 873         SOC_SINGLE_EXT("VISENSE Switch", WSA881X_PORT_VISENSE, 0, 1, 0,
 874                        wsa881x_get_port, wsa881x_set_port),
 875 };
 876
 877 static const struct snd_soc_dapm_route wsa881x_audio_map[] = {
 878         { "RDAC", NULL, "IN" },
 879         { "RDAC", NULL, "DCLK" },
 880         { "RDAC", NULL, "ACLK" },
 881         { "RDAC", NULL, "Bandgap" },
 882         { "SPKR PGA", NULL, "RDAC" },
 883         { "SPKR", NULL, "SPKR PGA" },
 884 };
 885
 886 static int wsa881x_visense_txfe_ctrl(struct snd_soc_component *comp,
 887                                      bool enable)
 888 {
 889         struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);
 890
 891         if (enable) {
 892                 regmap_multi_reg_write(wsa881x->regmap, wsa881x_vi_txfe_en_2_0,
 893                                        ARRAY_SIZE(wsa881x_vi_txfe_en_2_0));
 894         } else {
 895                 snd_soc_component_update_bits(comp,
 896                                               WSA881X_SPKR_PROT_FE_VSENSE_VCM,
 897                                               0x08, 0x08);
 898                 /*
 899                  * 200us sleep is needed after visense txfe disable as per
 900                  * HW requirement.
 901                  */
 902                 usleep_range(200, 210);
 903                 snd_soc_component_update_bits(comp, WSA881X_SPKR_PROT_FE_GAIN,
 904                                               0x01, 0x00);
 905         }
 906         return 0;
 907 }
 908
 909 static int wsa881x_visense_adc_ctrl(struct snd_soc_component *comp,
 910                                     bool enable)
 911 {
 912         snd_soc_component_update_bits(comp, WSA881X_ADC_EN_MODU_V, BIT(7),
 913                                       (enable << 7));
 914         snd_soc_component_update_bits(comp, WSA881X_ADC_EN_MODU_I, BIT(7),
 915                                       (enable << 7));
 916         return 0;
 917 }
 918
 919 static int wsa881x_spkr_pa_event(struct snd_soc_dapm_widget *w,
 920                                  struct snd_kcontrol *kcontrol, int event)
 921 {
 922         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
 923         struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);
 924
 925         switch (event) {
 926         case SND_SOC_DAPM_PRE_PMU:
 927                 snd_soc_component_update_bits(comp, WSA881X_SPKR_OCP_CTL,
 928                                               WSA881X_SPKR_OCP_MASK,
 929                                               WSA881X_SPKR_OCP_EN);
 930                 regmap_multi_reg_write(wsa881x->regmap, wsa881x_pre_pmu_pa_2_0,
 931                                        ARRAY_SIZE(wsa881x_pre_pmu_pa_2_0));
 932
 933                 snd_soc_component_update_bits(comp, WSA881X_SPKR_DRV_GAIN,
 934                                               WSA881X_PA_GAIN_SEL_MASK,
 935                                               WSA881X_PA_GAIN_SEL_REG);
 936                 break;
 937         case SND_SOC_DAPM_POST_PMU:
 938                 if (wsa881x->port_prepared[WSA881X_PORT_VISENSE]) {
 939                         wsa881x_visense_txfe_ctrl(comp, true);
 940                         snd_soc_component_update_bits(comp,
 941                                                       WSA881X_ADC_EN_SEL_IBAIS,
 942                                                       0x07, 0x01);
 943                         wsa881x_visense_adc_ctrl(comp, true);
 944                 }
 945
 946                 break;
 947         case SND_SOC_DAPM_POST_PMD:
 948                 if (wsa881x->port_prepared[WSA881X_PORT_VISENSE]) {
 949                         wsa881x_visense_adc_ctrl(comp, false);
 950                         wsa881x_visense_txfe_ctrl(comp, false);
 951                 }
 952
 953                 snd_soc_component_update_bits(comp, WSA881X_SPKR_OCP_CTL,
 954                                               WSA881X_SPKR_OCP_MASK,
 955                                               WSA881X_SPKR_OCP_EN |
 956                                               WSA881X_SPKR_OCP_HOLD);
 957                 break;
 958         }
 959         return 0;
 960 }
 961
 962 static const struct snd_soc_dapm_widget wsa881x_dapm_widgets[] = {
 963         SND_SOC_DAPM_INPUT("IN"),
 964         SND_SOC_DAPM_DAC_E("RDAC", NULL, WSA881X_SPKR_DAC_CTL, 7, 0,
 965                            NULL,
 966                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 967         SND_SOC_DAPM_PGA_E("SPKR PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
 968                            wsa881x_spkr_pa_event, SND_SOC_DAPM_PRE_PMU |
 969                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 970         SND_SOC_DAPM_SUPPLY("DCLK", WSA881X_CDC_DIG_CLK_CTL, 0, 0, NULL,
 971                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 972         SND_SOC_DAPM_SUPPLY("ACLK", WSA881X_CDC_ANA_CLK_CTL, 0, 0, NULL,
 973                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 974         SND_SOC_DAPM_SUPPLY("Bandgap", WSA881X_TEMP_OP, 3, 0,
 975                             NULL,
 976                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 977         SND_SOC_DAPM_OUTPUT("SPKR"),
 978 };
 979
 980 static int wsa881x_hw_params(struct snd_pcm_substream *substream,
 981                              struct snd_pcm_hw_params *params,
 982                              struct snd_soc_dai *dai)
 983 {
 984         struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);
 985         int i;
 986
 987         wsa881x->active_ports = 0;
 988         for (i = 0; i < WSA881X_MAX_SWR_PORTS; i++) {
 989                 if (!wsa881x->port_enable[i])
 990                         continue;
 991
 992                 wsa881x->port_config[wsa881x->active_ports] =
 993                                                         wsa881x_pconfig[i];
 994                 wsa881x->active_ports++;
 995         }
 996
 997         return sdw_stream_add_slave(wsa881x->slave, &wsa881x->sconfig,
 998                                     wsa881x->port_config, wsa881x->active_ports,
 999                                     wsa881x->sruntime);
1000 }
1001
1002 static int wsa881x_hw_free(struct snd_pcm_substream *substream,
1003                            struct snd_soc_dai *dai)
1004 {
1005         struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);
1006
1007         sdw_stream_remove_slave(wsa881x->slave, wsa881x->sruntime);
1008
1009         return 0;
1010 }
1011
1012 static int wsa881x_set_sdw_stream(struct snd_soc_dai *dai,
1013                                   void *stream, int direction)
1014 {
1015         struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);
1016
1017         wsa881x->sruntime = stream;
1018
1019         return 0;
1020 }
1021
1022 static int wsa881x_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
1023 {
1024         struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);
1025
1026         if (mute)
1027                 regmap_update_bits(wsa881x->regmap, WSA881X_SPKR_DRV_EN, 0x80,
1028                                    0x00);
1029         else
1030                 regmap_update_bits(wsa881x->regmap, WSA881X_SPKR_DRV_EN, 0x80,
1031                                    0x80);
1032
1033         return 0;
1034 }
1035
1036 static const struct snd_soc_dai_ops wsa881x_dai_ops = {
1037         .hw_params = wsa881x_hw_params,
1038         .hw_free = wsa881x_hw_free,
1039         .mute_stream = wsa881x_digital_mute,
1040         .set_stream = wsa881x_set_sdw_stream,
1041 };
1042
1043 static struct snd_soc_dai_driver wsa881x_dais[] = {
1044         {
1045                 .name = "SPKR",
1046                 .id = 0,
1047                 .playback = {
1048                         .stream_name = "SPKR Playback",
1049                         .rates = SNDRV_PCM_RATE_48000,
1050                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
1051                         .rate_max = 48000,
1052                         .rate_min = 48000,
1053                         .channels_min = 1,
1054                         .channels_max = 1,
1055                 },
1056                 .ops = &wsa881x_dai_ops,
1057         },
1058 };
1059
1060 static const struct snd_soc_component_driver wsa881x_component_drv = {
1061         .name = "WSA881x",
1062         .probe = wsa881x_component_probe,
1063         .controls = wsa881x_snd_controls,
1064         .num_controls = ARRAY_SIZE(wsa881x_snd_controls),
1065         .dapm_widgets = wsa881x_dapm_widgets,
1066         .num_dapm_widgets = ARRAY_SIZE(wsa881x_dapm_widgets),
1067         .dapm_routes = wsa881x_audio_map,
1068         .num_dapm_routes = ARRAY_SIZE(wsa881x_audio_map),
1069 };
1070
1071 static int wsa881x_update_status(struct sdw_slave *slave,
1072                                  enum sdw_slave_status status)
1073 {
1074         struct wsa881x_priv *wsa881x = dev_get_drvdata(&slave->dev);
1075
1076         if (status == SDW_SLAVE_ATTACHED && slave->dev_num > 0)
1077                 wsa881x_init(wsa881x);
1078
1079         return 0;
1080 }
1081
1082 static int wsa881x_port_prep(struct sdw_slave *slave,
1083                              struct sdw_prepare_ch *prepare_ch,
1084                              enum sdw_port_prep_ops state)
1085 {
1086         struct wsa881x_priv *wsa881x = dev_get_drvdata(&slave->dev);
1087
1088         if (state == SDW_OPS_PORT_POST_PREP)
1089                 wsa881x->port_prepared[prepare_ch->num - 1] = true;
1090         else
1091                 wsa881x->port_prepared[prepare_ch->num - 1] = false;
1092
1093         return 0;
1094 }
1095
1096 static int wsa881x_bus_config(struct sdw_slave *slave,
1097                               struct sdw_bus_params *params)
1098 {
1099         sdw_write(slave, SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(params->next_bank),
1100                   0x01);
1101
1102         return 0;
1103 }
1104
1105 static struct sdw_slave_ops wsa881x_slave_ops = {
1106         .update_status = wsa881x_update_status,
1107         .bus_config = wsa881x_bus_config,
1108         .port_prep = wsa881x_port_prep,
1109 };
1110
1111 static int wsa881x_probe(struct sdw_slave *pdev,
1112                          const struct sdw_device_id *id)
1113 {
1114         struct wsa881x_priv *wsa881x;
1115         struct device *dev = &pdev->dev;
1116
1117         wsa881x = devm_kzalloc(&pdev->dev, sizeof(*wsa881x), GFP_KERNEL);
1118         if (!wsa881x)
1119                 return -ENOMEM;
1120
1121         wsa881x->sd_n = devm_gpiod_get_optional(&pdev->dev, "powerdown",
1122                                                 GPIOD_FLAGS_BIT_NONEXCLUSIVE);
1123         if (IS_ERR(wsa881x->sd_n)) {
1124                 dev_err(&pdev->dev, "Shutdown Control GPIO not found\n");
1125                 return PTR_ERR(wsa881x->sd_n);
1126         }
1127
1128         dev_set_drvdata(&pdev->dev, wsa881x);
1129         wsa881x->slave = pdev;
1130         wsa881x->dev = &pdev->dev;
1131         wsa881x->sconfig.ch_count = 1;
1132         wsa881x->sconfig.bps = 1;
1133         wsa881x->sconfig.frame_rate = 48000;
1134         wsa881x->sconfig.direction = SDW_DATA_DIR_RX;
1135         wsa881x->sconfig.type = SDW_STREAM_PDM;
1136         pdev->prop.sink_ports = GENMASK(WSA881X_MAX_SWR_PORTS, 0);
1137         pdev->prop.sink_dpn_prop = wsa_sink_dpn_prop;
1138         pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
1139         gpiod_direction_output(wsa881x->sd_n, 1);
1140
1141         wsa881x->regmap = devm_regmap_init_sdw(pdev, &wsa881x_regmap_config);
1142         if (IS_ERR(wsa881x->regmap)) {
1143                 dev_err(&pdev->dev, "regmap_init failed\n");
1144                 return PTR_ERR(wsa881x->regmap);
1145         }
1146
1147         pm_runtime_set_autosuspend_delay(dev, 3000);
1148         pm_runtime_use_autosuspend(dev);
1149         pm_runtime_mark_last_busy(dev);
1150         pm_runtime_set_active(dev);
1151         pm_runtime_enable(dev);
1152
1153         return devm_snd_soc_register_component(&pdev->dev,
1154                                                &wsa881x_component_drv,
1155                                                wsa881x_dais,
1156                                                ARRAY_SIZE(wsa881x_dais));
1157 }
1158
1159 static int __maybe_unused wsa881x_runtime_suspend(struct device *dev)
1160 {
1161         struct regmap *regmap = dev_get_regmap(dev, NULL);
1162         struct wsa881x_priv *wsa881x = dev_get_drvdata(dev);
1163
1164         gpiod_direction_output(wsa881x->sd_n, 0);
1165
1166         regcache_cache_only(regmap, true);
1167         regcache_mark_dirty(regmap);
1168
1169         return 0;
1170 }
1171
1172 static int __maybe_unused wsa881x_runtime_resume(struct device *dev)
1173 {
1174         struct sdw_slave *slave = dev_to_sdw_dev(dev);
1175         struct regmap *regmap = dev_get_regmap(dev, NULL);
1176         struct wsa881x_priv *wsa881x = dev_get_drvdata(dev);
1177
1178         gpiod_direction_output(wsa881x->sd_n, 1);
1179
1180         wait_for_completion_timeout(&slave->initialization_complete,
1181                                     msecs_to_jiffies(WSA881X_PROBE_TIMEOUT));
1182
1183         regcache_cache_only(regmap, false);
1184         regcache_sync(regmap);
1185
1186         return 0;
1187 }
1188
1189 static const struct dev_pm_ops wsa881x_pm_ops = {
1190         SET_RUNTIME_PM_OPS(wsa881x_runtime_suspend, wsa881x_runtime_resume, NULL)
1191 };
1192
1193 static const struct sdw_device_id wsa881x_slave_id[] = {
1194         SDW_SLAVE_ENTRY(0x0217, 0x2010, 0),
1195         SDW_SLAVE_ENTRY(0x0217, 0x2110, 0),
1196         {},
1197 };
1198 MODULE_DEVICE_TABLE(sdw, wsa881x_slave_id);
1199
1200 static struct sdw_driver wsa881x_codec_driver = {
1201         .probe  = wsa881x_probe,
1202         .ops = &wsa881x_slave_ops,
1203         .id_table = wsa881x_slave_id,
1204         .driver = {
1205                 .name   = "wsa881x-codec",
1206                 .pm = &wsa881x_pm_ops,
1207         }
1208 };
1209 module_sdw_driver(wsa881x_codec_driver);
1210
1211 MODULE_DESCRIPTION("WSA881x codec driver");
1212 MODULE_LICENSE("GPL v2");