sound/soc/codecs/wm_adsp.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * wm_adsp.c  --  Wolfson ADSP support
   4  *
   5  * Copyright 2012 Wolfson Microelectronics plc
   6  *
   7  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   8  */
   9
  10 #include <linux/ctype.h>
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/init.h>
  14 #include <linux/delay.h>
  15 #include <linux/firmware.h>
  16 #include <linux/list.h>
  17 #include <linux/pm.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/regmap.h>
  20 #include <linux/regulator/consumer.h>
  21 #include <linux/slab.h>
  22 #include <linux/vmalloc.h>
  23 #include <linux/workqueue.h>
  24 #include <linux/debugfs.h>
  25 #include <sound/core.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/jack.h>
  30 #include <sound/initval.h>
  31 #include <sound/tlv.h>
  32
  33 #include "wm_adsp.h"
  34
  35 #define adsp_crit(_dsp, fmt, ...) \
  36         dev_crit(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
  37 #define adsp_err(_dsp, fmt, ...) \
  38         dev_err(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
  39 #define adsp_warn(_dsp, fmt, ...) \
  40         dev_warn(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
  41 #define adsp_info(_dsp, fmt, ...) \
  42         dev_info(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
  43 #define adsp_dbg(_dsp, fmt, ...) \
  44         dev_dbg(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
  45
  46 #define compr_err(_obj, fmt, ...) \
  47         adsp_err(_obj->dsp, "%s: " fmt, _obj->name ? _obj->name : "legacy", \
  48                  ##__VA_ARGS__)
  49 #define compr_dbg(_obj, fmt, ...) \
  50         adsp_dbg(_obj->dsp, "%s: " fmt, _obj->name ? _obj->name : "legacy", \
  51                  ##__VA_ARGS__)
  52
  53 #define ADSP1_CONTROL_1                   0x00
  54 #define ADSP1_CONTROL_2                   0x02
  55 #define ADSP1_CONTROL_3                   0x03
  56 #define ADSP1_CONTROL_4                   0x04
  57 #define ADSP1_CONTROL_5                   0x06
  58 #define ADSP1_CONTROL_6                   0x07
  59 #define ADSP1_CONTROL_7                   0x08
  60 #define ADSP1_CONTROL_8                   0x09
  61 #define ADSP1_CONTROL_9                   0x0A
  62 #define ADSP1_CONTROL_10                  0x0B
  63 #define ADSP1_CONTROL_11                  0x0C
  64 #define ADSP1_CONTROL_12                  0x0D
  65 #define ADSP1_CONTROL_13                  0x0F
  66 #define ADSP1_CONTROL_14                  0x10
  67 #define ADSP1_CONTROL_15                  0x11
  68 #define ADSP1_CONTROL_16                  0x12
  69 #define ADSP1_CONTROL_17                  0x13
  70 #define ADSP1_CONTROL_18                  0x14
  71 #define ADSP1_CONTROL_19                  0x16
  72 #define ADSP1_CONTROL_20                  0x17
  73 #define ADSP1_CONTROL_21                  0x18
  74 #define ADSP1_CONTROL_22                  0x1A
  75 #define ADSP1_CONTROL_23                  0x1B
  76 #define ADSP1_CONTROL_24                  0x1C
  77 #define ADSP1_CONTROL_25                  0x1E
  78 #define ADSP1_CONTROL_26                  0x20
  79 #define ADSP1_CONTROL_27                  0x21
  80 #define ADSP1_CONTROL_28                  0x22
  81 #define ADSP1_CONTROL_29                  0x23
  82 #define ADSP1_CONTROL_30                  0x24
  83 #define ADSP1_CONTROL_31                  0x26
  84
  85 /*
  86  * ADSP1 Control 19
  87  */
  88 #define ADSP1_WDMA_BUFFER_LENGTH_MASK     0x00FF  /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
  89 #define ADSP1_WDMA_BUFFER_LENGTH_SHIFT         0  /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
  90 #define ADSP1_WDMA_BUFFER_LENGTH_WIDTH         8  /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
  91
  92
  93 /*
  94  * ADSP1 Control 30
  95  */
  96 #define ADSP1_DBG_CLK_ENA                 0x0008  /* DSP1_DBG_CLK_ENA */
  97 #define ADSP1_DBG_CLK_ENA_MASK            0x0008  /* DSP1_DBG_CLK_ENA */
  98 #define ADSP1_DBG_CLK_ENA_SHIFT                3  /* DSP1_DBG_CLK_ENA */
  99 #define ADSP1_DBG_CLK_ENA_WIDTH                1  /* DSP1_DBG_CLK_ENA */
 100 #define ADSP1_SYS_ENA                     0x0004  /* DSP1_SYS_ENA */
 101 #define ADSP1_SYS_ENA_MASK                0x0004  /* DSP1_SYS_ENA */
 102 #define ADSP1_SYS_ENA_SHIFT                    2  /* DSP1_SYS_ENA */
 103 #define ADSP1_SYS_ENA_WIDTH                    1  /* DSP1_SYS_ENA */
 104 #define ADSP1_CORE_ENA                    0x0002  /* DSP1_CORE_ENA */
 105 #define ADSP1_CORE_ENA_MASK               0x0002  /* DSP1_CORE_ENA */
 106 #define ADSP1_CORE_ENA_SHIFT                   1  /* DSP1_CORE_ENA */
 107 #define ADSP1_CORE_ENA_WIDTH                   1  /* DSP1_CORE_ENA */
 108 #define ADSP1_START                       0x0001  /* DSP1_START */
 109 #define ADSP1_START_MASK                  0x0001  /* DSP1_START */
 110 #define ADSP1_START_SHIFT                      0  /* DSP1_START */
 111 #define ADSP1_START_WIDTH                      1  /* DSP1_START */
 112
 113 /*
 114  * ADSP1 Control 31
 115  */
 116 #define ADSP1_CLK_SEL_MASK                0x0007  /* CLK_SEL_ENA */
 117 #define ADSP1_CLK_SEL_SHIFT                    0  /* CLK_SEL_ENA */
 118 #define ADSP1_CLK_SEL_WIDTH                    3  /* CLK_SEL_ENA */
 119
 120 #define ADSP2_CONTROL                     0x0
 121 #define ADSP2_CLOCKING                    0x1
 122 #define ADSP2V2_CLOCKING                  0x2
 123 #define ADSP2_STATUS1                     0x4
 124 #define ADSP2_WDMA_CONFIG_1               0x30
 125 #define ADSP2_WDMA_CONFIG_2               0x31
 126 #define ADSP2V2_WDMA_CONFIG_2             0x32
 127 #define ADSP2_RDMA_CONFIG_1               0x34
 128
 129 #define ADSP2_SCRATCH0                    0x40
 130 #define ADSP2_SCRATCH1                    0x41
 131 #define ADSP2_SCRATCH2                    0x42
 132 #define ADSP2_SCRATCH3                    0x43
 133
 134 #define ADSP2V2_SCRATCH0_1                0x40
 135 #define ADSP2V2_SCRATCH2_3                0x42
 136
 137 /*
 138  * ADSP2 Control
 139  */
 140
 141 #define ADSP2_MEM_ENA                     0x0010  /* DSP1_MEM_ENA */
 142 #define ADSP2_MEM_ENA_MASK                0x0010  /* DSP1_MEM_ENA */
 143 #define ADSP2_MEM_ENA_SHIFT                    4  /* DSP1_MEM_ENA */
 144 #define ADSP2_MEM_ENA_WIDTH                    1  /* DSP1_MEM_ENA */
 145 #define ADSP2_SYS_ENA                     0x0004  /* DSP1_SYS_ENA */
 146 #define ADSP2_SYS_ENA_MASK                0x0004  /* DSP1_SYS_ENA */
 147 #define ADSP2_SYS_ENA_SHIFT                    2  /* DSP1_SYS_ENA */
 148 #define ADSP2_SYS_ENA_WIDTH                    1  /* DSP1_SYS_ENA */
 149 #define ADSP2_CORE_ENA                    0x0002  /* DSP1_CORE_ENA */
 150 #define ADSP2_CORE_ENA_MASK               0x0002  /* DSP1_CORE_ENA */
 151 #define ADSP2_CORE_ENA_SHIFT                   1  /* DSP1_CORE_ENA */
 152 #define ADSP2_CORE_ENA_WIDTH                   1  /* DSP1_CORE_ENA */
 153 #define ADSP2_START                       0x0001  /* DSP1_START */
 154 #define ADSP2_START_MASK                  0x0001  /* DSP1_START */
 155 #define ADSP2_START_SHIFT                      0  /* DSP1_START */
 156 #define ADSP2_START_WIDTH                      1  /* DSP1_START */
 157
 158 /*
 159  * ADSP2 clocking
 160  */
 161 #define ADSP2_CLK_SEL_MASK                0x0007  /* CLK_SEL_ENA */
 162 #define ADSP2_CLK_SEL_SHIFT                    0  /* CLK_SEL_ENA */
 163 #define ADSP2_CLK_SEL_WIDTH                    3  /* CLK_SEL_ENA */
 164
 165 /*
 166  * ADSP2V2 clocking
 167  */
 168 #define ADSP2V2_CLK_SEL_MASK             0x70000  /* CLK_SEL_ENA */
 169 #define ADSP2V2_CLK_SEL_SHIFT                 16  /* CLK_SEL_ENA */
 170 #define ADSP2V2_CLK_SEL_WIDTH                  3  /* CLK_SEL_ENA */
 171
 172 #define ADSP2V2_RATE_MASK                 0x7800  /* DSP_RATE */
 173 #define ADSP2V2_RATE_SHIFT                    11  /* DSP_RATE */
 174 #define ADSP2V2_RATE_WIDTH                     4  /* DSP_RATE */
 175
 176 /*
 177  * ADSP2 Status 1
 178  */
 179 #define ADSP2_RAM_RDY                     0x0001
 180 #define ADSP2_RAM_RDY_MASK                0x0001
 181 #define ADSP2_RAM_RDY_SHIFT                    0
 182 #define ADSP2_RAM_RDY_WIDTH                    1
 183
 184 /*
 185  * ADSP2 Lock support
 186  */
 187 #define ADSP2_LOCK_CODE_0                    0x5555
 188 #define ADSP2_LOCK_CODE_1                    0xAAAA
 189
 190 #define ADSP2_WATCHDOG                       0x0A
 191 #define ADSP2_BUS_ERR_ADDR                   0x52
 192 #define ADSP2_REGION_LOCK_STATUS             0x64
 193 #define ADSP2_LOCK_REGION_1_LOCK_REGION_0    0x66
 194 #define ADSP2_LOCK_REGION_3_LOCK_REGION_2    0x68
 195 #define ADSP2_LOCK_REGION_5_LOCK_REGION_4    0x6A
 196 #define ADSP2_LOCK_REGION_7_LOCK_REGION_6    0x6C
 197 #define ADSP2_LOCK_REGION_9_LOCK_REGION_8    0x6E
 198 #define ADSP2_LOCK_REGION_CTRL               0x7A
 199 #define ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR    0x7C
 200
 201 #define ADSP2_REGION_LOCK_ERR_MASK           0x8000
 202 #define ADSP2_ADDR_ERR_MASK                  0x4000
 203 #define ADSP2_WDT_TIMEOUT_STS_MASK           0x2000
 204 #define ADSP2_CTRL_ERR_PAUSE_ENA             0x0002
 205 #define ADSP2_CTRL_ERR_EINT                  0x0001
 206
 207 #define ADSP2_BUS_ERR_ADDR_MASK              0x00FFFFFF
 208 #define ADSP2_XMEM_ERR_ADDR_MASK             0x0000FFFF
 209 #define ADSP2_PMEM_ERR_ADDR_MASK             0x7FFF0000
 210 #define ADSP2_PMEM_ERR_ADDR_SHIFT            16
 211 #define ADSP2_WDT_ENA_MASK                   0xFFFFFFFD
 212
 213 #define ADSP2_LOCK_REGION_SHIFT              16
 214
 215 #define ADSP_MAX_STD_CTRL_SIZE               512
 216
 217 #define WM_ADSP_ACKED_CTL_TIMEOUT_MS         100
 218 #define WM_ADSP_ACKED_CTL_N_QUICKPOLLS       10
 219 #define WM_ADSP_ACKED_CTL_MIN_VALUE          0
 220 #define WM_ADSP_ACKED_CTL_MAX_VALUE          0xFFFFFF
 221
 222 /*
 223  * Event control messages
 224  */
 225 #define WM_ADSP_FW_EVENT_SHUTDOWN            0x000001
 226
 227 /*
 228  * HALO system info
 229  */
 230 #define HALO_AHBM_WINDOW_DEBUG_0             0x02040
 231 #define HALO_AHBM_WINDOW_DEBUG_1             0x02044
 232
 233 /*
 234  * HALO core
 235  */
 236 #define HALO_SCRATCH1                        0x005c0
 237 #define HALO_SCRATCH2                        0x005c8
 238 #define HALO_SCRATCH3                        0x005d0
 239 #define HALO_SCRATCH4                        0x005d8
 240 #define HALO_CCM_CORE_CONTROL                0x41000
 241 #define HALO_CORE_SOFT_RESET                 0x00010
 242 #define HALO_WDT_CONTROL                     0x47000
 243
 244 /*
 245  * HALO MPU banks
 246  */
 247 #define HALO_MPU_XMEM_ACCESS_0               0x43000
 248 #define HALO_MPU_YMEM_ACCESS_0               0x43004
 249 #define HALO_MPU_WINDOW_ACCESS_0             0x43008
 250 #define HALO_MPU_XREG_ACCESS_0               0x4300C
 251 #define HALO_MPU_YREG_ACCESS_0               0x43014
 252 #define HALO_MPU_XMEM_ACCESS_1               0x43018
 253 #define HALO_MPU_YMEM_ACCESS_1               0x4301C
 254 #define HALO_MPU_WINDOW_ACCESS_1             0x43020
 255 #define HALO_MPU_XREG_ACCESS_1               0x43024
 256 #define HALO_MPU_YREG_ACCESS_1               0x4302C
 257 #define HALO_MPU_XMEM_ACCESS_2               0x43030
 258 #define HALO_MPU_YMEM_ACCESS_2               0x43034
 259 #define HALO_MPU_WINDOW_ACCESS_2             0x43038
 260 #define HALO_MPU_XREG_ACCESS_2               0x4303C
 261 #define HALO_MPU_YREG_ACCESS_2               0x43044
 262 #define HALO_MPU_XMEM_ACCESS_3               0x43048
 263 #define HALO_MPU_YMEM_ACCESS_3               0x4304C
 264 #define HALO_MPU_WINDOW_ACCESS_3             0x43050
 265 #define HALO_MPU_XREG_ACCESS_3               0x43054
 266 #define HALO_MPU_YREG_ACCESS_3               0x4305C
 267 #define HALO_MPU_XM_VIO_ADDR                 0x43100
 268 #define HALO_MPU_XM_VIO_STATUS               0x43104
 269 #define HALO_MPU_YM_VIO_ADDR                 0x43108
 270 #define HALO_MPU_YM_VIO_STATUS               0x4310C
 271 #define HALO_MPU_PM_VIO_ADDR                 0x43110
 272 #define HALO_MPU_PM_VIO_STATUS               0x43114
 273 #define HALO_MPU_LOCK_CONFIG                 0x43140
 274
 275 /*
 276  * HALO_AHBM_WINDOW_DEBUG_1
 277  */
 278 #define HALO_AHBM_CORE_ERR_ADDR_MASK         0x0fffff00
 279 #define HALO_AHBM_CORE_ERR_ADDR_SHIFT                 8
 280 #define HALO_AHBM_FLAGS_ERR_MASK             0x000000ff
 281
 282 /*
 283  * HALO_CCM_CORE_CONTROL
 284  */
 285 #define HALO_CORE_RESET                     0x00000200
 286 #define HALO_CORE_EN                        0x00000001
 287
 288 /*
 289  * HALO_CORE_SOFT_RESET
 290  */
 291 #define HALO_CORE_SOFT_RESET_MASK           0x00000001
 292
 293 /*
 294  * HALO_WDT_CONTROL
 295  */
 296 #define HALO_WDT_EN_MASK                    0x00000001
 297
 298 /*
 299  * HALO_MPU_?M_VIO_STATUS
 300  */
 301 #define HALO_MPU_VIO_STS_MASK               0x007e0000
 302 #define HALO_MPU_VIO_STS_SHIFT                      17
 303 #define HALO_MPU_VIO_ERR_WR_MASK            0x00008000
 304 #define HALO_MPU_VIO_ERR_SRC_MASK           0x00007fff
 305 #define HALO_MPU_VIO_ERR_SRC_SHIFT                   0
 306
 307 static const struct wm_adsp_ops wm_adsp1_ops;
 308 static const struct wm_adsp_ops wm_adsp2_ops[];
 309 static const struct wm_adsp_ops wm_halo_ops;
 310
 311 struct wm_adsp_buf {
 312         struct list_head list;
 313         void *buf;
 314 };
 315
 316 static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
 317                                              struct list_head *list)
 318 {
 319         struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
 320
 321         if (buf == NULL)
 322                 return NULL;
 323
 324         buf->buf = vmalloc(len);
 325         if (!buf->buf) {
 326                 kfree(buf);
 327                 return NULL;
 328         }
 329         memcpy(buf->buf, src, len);
 330
 331         if (list)
 332                 list_add_tail(&buf->list, list);
 333
 334         return buf;
 335 }
 336
 337 static void wm_adsp_buf_free(struct list_head *list)
 338 {
 339         while (!list_empty(list)) {
 340                 struct wm_adsp_buf *buf = list_first_entry(list,
 341                                                            struct wm_adsp_buf,
 342                                                            list);
 343                 list_del(&buf->list);
 344                 vfree(buf->buf);
 345                 kfree(buf);
 346         }
 347 }
 348
 349 #define WM_ADSP_FW_MBC_VSS  0
 350 #define WM_ADSP_FW_HIFI     1
 351 #define WM_ADSP_FW_TX       2
 352 #define WM_ADSP_FW_TX_SPK   3
 353 #define WM_ADSP_FW_RX       4
 354 #define WM_ADSP_FW_RX_ANC   5
 355 #define WM_ADSP_FW_CTRL     6
 356 #define WM_ADSP_FW_ASR      7
 357 #define WM_ADSP_FW_TRACE    8
 358 #define WM_ADSP_FW_SPK_PROT 9
 359 #define WM_ADSP_FW_SPK_CALI 10
 360 #define WM_ADSP_FW_SPK_DIAG 11
 361 #define WM_ADSP_FW_MISC     12
 362
 363 #define WM_ADSP_NUM_FW      13
 364
 365 static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
 366         [WM_ADSP_FW_MBC_VSS] =  "MBC/VSS",
 367         [WM_ADSP_FW_HIFI] =     "MasterHiFi",
 368         [WM_ADSP_FW_TX] =       "Tx",
 369         [WM_ADSP_FW_TX_SPK] =   "Tx Speaker",
 370         [WM_ADSP_FW_RX] =       "Rx",
 371         [WM_ADSP_FW_RX_ANC] =   "Rx ANC",
 372         [WM_ADSP_FW_CTRL] =     "Voice Ctrl",
 373         [WM_ADSP_FW_ASR] =      "ASR Assist",
 374         [WM_ADSP_FW_TRACE] =    "Dbg Trace",
 375         [WM_ADSP_FW_SPK_PROT] = "Protection",
 376         [WM_ADSP_FW_SPK_CALI] = "Calibration",
 377         [WM_ADSP_FW_SPK_DIAG] = "Diagnostic",
 378         [WM_ADSP_FW_MISC] =     "Misc",
 379 };
 380
 381 struct wm_adsp_system_config_xm_hdr {
 382         __be32 sys_enable;
 383         __be32 fw_id;
 384         __be32 fw_rev;
 385         __be32 boot_status;
 386         __be32 watchdog;
 387         __be32 dma_buffer_size;
 388         __be32 rdma[6];
 389         __be32 wdma[8];
 390         __be32 build_job_name[3];
 391         __be32 build_job_number;
 392 };
 393
 394 struct wm_halo_system_config_xm_hdr {
 395         __be32 halo_heartbeat;
 396         __be32 build_job_name[3];
 397         __be32 build_job_number;
 398 };
 399
 400 struct wm_adsp_alg_xm_struct {
 401         __be32 magic;
 402         __be32 smoothing;
 403         __be32 threshold;
 404         __be32 host_buf_ptr;
 405         __be32 start_seq;
 406         __be32 high_water_mark;
 407         __be32 low_water_mark;
 408         __be64 smoothed_power;
 409 };
 410
 411 struct wm_adsp_host_buf_coeff_v1 {
 412         __be32 host_buf_ptr;            /* Host buffer pointer */
 413         __be32 versions;                /* Version numbers */
 414         __be32 name[4];                 /* The buffer name */
 415 };
 416
 417 struct wm_adsp_buffer {
 418         __be32 buf1_base;               /* Base addr of first buffer area */
 419         __be32 buf1_size;               /* Size of buf1 area in DSP words */
 420         __be32 buf2_base;               /* Base addr of 2nd buffer area */
 421         __be32 buf1_buf2_size;          /* Size of buf1+buf2 in DSP words */
 422         __be32 buf3_base;               /* Base addr of buf3 area */
 423         __be32 buf_total_size;          /* Size of buf1+buf2+buf3 in DSP words */
 424         __be32 high_water_mark;         /* Point at which IRQ is asserted */
 425         __be32 irq_count;               /* bits 1-31 count IRQ assertions */
 426         __be32 irq_ack;                 /* acked IRQ count, bit 0 enables IRQ */
 427         __be32 next_write_index;        /* word index of next write */
 428         __be32 next_read_index;         /* word index of next read */
 429         __be32 error;                   /* error if any */
 430         __be32 oldest_block_index;      /* word index of oldest surviving */
 431         __be32 requested_rewind;        /* how many blocks rewind was done */
 432         __be32 reserved_space;          /* internal */
 433         __be32 min_free;                /* min free space since stream start */
 434         __be32 blocks_written[2];       /* total blocks written (64 bit) */
 435         __be32 words_written[2];        /* total words written (64 bit) */
 436 };
 437
 438 struct wm_adsp_compr;
 439
 440 struct wm_adsp_compr_buf {
 441         struct list_head list;
 442         struct wm_adsp *dsp;
 443         struct wm_adsp_compr *compr;
 444
 445         struct wm_adsp_buffer_region *regions;
 446         u32 host_buf_ptr;
 447
 448         u32 error;
 449         u32 irq_count;
 450         int read_index;
 451         int avail;
 452         int host_buf_mem_type;
 453
 454         char *name;
 455 };
 456
 457 struct wm_adsp_compr {
 458         struct list_head list;
 459         struct wm_adsp *dsp;
 460         struct wm_adsp_compr_buf *buf;
 461
 462         struct snd_compr_stream *stream;
 463         struct snd_compressed_buffer size;
 464
 465         u32 *raw_buf;
 466         unsigned int copied_total;
 467
 468         unsigned int sample_rate;
 469
 470         const char *name;
 471 };
 472
 473 #define WM_ADSP_DATA_WORD_SIZE         3
 474
 475 #define WM_ADSP_MIN_FRAGMENTS          1
 476 #define WM_ADSP_MAX_FRAGMENTS          256
 477 #define WM_ADSP_MIN_FRAGMENT_SIZE      (64 * WM_ADSP_DATA_WORD_SIZE)
 478 #define WM_ADSP_MAX_FRAGMENT_SIZE      (4096 * WM_ADSP_DATA_WORD_SIZE)
 479
 480 #define WM_ADSP_ALG_XM_STRUCT_MAGIC    0x49aec7
 481
 482 #define HOST_BUFFER_FIELD(field) \
 483         (offsetof(struct wm_adsp_buffer, field) / sizeof(__be32))
 484
 485 #define ALG_XM_FIELD(field) \
 486         (offsetof(struct wm_adsp_alg_xm_struct, field) / sizeof(__be32))
 487
 488 #define HOST_BUF_COEFF_SUPPORTED_COMPAT_VER     1
 489
 490 #define HOST_BUF_COEFF_COMPAT_VER_MASK          0xFF00
 491 #define HOST_BUF_COEFF_COMPAT_VER_SHIFT         8
 492
 493 static int wm_adsp_buffer_init(struct wm_adsp *dsp);
 494 static int wm_adsp_buffer_free(struct wm_adsp *dsp);
 495
 496 struct wm_adsp_buffer_region {
 497         unsigned int offset;
 498         unsigned int cumulative_size;
 499         unsigned int mem_type;
 500         unsigned int base_addr;
 501 };
 502
 503 struct wm_adsp_buffer_region_def {
 504         unsigned int mem_type;
 505         unsigned int base_offset;
 506         unsigned int size_offset;
 507 };
 508
 509 static const struct wm_adsp_buffer_region_def default_regions[] = {
 510         {
 511                 .mem_type = WMFW_ADSP2_XM,
 512                 .base_offset = HOST_BUFFER_FIELD(buf1_base),
 513                 .size_offset = HOST_BUFFER_FIELD(buf1_size),
 514         },
 515         {
 516                 .mem_type = WMFW_ADSP2_XM,
 517                 .base_offset = HOST_BUFFER_FIELD(buf2_base),
 518                 .size_offset = HOST_BUFFER_FIELD(buf1_buf2_size),
 519         },
 520         {
 521                 .mem_type = WMFW_ADSP2_YM,
 522                 .base_offset = HOST_BUFFER_FIELD(buf3_base),
 523                 .size_offset = HOST_BUFFER_FIELD(buf_total_size),
 524         },
 525 };
 526
 527 struct wm_adsp_fw_caps {
 528         u32 id;
 529         struct snd_codec_desc desc;
 530         int num_regions;
 531         const struct wm_adsp_buffer_region_def *region_defs;
 532 };
 533
 534 static const struct wm_adsp_fw_caps ctrl_caps[] = {
 535         {
 536                 .id = SND_AUDIOCODEC_BESPOKE,
 537                 .desc = {
 538                         .max_ch = 8,
 539                         .sample_rates = { 16000 },
 540                         .num_sample_rates = 1,
 541                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
 542                 },
 543                 .num_regions = ARRAY_SIZE(default_regions),
 544                 .region_defs = default_regions,
 545         },
 546 };
 547
 548 static const struct wm_adsp_fw_caps trace_caps[] = {
 549         {
 550                 .id = SND_AUDIOCODEC_BESPOKE,
 551                 .desc = {
 552                         .max_ch = 8,
 553                         .sample_rates = {
 554                                 4000, 8000, 11025, 12000, 16000, 22050,
 555                                 24000, 32000, 44100, 48000, 64000, 88200,
 556                                 96000, 176400, 192000
 557                         },
 558                         .num_sample_rates = 15,
 559                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
 560                 },
 561                 .num_regions = ARRAY_SIZE(default_regions),
 562                 .region_defs = default_regions,
 563         },
 564 };
 565
 566 static const struct {
 567         const char *file;
 568         int compr_direction;
 569         int num_caps;
 570         const struct wm_adsp_fw_caps *caps;
 571         bool voice_trigger;
 572 } wm_adsp_fw[WM_ADSP_NUM_FW] = {
 573         [WM_ADSP_FW_MBC_VSS] =  { .file = "mbc-vss" },
 574         [WM_ADSP_FW_HIFI] =     { .file = "hifi" },
 575         [WM_ADSP_FW_TX] =       { .file = "tx" },
 576         [WM_ADSP_FW_TX_SPK] =   { .file = "tx-spk" },
 577         [WM_ADSP_FW_RX] =       { .file = "rx" },
 578         [WM_ADSP_FW_RX_ANC] =   { .file = "rx-anc" },
 579         [WM_ADSP_FW_CTRL] =     {
 580                 .file = "ctrl",
 581                 .compr_direction = SND_COMPRESS_CAPTURE,
 582                 .num_caps = ARRAY_SIZE(ctrl_caps),
 583                 .caps = ctrl_caps,
 584                 .voice_trigger = true,
 585         },
 586         [WM_ADSP_FW_ASR] =      { .file = "asr" },
 587         [WM_ADSP_FW_TRACE] =    {
 588                 .file = "trace",
 589                 .compr_direction = SND_COMPRESS_CAPTURE,
 590                 .num_caps = ARRAY_SIZE(trace_caps),
 591                 .caps = trace_caps,
 592         },
 593         [WM_ADSP_FW_SPK_PROT] = { .file = "spk-prot" },
 594         [WM_ADSP_FW_SPK_CALI] = { .file = "spk-cali" },
 595         [WM_ADSP_FW_SPK_DIAG] = { .file = "spk-diag" },
 596         [WM_ADSP_FW_MISC] =     { .file = "misc" },
 597 };
 598
 599 struct wm_coeff_ctl {
 600         const char *name;
 601         const char *fw_name;
 602         /* Subname is needed to match with firmware */
 603         const char *subname;
 604         unsigned int subname_len;
 605         struct wm_adsp_alg_region alg_region;
 606         struct wm_adsp *dsp;
 607         unsigned int enabled:1;
 608         struct list_head list;
 609         void *cache;
 610         unsigned int offset;
 611         size_t len;
 612         unsigned int set:1;
 613         struct soc_bytes_ext bytes_ext;
 614         unsigned int flags;
 615         unsigned int type;
 616         struct work_struct work;
 617 };
 618
 619 static const char *wm_adsp_mem_region_name(unsigned int type)
 620 {
 621         switch (type) {
 622         case WMFW_ADSP1_PM:
 623                 return "PM";
 624         case WMFW_HALO_PM_PACKED:
 625                 return "PM_PACKED";
 626         case WMFW_ADSP1_DM:
 627                 return "DM";
 628         case WMFW_ADSP2_XM:
 629                 return "XM";
 630         case WMFW_HALO_XM_PACKED:
 631                 return "XM_PACKED";
 632         case WMFW_ADSP2_YM:
 633                 return "YM";
 634         case WMFW_HALO_YM_PACKED:
 635                 return "YM_PACKED";
 636         case WMFW_ADSP1_ZM:
 637                 return "ZM";
 638         default:
 639                 return NULL;
 640         }
 641 }
 642
 643 #ifdef CONFIG_DEBUG_FS
 644 static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s)
 645 {
 646         char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
 647
 648         kfree(dsp->wmfw_file_name);
 649         dsp->wmfw_file_name = tmp;
 650 }
 651
 652 static void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, const char *s)
 653 {
 654         char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
 655
 656         kfree(dsp->bin_file_name);
 657         dsp->bin_file_name = tmp;
 658 }
 659
 660 static void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
 661 {
 662         kfree(dsp->wmfw_file_name);
 663         kfree(dsp->bin_file_name);
 664         dsp->wmfw_file_name = NULL;
 665         dsp->bin_file_name = NULL;
 666 }
 667
 668 static ssize_t wm_adsp_debugfs_wmfw_read(struct file *file,
 669                                          char __user *user_buf,
 670                                          size_t count, loff_t *ppos)
 671 {
 672         struct wm_adsp *dsp = file->private_data;
 673         ssize_t ret;
 674
 675         mutex_lock(&dsp->pwr_lock);
 676
 677         if (!dsp->wmfw_file_name || !dsp->booted)
 678                 ret = 0;
 679         else
 680                 ret = simple_read_from_buffer(user_buf, count, ppos,
 681                                               dsp->wmfw_file_name,
 682                                               strlen(dsp->wmfw_file_name));
 683
 684         mutex_unlock(&dsp->pwr_lock);
 685         return ret;
 686 }
 687
 688 static ssize_t wm_adsp_debugfs_bin_read(struct file *file,
 689                                         char __user *user_buf,
 690                                         size_t count, loff_t *ppos)
 691 {
 692         struct wm_adsp *dsp = file->private_data;
 693         ssize_t ret;
 694
 695         mutex_lock(&dsp->pwr_lock);
 696
 697         if (!dsp->bin_file_name || !dsp->booted)
 698                 ret = 0;
 699         else
 700                 ret = simple_read_from_buffer(user_buf, count, ppos,
 701                                               dsp->bin_file_name,
 702                                               strlen(dsp->bin_file_name));
 703
 704         mutex_unlock(&dsp->pwr_lock);
 705         return ret;
 706 }
 707
 708 static const struct {
 709         const char *name;
 710         const struct file_operations fops;
 711 } wm_adsp_debugfs_fops[] = {
 712         {
 713                 .name = "wmfw_file_name",
 714                 .fops = {
 715                         .open = simple_open,
 716                         .read = wm_adsp_debugfs_wmfw_read,
 717                 },
 718         },
 719         {
 720                 .name = "bin_file_name",
 721                 .fops = {
 722                         .open = simple_open,
 723                         .read = wm_adsp_debugfs_bin_read,
 724                 },
 725         },
 726 };
 727
 728 static void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
 729                                   struct snd_soc_component *component)
 730 {
 731         struct dentry *root = NULL;
 732         int i;
 733
 734         root = debugfs_create_dir(dsp->name, component->debugfs_root);
 735
 736         debugfs_create_bool("booted", 0444, root, &dsp->booted);
 737         debugfs_create_bool("running", 0444, root, &dsp->running);
 738         debugfs_create_x32("fw_id", 0444, root, &dsp->fw_id);
 739         debugfs_create_x32("fw_version", 0444, root, &dsp->fw_id_version);
 740
 741         for (i = 0; i < ARRAY_SIZE(wm_adsp_debugfs_fops); ++i)
 742                 debugfs_create_file(wm_adsp_debugfs_fops[i].name, 0444, root,
 743                                     dsp, &wm_adsp_debugfs_fops[i].fops);
 744
 745         dsp->debugfs_root = root;
 746 }
 747
 748 static void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
 749 {
 750         wm_adsp_debugfs_clear(dsp);
 751         debugfs_remove_recursive(dsp->debugfs_root);
 752         dsp->debugfs_root = NULL;
 753 }
 754 #else
 755 static inline void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
 756                                          struct snd_soc_component *component)
 757 {
 758 }
 759
 760 static inline void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
 761 {
 762 }
 763
 764 static inline void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp,
 765                                                  const char *s)
 766 {
 767 }
 768
 769 static inline void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp,
 770                                                 const char *s)
 771 {
 772 }
 773
 774 static inline void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
 775 {
 776 }
 777 #endif
 778
 779 int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
 780                    struct snd_ctl_elem_value *ucontrol)
 781 {
 782         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 783         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
 784         struct wm_adsp *dsp = snd_soc_component_get_drvdata(component);
 785
 786         ucontrol->value.enumerated.item[0] = dsp[e->shift_l].fw;
 787
 788         return 0;
 789 }
 790 EXPORT_SYMBOL_GPL(wm_adsp_fw_get);
 791
 792 int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
 793                    struct snd_ctl_elem_value *ucontrol)
 794 {
 795         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 796         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
 797         struct wm_adsp *dsp = snd_soc_component_get_drvdata(component);
 798         int ret = 0;
 799
 800         if (ucontrol->value.enumerated.item[0] == dsp[e->shift_l].fw)
 801                 return 0;
 802
 803         if (ucontrol->value.enumerated.item[0] >= WM_ADSP_NUM_FW)
 804                 return -EINVAL;
 805
 806         mutex_lock(&dsp[e->shift_l].pwr_lock);
 807
 808         if (dsp[e->shift_l].booted || !list_empty(&dsp[e->shift_l].compr_list))
 809                 ret = -EBUSY;
 810         else
 811                 dsp[e->shift_l].fw = ucontrol->value.enumerated.item[0];
 812
 813         mutex_unlock(&dsp[e->shift_l].pwr_lock);
 814
 815         return ret;
 816 }
 817 EXPORT_SYMBOL_GPL(wm_adsp_fw_put);
 818
 819 const struct soc_enum wm_adsp_fw_enum[] = {
 820         SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
 821         SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
 822         SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
 823         SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
 824         SOC_ENUM_SINGLE(0, 4, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
 825         SOC_ENUM_SINGLE(0, 5, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
 826         SOC_ENUM_SINGLE(0, 6, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
 827 };
 828 EXPORT_SYMBOL_GPL(wm_adsp_fw_enum);
 829
 830 static const struct wm_adsp_region *wm_adsp_find_region(struct wm_adsp *dsp,
 831                                                         int type)
 832 {
 833         int i;
 834
 835         for (i = 0; i < dsp->num_mems; i++)
 836                 if (dsp->mem[i].type == type)
 837                         return &dsp->mem[i];
 838
 839         return NULL;
 840 }
 841
 842 static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem,
 843                                           unsigned int offset)
 844 {
 845         switch (mem->type) {
 846         case WMFW_ADSP1_PM:
 847                 return mem->base + (offset * 3);
 848         case WMFW_ADSP1_DM:
 849         case WMFW_ADSP2_XM:
 850         case WMFW_ADSP2_YM:
 851         case WMFW_ADSP1_ZM:
 852                 return mem->base + (offset * 2);
 853         default:
 854                 WARN(1, "Unknown memory region type");
 855                 return offset;
 856         }
 857 }
 858
 859 static unsigned int wm_halo_region_to_reg(struct wm_adsp_region const *mem,
 860                                           unsigned int offset)
 861 {
 862         switch (mem->type) {
 863         case WMFW_ADSP2_XM:
 864         case WMFW_ADSP2_YM:
 865                 return mem->base + (offset * 4);
 866         case WMFW_HALO_XM_PACKED:
 867         case WMFW_HALO_YM_PACKED:
 868                 return (mem->base + (offset * 3)) & ~0x3;
 869         case WMFW_HALO_PM_PACKED:
 870                 return mem->base + (offset * 5);
 871         default:
 872                 WARN(1, "Unknown memory region type");
 873                 return offset;
 874         }
 875 }
 876
 877 static void wm_adsp_read_fw_status(struct wm_adsp *dsp,
 878                                    int noffs, unsigned int *offs)
 879 {
 880         unsigned int i;
 881         int ret;
 882
 883         for (i = 0; i < noffs; ++i) {
 884                 ret = regmap_read(dsp->regmap, dsp->base + offs[i], &offs[i]);
 885                 if (ret) {
 886                         adsp_err(dsp, "Failed to read SCRATCH%u: %d\n", i, ret);
 887                         return;
 888                 }
 889         }
 890 }
 891
 892 static void wm_adsp2_show_fw_status(struct wm_adsp *dsp)
 893 {
 894         unsigned int offs[] = {
 895                 ADSP2_SCRATCH0, ADSP2_SCRATCH1, ADSP2_SCRATCH2, ADSP2_SCRATCH3,
 896         };
 897
 898         wm_adsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs);
 899
 900         adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
 901                  offs[0], offs[1], offs[2], offs[3]);
 902 }
 903
 904 static void wm_adsp2v2_show_fw_status(struct wm_adsp *dsp)
 905 {
 906         unsigned int offs[] = { ADSP2V2_SCRATCH0_1, ADSP2V2_SCRATCH2_3 };
 907
 908         wm_adsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs);
 909
 910         adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
 911                  offs[0] & 0xFFFF, offs[0] >> 16,
 912                  offs[1] & 0xFFFF, offs[1] >> 16);
 913 }
 914
 915 static void wm_halo_show_fw_status(struct wm_adsp *dsp)
 916 {
 917         unsigned int offs[] = {
 918                 HALO_SCRATCH1, HALO_SCRATCH2, HALO_SCRATCH3, HALO_SCRATCH4,
 919         };
 920
 921         wm_adsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs);
 922
 923         adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
 924                  offs[0], offs[1], offs[2], offs[3]);
 925 }
 926
 927 static inline struct wm_coeff_ctl *bytes_ext_to_ctl(struct soc_bytes_ext *ext)
 928 {
 929         return container_of(ext, struct wm_coeff_ctl, bytes_ext);
 930 }
 931
 932 static int wm_coeff_base_reg(struct wm_coeff_ctl *ctl, unsigned int *reg)
 933 {
 934         const struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
 935         struct wm_adsp *dsp = ctl->dsp;
 936         const struct wm_adsp_region *mem;
 937
 938         mem = wm_adsp_find_region(dsp, alg_region->type);
 939         if (!mem) {
 940                 adsp_err(dsp, "No base for region %x\n",
 941                          alg_region->type);
 942                 return -EINVAL;
 943         }
 944
 945         *reg = dsp->ops->region_to_reg(mem, ctl->alg_region.base + ctl->offset);
 946
 947         return 0;
 948 }
 949
 950 static int wm_coeff_info(struct snd_kcontrol *kctl,
 951                          struct snd_ctl_elem_info *uinfo)
 952 {
 953         struct soc_bytes_ext *bytes_ext =
 954                 (struct soc_bytes_ext *)kctl->private_value;
 955         struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
 956
 957         switch (ctl->type) {
 958         case WMFW_CTL_TYPE_ACKED:
 959                 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 960                 uinfo->value.integer.min = WM_ADSP_ACKED_CTL_MIN_VALUE;
 961                 uinfo->value.integer.max = WM_ADSP_ACKED_CTL_MAX_VALUE;
 962                 uinfo->value.integer.step = 1;
 963                 uinfo->count = 1;
 964                 break;
 965         default:
 966                 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
 967                 uinfo->count = ctl->len;
 968                 break;
 969         }
 970
 971         return 0;
 972 }
 973
 974 static int wm_coeff_write_acked_control(struct wm_coeff_ctl *ctl,
 975                                         unsigned int event_id)
 976 {
 977         struct wm_adsp *dsp = ctl->dsp;
 978         __be32 val = cpu_to_be32(event_id);
 979         unsigned int reg;
 980         int i, ret;
 981
 982         ret = wm_coeff_base_reg(ctl, &reg);
 983         if (ret)
 984                 return ret;
 985
 986         adsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n",
 987                  event_id, ctl->alg_region.alg,
 988                  wm_adsp_mem_region_name(ctl->alg_region.type), ctl->offset);
 989
 990         ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val));
 991         if (ret) {
 992                 adsp_err(dsp, "Failed to write %x: %d\n", reg, ret);
 993                 return ret;
 994         }
 995
 996         /*
 997          * Poll for ack, we initially poll at ~1ms intervals for firmwares
 998          * that respond quickly, then go to ~10ms polls. A firmware is unlikely
 999          * to ack instantly so we do the first 1ms delay before reading the
1000          * control to avoid a pointless bus transaction
1001          */
1002         for (i = 0; i < WM_ADSP_ACKED_CTL_TIMEOUT_MS;) {
1003                 switch (i) {
1004                 case 0 ... WM_ADSP_ACKED_CTL_N_QUICKPOLLS - 1:
1005                         usleep_range(1000, 2000);
1006                         i++;
1007                         break;
1008                 default:
1009                         usleep_range(10000, 20000);
1010                         i += 10;
1011                         break;
1012                 }
1013
1014                 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
1015                 if (ret) {
1016                         adsp_err(dsp, "Failed to read %x: %d\n", reg, ret);
1017                         return ret;
1018                 }
1019
1020                 if (val == 0) {
1021                         adsp_dbg(dsp, "Acked control ACKED at poll %u\n", i);
1022                         return 0;
1023                 }
1024         }
1025
1026         adsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n",
1027                   reg, ctl->alg_region.alg,
1028                   wm_adsp_mem_region_name(ctl->alg_region.type),
1029                   ctl->offset);
1030
1031         return -ETIMEDOUT;
1032 }
1033
1034 static int wm_coeff_write_ctrl_raw(struct wm_coeff_ctl *ctl,
1035                                    const void *buf, size_t len)
1036 {
1037         struct wm_adsp *dsp = ctl->dsp;
1038         void *scratch;
1039         int ret;
1040         unsigned int reg;
1041
1042         ret = wm_coeff_base_reg(ctl, &reg);
1043         if (ret)
1044                 return ret;
1045
1046         scratch = kmemdup(buf, len, GFP_KERNEL | GFP_DMA);
1047         if (!scratch)
1048                 return -ENOMEM;
1049
1050         ret = regmap_raw_write(dsp->regmap, reg, scratch,
1051                                len);
1052         if (ret) {
1053                 adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n",
1054                          len, reg, ret);
1055                 kfree(scratch);
1056                 return ret;
1057         }
1058         adsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg);
1059
1060         kfree(scratch);
1061
1062         return 0;
1063 }
1064
1065 static int wm_coeff_write_ctrl(struct wm_coeff_ctl *ctl,
1066                                const void *buf, size_t len)
1067 {
1068         int ret = 0;
1069
1070         if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
1071                 ret = -EPERM;
1072         else if (buf != ctl->cache)
1073                 memcpy(ctl->cache, buf, len);
1074
1075         ctl->set = 1;
1076         if (ctl->enabled && ctl->dsp->running)
1077                 ret = wm_coeff_write_ctrl_raw(ctl, buf, len);
1078
1079         return ret;
1080 }
1081
1082 static int wm_coeff_put(struct snd_kcontrol *kctl,
1083                         struct snd_ctl_elem_value *ucontrol)
1084 {
1085         struct soc_bytes_ext *bytes_ext =
1086                 (struct soc_bytes_ext *)kctl->private_value;
1087         struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1088         char *p = ucontrol->value.bytes.data;
1089         int ret = 0;
1090
1091         mutex_lock(&ctl->dsp->pwr_lock);
1092         ret = wm_coeff_write_ctrl(ctl, p, ctl->len);
1093         mutex_unlock(&ctl->dsp->pwr_lock);
1094
1095         return ret;
1096 }
1097
1098 static int wm_coeff_tlv_put(struct snd_kcontrol *kctl,
1099                             const unsigned int __user *bytes, unsigned int size)
1100 {
1101         struct soc_bytes_ext *bytes_ext =
1102                 (struct soc_bytes_ext *)kctl->private_value;
1103         struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1104         int ret = 0;
1105
1106         mutex_lock(&ctl->dsp->pwr_lock);
1107
1108         if (copy_from_user(ctl->cache, bytes, size))
1109                 ret = -EFAULT;
1110         else
1111                 ret = wm_coeff_write_ctrl(ctl, ctl->cache, size);
1112
1113         mutex_unlock(&ctl->dsp->pwr_lock);
1114
1115         return ret;
1116 }
1117
1118 static int wm_coeff_put_acked(struct snd_kcontrol *kctl,
1119                               struct snd_ctl_elem_value *ucontrol)
1120 {
1121         struct soc_bytes_ext *bytes_ext =
1122                 (struct soc_bytes_ext *)kctl->private_value;
1123         struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1124         unsigned int val = ucontrol->value.integer.value[0];
1125         int ret;
1126
1127         if (val == 0)
1128                 return 0;       /* 0 means no event */
1129
1130         mutex_lock(&ctl->dsp->pwr_lock);
1131
1132         if (ctl->enabled && ctl->dsp->running)
1133                 ret = wm_coeff_write_acked_control(ctl, val);
1134         else
1135                 ret = -EPERM;
1136
1137         mutex_unlock(&ctl->dsp->pwr_lock);
1138
1139         return ret;
1140 }
1141
1142 static int wm_coeff_read_ctrl_raw(struct wm_coeff_ctl *ctl,
1143                                   void *buf, size_t len)
1144 {
1145         struct wm_adsp *dsp = ctl->dsp;
1146         void *scratch;
1147         int ret;
1148         unsigned int reg;
1149
1150         ret = wm_coeff_base_reg(ctl, &reg);
1151         if (ret)
1152                 return ret;
1153
1154         scratch = kmalloc(len, GFP_KERNEL | GFP_DMA);
1155         if (!scratch)
1156                 return -ENOMEM;
1157
1158         ret = regmap_raw_read(dsp->regmap, reg, scratch, len);
1159         if (ret) {
1160                 adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n",
1161                          len, reg, ret);
1162                 kfree(scratch);
1163                 return ret;
1164         }
1165         adsp_dbg(dsp, "Read %zu bytes from %x\n", len, reg);
1166
1167         memcpy(buf, scratch, len);
1168         kfree(scratch);
1169
1170         return 0;
1171 }
1172
1173 static int wm_coeff_read_ctrl(struct wm_coeff_ctl *ctl, void *buf, size_t len)
1174 {
1175         int ret = 0;
1176
1177         if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
1178                 if (ctl->enabled && ctl->dsp->running)
1179                         return wm_coeff_read_ctrl_raw(ctl, buf, len);
1180                 else
1181                         return -EPERM;
1182         } else {
1183                 if (!ctl->flags && ctl->enabled && ctl->dsp->running)
1184                         ret = wm_coeff_read_ctrl_raw(ctl, ctl->cache, ctl->len);
1185
1186                 if (buf != ctl->cache)
1187                         memcpy(buf, ctl->cache, len);
1188         }
1189
1190         return ret;
1191 }
1192
1193 static int wm_coeff_get(struct snd_kcontrol *kctl,
1194                         struct snd_ctl_elem_value *ucontrol)
1195 {
1196         struct soc_bytes_ext *bytes_ext =
1197                 (struct soc_bytes_ext *)kctl->private_value;
1198         struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1199         char *p = ucontrol->value.bytes.data;
1200         int ret;
1201
1202         mutex_lock(&ctl->dsp->pwr_lock);
1203         ret = wm_coeff_read_ctrl(ctl, p, ctl->len);
1204         mutex_unlock(&ctl->dsp->pwr_lock);
1205
1206         return ret;
1207 }
1208
1209 static int wm_coeff_tlv_get(struct snd_kcontrol *kctl,
1210                             unsigned int __user *bytes, unsigned int size)
1211 {
1212         struct soc_bytes_ext *bytes_ext =
1213                 (struct soc_bytes_ext *)kctl->private_value;
1214         struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1215         int ret = 0;
1216
1217         mutex_lock(&ctl->dsp->pwr_lock);
1218
1219         ret = wm_coeff_read_ctrl(ctl, ctl->cache, size);
1220
1221         if (!ret && copy_to_user(bytes, ctl->cache, size))
1222                 ret = -EFAULT;
1223
1224         mutex_unlock(&ctl->dsp->pwr_lock);
1225
1226         return ret;
1227 }
1228
1229 static int wm_coeff_get_acked(struct snd_kcontrol *kcontrol,
1230                               struct snd_ctl_elem_value *ucontrol)
1231 {
1232         /*
1233          * Although it's not useful to read an acked control, we must satisfy
1234          * user-side assumptions that all controls are readable and that a
1235          * write of the same value should be filtered out (it's valid to send
1236          * the same event number again to the firmware). We therefore return 0,
1237          * meaning "no event" so valid event numbers will always be a change
1238          */
1239         ucontrol->value.integer.value[0] = 0;
1240
1241         return 0;
1242 }
1243
1244 static unsigned int wmfw_convert_flags(unsigned int in, unsigned int len)
1245 {
1246         unsigned int out, rd, wr, vol;
1247
1248         if (len > ADSP_MAX_STD_CTRL_SIZE) {
1249                 rd = SNDRV_CTL_ELEM_ACCESS_TLV_READ;
1250                 wr = SNDRV_CTL_ELEM_ACCESS_TLV_WRITE;
1251                 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1252
1253                 out = SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK;
1254         } else {
1255                 rd = SNDRV_CTL_ELEM_ACCESS_READ;
1256                 wr = SNDRV_CTL_ELEM_ACCESS_WRITE;
1257                 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1258
1259                 out = 0;
1260         }
1261
1262         if (in) {
1263                 out |= rd;
1264                 if (in & WMFW_CTL_FLAG_WRITEABLE)
1265                         out |= wr;
1266                 if (in & WMFW_CTL_FLAG_VOLATILE)
1267                         out |= vol;
1268         } else {
1269                 out |= rd | wr | vol;
1270         }
1271
1272         return out;
1273 }
1274
1275 static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl)
1276 {
1277         struct snd_kcontrol_new *kcontrol;
1278         int ret;
1279
1280         if (!ctl || !ctl->name)
1281                 return -EINVAL;
1282
1283         kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
1284         if (!kcontrol)
1285                 return -ENOMEM;
1286
1287         kcontrol->name = ctl->name;
1288         kcontrol->info = wm_coeff_info;
1289         kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1290         kcontrol->tlv.c = snd_soc_bytes_tlv_callback;
1291         kcontrol->private_value = (unsigned long)&ctl->bytes_ext;
1292         kcontrol->access = wmfw_convert_flags(ctl->flags, ctl->len);
1293
1294         switch (ctl->type) {
1295         case WMFW_CTL_TYPE_ACKED:
1296                 kcontrol->get = wm_coeff_get_acked;
1297                 kcontrol->put = wm_coeff_put_acked;
1298                 break;
1299         default:
1300                 if (kcontrol->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
1301                         ctl->bytes_ext.max = ctl->len;
1302                         ctl->bytes_ext.get = wm_coeff_tlv_get;
1303                         ctl->bytes_ext.put = wm_coeff_tlv_put;
1304                 } else {
1305                         kcontrol->get = wm_coeff_get;
1306                         kcontrol->put = wm_coeff_put;
1307                 }
1308                 break;
1309         }
1310
1311         ret = snd_soc_add_component_controls(dsp->component, kcontrol, 1);
1312         if (ret < 0)
1313                 goto err_kcontrol;
1314
1315         kfree(kcontrol);
1316
1317         return 0;
1318
1319 err_kcontrol:
1320         kfree(kcontrol);
1321         return ret;
1322 }
1323
1324 static int wm_coeff_init_control_caches(struct wm_adsp *dsp)
1325 {
1326         struct wm_coeff_ctl *ctl;
1327         int ret;
1328
1329         list_for_each_entry(ctl, &dsp->ctl_list, list) {
1330                 if (!ctl->enabled || ctl->set)
1331                         continue;
1332                 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
1333                         continue;
1334
1335                 /*
1336                  * For readable controls populate the cache from the DSP memory.
1337                  * For non-readable controls the cache was zero-filled when
1338                  * created so we don't need to do anything.
1339                  */
1340                 if (!ctl->flags || (ctl->flags & WMFW_CTL_FLAG_READABLE)) {
1341                         ret = wm_coeff_read_ctrl_raw(ctl, ctl->cache, ctl->len);
1342                         if (ret < 0)
1343                                 return ret;
1344                 }
1345         }
1346
1347         return 0;
1348 }
1349
1350 static int wm_coeff_sync_controls(struct wm_adsp *dsp)
1351 {
1352         struct wm_coeff_ctl *ctl;
1353         int ret;
1354
1355         list_for_each_entry(ctl, &dsp->ctl_list, list) {
1356                 if (!ctl->enabled)
1357                         continue;
1358                 if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) {
1359                         ret = wm_coeff_write_ctrl_raw(ctl, ctl->cache,
1360                                                       ctl->len);
1361                         if (ret < 0)
1362                                 return ret;
1363                 }
1364         }
1365
1366         return 0;
1367 }
1368
1369 static void wm_adsp_signal_event_controls(struct wm_adsp *dsp,
1370                                           unsigned int event)
1371 {
1372         struct wm_coeff_ctl *ctl;
1373         int ret;
1374
1375         list_for_each_entry(ctl, &dsp->ctl_list, list) {
1376                 if (ctl->type != WMFW_CTL_TYPE_HOSTEVENT)
1377                         continue;
1378
1379                 if (!ctl->enabled)
1380                         continue;
1381
1382                 ret = wm_coeff_write_acked_control(ctl, event);
1383                 if (ret)
1384                         adsp_warn(dsp,
1385                                   "Failed to send 0x%x event to alg 0x%x (%d)\n",
1386                                   event, ctl->alg_region.alg, ret);
1387         }
1388 }
1389
1390 static void wm_adsp_ctl_work(struct work_struct *work)
1391 {
1392         struct wm_coeff_ctl *ctl = container_of(work,
1393                                                 struct wm_coeff_ctl,
1394                                                 work);
1395
1396         wmfw_add_ctl(ctl->dsp, ctl);
1397 }
1398
1399 static void wm_adsp_free_ctl_blk(struct wm_coeff_ctl *ctl)
1400 {
1401         cancel_work_sync(&ctl->work);
1402
1403         kfree(ctl->cache);
1404         kfree(ctl->name);
1405         kfree(ctl->subname);
1406         kfree(ctl);
1407 }
1408
1409 static int wm_adsp_create_control(struct wm_adsp *dsp,
1410                                   const struct wm_adsp_alg_region *alg_region,
1411                                   unsigned int offset, unsigned int len,
1412                                   const char *subname, unsigned int subname_len,
1413                                   unsigned int flags, unsigned int type)
1414 {
1415         struct wm_coeff_ctl *ctl;
1416         char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
1417         const char *region_name;
1418         int ret;
1419
1420         list_for_each_entry(ctl, &dsp->ctl_list, list) {
1421                 if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] &&
1422                     ctl->alg_region.alg == alg_region->alg &&
1423                     ctl->alg_region.type == alg_region->type) {
1424                         if ((!subname && !ctl->subname) ||
1425                             (subname && !strncmp(ctl->subname, subname, ctl->subname_len))) {
1426                                 if (!ctl->enabled)
1427                                         ctl->enabled = 1;
1428                                 return 0;
1429                         }
1430                 }
1431         }
1432
1433         region_name = wm_adsp_mem_region_name(alg_region->type);
1434         if (!region_name) {
1435                 adsp_err(dsp, "Unknown region type: %d\n", alg_region->type);
1436                 return -EINVAL;
1437         }
1438
1439         switch (dsp->fw_ver) {
1440         case 0:
1441         case 1:
1442                 snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "%s %s %x",
1443                          dsp->name, region_name, alg_region->alg);
1444                 subname = NULL; /* don't append subname */
1445                 break;
1446         case 2:
1447                 ret = scnprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
1448                                 "%s%c %.12s %x", dsp->name, *region_name,
1449                                 wm_adsp_fw_text[dsp->fw], alg_region->alg);
1450                 break;
1451         default:
1452                 ret = scnprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
1453                                 "%s %.12s %x", dsp->name,
1454                                 wm_adsp_fw_text[dsp->fw], alg_region->alg);
1455                 break;
1456         }
1457
1458         if (subname) {
1459                 int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2;
1460                 int skip = 0;
1461
1462                 if (dsp->component->name_prefix)
1463                         avail -= strlen(dsp->component->name_prefix) + 1;
1464
1465                 /* Truncate the subname from the start if it is too long */
1466                 if (subname_len > avail)
1467                         skip = subname_len - avail;
1468
1469                 snprintf(name + ret, SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret,
1470                          " %.*s", subname_len - skip, subname + skip);
1471         }
1472
1473         ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
1474         if (!ctl)
1475                 return -ENOMEM;
1476         ctl->fw_name = wm_adsp_fw_text[dsp->fw];
1477         ctl->alg_region = *alg_region;
1478         ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
1479         if (!ctl->name) {
1480                 ret = -ENOMEM;
1481                 goto err_ctl;
1482         }
1483         if (subname) {
1484                 ctl->subname_len = subname_len;
1485                 ctl->subname = kmemdup(subname,
1486                                        strlen(subname) + 1, GFP_KERNEL);
1487                 if (!ctl->subname) {
1488                         ret = -ENOMEM;
1489                         goto err_ctl_name;
1490                 }
1491         }
1492         ctl->enabled = 1;
1493         ctl->set = 0;
1494         ctl->dsp = dsp;
1495
1496         ctl->flags = flags;
1497         ctl->type = type;
1498         ctl->offset = offset;
1499         ctl->len = len;
1500         ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
1501         if (!ctl->cache) {
1502                 ret = -ENOMEM;
1503                 goto err_ctl_subname;
1504         }
1505
1506         list_add(&ctl->list, &dsp->ctl_list);
1507
1508         if (flags & WMFW_CTL_FLAG_SYS)
1509                 return 0;
1510
1511         INIT_WORK(&ctl->work, wm_adsp_ctl_work);
1512         schedule_work(&ctl->work);
1513
1514         return 0;
1515
1516 err_ctl_subname:
1517         kfree(ctl->subname);
1518 err_ctl_name:
1519         kfree(ctl->name);
1520 err_ctl:
1521         kfree(ctl);
1522
1523         return ret;
1524 }
1525
1526 struct wm_coeff_parsed_alg {
1527         int id;
1528         const u8 *name;
1529         int name_len;
1530         int ncoeff;
1531 };
1532
1533 struct wm_coeff_parsed_coeff {
1534         int offset;
1535         int mem_type;
1536         const u8 *name;
1537         int name_len;
1538         unsigned int ctl_type;
1539         int flags;
1540         int len;
1541 };
1542
1543 static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str)
1544 {
1545         int length;
1546
1547         switch (bytes) {
1548         case 1:
1549                 length = **pos;
1550                 break;
1551         case 2:
1552                 length = le16_to_cpu(*((__le16 *)*pos));
1553                 break;
1554         default:
1555                 return 0;
1556         }
1557
1558         if (str)
1559                 *str = *pos + bytes;
1560
1561         *pos += ((length + bytes) + 3) & ~0x03;
1562
1563         return length;
1564 }
1565
1566 static int wm_coeff_parse_int(int bytes, const u8 **pos)
1567 {
1568         int val = 0;
1569
1570         switch (bytes) {
1571         case 2:
1572                 val = le16_to_cpu(*((__le16 *)*pos));
1573                 break;
1574         case 4:
1575                 val = le32_to_cpu(*((__le32 *)*pos));
1576                 break;
1577         default:
1578                 break;
1579         }
1580
1581         *pos += bytes;
1582
1583         return val;
1584 }
1585
1586 static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data,
1587                                       struct wm_coeff_parsed_alg *blk)
1588 {
1589         const struct wmfw_adsp_alg_data *raw;
1590
1591         switch (dsp->fw_ver) {
1592         case 0:
1593         case 1:
1594                 raw = (const struct wmfw_adsp_alg_data *)*data;
1595                 *data = raw->data;
1596
1597                 blk->id = le32_to_cpu(raw->id);
1598                 blk->name = raw->name;
1599                 blk->name_len = strlen(raw->name);
1600                 blk->ncoeff = le32_to_cpu(raw->ncoeff);
1601                 break;
1602         default:
1603                 blk->id = wm_coeff_parse_int(sizeof(raw->id), data);
1604                 blk->name_len = wm_coeff_parse_string(sizeof(u8), data,
1605                                                       &blk->name);
1606                 wm_coeff_parse_string(sizeof(u16), data, NULL);
1607                 blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data);
1608                 break;
1609         }
1610
1611         adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id);
1612         adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name);
1613         adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff);
1614 }
1615
1616 static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data,
1617                                         struct wm_coeff_parsed_coeff *blk)
1618 {
1619         const struct wmfw_adsp_coeff_data *raw;
1620         const u8 *tmp;
1621         int length;
1622
1623         switch (dsp->fw_ver) {
1624         case 0:
1625         case 1:
1626                 raw = (const struct wmfw_adsp_coeff_data *)*data;
1627                 *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size);
1628
1629                 blk->offset = le16_to_cpu(raw->hdr.offset);
1630                 blk->mem_type = le16_to_cpu(raw->hdr.type);
1631                 blk->name = raw->name;
1632                 blk->name_len = strlen(raw->name);
1633                 blk->ctl_type = le16_to_cpu(raw->ctl_type);
1634                 blk->flags = le16_to_cpu(raw->flags);
1635                 blk->len = le32_to_cpu(raw->len);
1636                 break;
1637         default:
1638                 tmp = *data;
1639                 blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp);
1640                 blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp);
1641                 length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp);
1642                 blk->name_len = wm_coeff_parse_string(sizeof(u8), &tmp,
1643                                                       &blk->name);
1644                 wm_coeff_parse_string(sizeof(u8), &tmp, NULL);
1645                 wm_coeff_parse_string(sizeof(u16), &tmp, NULL);
1646                 blk->ctl_type = wm_coeff_parse_int(sizeof(raw->ctl_type), &tmp);
1647                 blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp);
1648                 blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp);
1649
1650                 *data = *data + sizeof(raw->hdr) + length;
1651                 break;
1652         }
1653
1654         adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type);
1655         adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset);
1656         adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name);
1657         adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags);
1658         adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type);
1659         adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len);
1660 }
1661
1662 static int wm_adsp_check_coeff_flags(struct wm_adsp *dsp,
1663                                 const struct wm_coeff_parsed_coeff *coeff_blk,
1664                                 unsigned int f_required,
1665                                 unsigned int f_illegal)
1666 {
1667         if ((coeff_blk->flags & f_illegal) ||
1668             ((coeff_blk->flags & f_required) != f_required)) {
1669                 adsp_err(dsp, "Illegal flags 0x%x for control type 0x%x\n",
1670                          coeff_blk->flags, coeff_blk->ctl_type);
1671                 return -EINVAL;
1672         }
1673
1674         return 0;
1675 }
1676
1677 static int wm_adsp_parse_coeff(struct wm_adsp *dsp,
1678                                const struct wmfw_region *region)
1679 {
1680         struct wm_adsp_alg_region alg_region = {};
1681         struct wm_coeff_parsed_alg alg_blk;
1682         struct wm_coeff_parsed_coeff coeff_blk;
1683         const u8 *data = region->data;
1684         int i, ret;
1685
1686         wm_coeff_parse_alg(dsp, &data, &alg_blk);
1687         for (i = 0; i < alg_blk.ncoeff; i++) {
1688                 wm_coeff_parse_coeff(dsp, &data, &coeff_blk);
1689
1690                 switch (coeff_blk.ctl_type) {
1691                 case WMFW_CTL_TYPE_BYTES:
1692                         break;
1693                 case WMFW_CTL_TYPE_ACKED:
1694                         if (coeff_blk.flags & WMFW_CTL_FLAG_SYS)
1695                                 continue;       /* ignore */
1696
1697                         ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1698                                                 WMFW_CTL_FLAG_VOLATILE |
1699                                                 WMFW_CTL_FLAG_WRITEABLE |
1700                                                 WMFW_CTL_FLAG_READABLE,
1701                                                 0);
1702                         if (ret)
1703                                 return -EINVAL;
1704                         break;
1705                 case WMFW_CTL_TYPE_HOSTEVENT:
1706                         ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1707                                                 WMFW_CTL_FLAG_SYS |
1708                                                 WMFW_CTL_FLAG_VOLATILE |
1709                                                 WMFW_CTL_FLAG_WRITEABLE |
1710                                                 WMFW_CTL_FLAG_READABLE,
1711                                                 0);
1712                         if (ret)
1713                                 return -EINVAL;
1714                         break;
1715                 case WMFW_CTL_TYPE_HOST_BUFFER:
1716                         ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1717                                                 WMFW_CTL_FLAG_SYS |
1718                                                 WMFW_CTL_FLAG_VOLATILE |
1719                                                 WMFW_CTL_FLAG_READABLE,
1720                                                 0);
1721                         if (ret)
1722                                 return -EINVAL;
1723                         break;
1724                 default:
1725                         adsp_err(dsp, "Unknown control type: %d\n",
1726                                  coeff_blk.ctl_type);
1727                         return -EINVAL;
1728                 }
1729
1730                 alg_region.type = coeff_blk.mem_type;
1731                 alg_region.alg = alg_blk.id;
1732
1733                 ret = wm_adsp_create_control(dsp, &alg_region,
1734                                              coeff_blk.offset,
1735                                              coeff_blk.len,
1736                                              coeff_blk.name,
1737                                              coeff_blk.name_len,
1738                                              coeff_blk.flags,
1739                                              coeff_blk.ctl_type);
1740                 if (ret < 0)
1741                         adsp_err(dsp, "Failed to create control: %.*s, %d\n",
1742                                  coeff_blk.name_len, coeff_blk.name, ret);
1743         }
1744
1745         return 0;
1746 }
1747
1748 static unsigned int wm_adsp1_parse_sizes(struct wm_adsp *dsp,
1749                                          const char * const file,
1750                                          unsigned int pos,
1751                                          const struct firmware *firmware)
1752 {
1753         const struct wmfw_adsp1_sizes *adsp1_sizes;
1754
1755         adsp1_sizes = (void *)&firmware->data[pos];
1756
1757         adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n", file,
1758                  le32_to_cpu(adsp1_sizes->dm), le32_to_cpu(adsp1_sizes->pm),
1759                  le32_to_cpu(adsp1_sizes->zm));
1760
1761         return pos + sizeof(*adsp1_sizes);
1762 }
1763
1764 static unsigned int wm_adsp2_parse_sizes(struct wm_adsp *dsp,
1765                                          const char * const file,
1766                                          unsigned int pos,
1767                                          const struct firmware *firmware)
1768 {
1769         const struct wmfw_adsp2_sizes *adsp2_sizes;
1770
1771         adsp2_sizes = (void *)&firmware->data[pos];
1772
1773         adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n", file,
1774                  le32_to_cpu(adsp2_sizes->xm), le32_to_cpu(adsp2_sizes->ym),
1775                  le32_to_cpu(adsp2_sizes->pm), le32_to_cpu(adsp2_sizes->zm));
1776
1777         return pos + sizeof(*adsp2_sizes);
1778 }
1779
1780 static bool wm_adsp_validate_version(struct wm_adsp *dsp, unsigned int version)
1781 {
1782         switch (version) {
1783         case 0:
1784                 adsp_warn(dsp, "Deprecated file format %d\n", version);
1785                 return true;
1786         case 1:
1787         case 2:
1788                 return true;
1789         default:
1790                 return false;
1791         }
1792 }
1793
1794 static bool wm_halo_validate_version(struct wm_adsp *dsp, unsigned int version)
1795 {
1796         switch (version) {
1797         case 3:
1798                 return true;
1799         default:
1800                 return false;
1801         }
1802 }
1803
1804 static int wm_adsp_load(struct wm_adsp *dsp)
1805 {
1806         LIST_HEAD(buf_list);
1807         const struct firmware *firmware;
1808         struct regmap *regmap = dsp->regmap;
1809         unsigned int pos = 0;
1810         const struct wmfw_header *header;
1811         const struct wmfw_adsp1_sizes *adsp1_sizes;
1812         const struct wmfw_footer *footer;
1813         const struct wmfw_region *region;
1814         const struct wm_adsp_region *mem;
1815         const char *region_name;
1816         char *file, *text = NULL;
1817         struct wm_adsp_buf *buf;
1818         unsigned int reg;
1819         int regions = 0;
1820         int ret, offset, type;
1821
1822         file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1823         if (file == NULL)
1824                 return -ENOMEM;
1825
1826         snprintf(file, PAGE_SIZE, "%s-%s-%s.wmfw", dsp->part, dsp->fwf_name,
1827                  wm_adsp_fw[dsp->fw].file);
1828         file[PAGE_SIZE - 1] = '\0';
1829
1830         ret = request_firmware(&firmware, file, dsp->dev);
1831         if (ret != 0) {
1832                 adsp_err(dsp, "Failed to request '%s'\n", file);
1833                 goto out;
1834         }
1835         ret = -EINVAL;
1836
1837         pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1838         if (pos >= firmware->size) {
1839                 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1840                          file, firmware->size);
1841                 goto out_fw;
1842         }
1843
1844         header = (void *)&firmware->data[0];
1845
1846         if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
1847                 adsp_err(dsp, "%s: invalid magic\n", file);
1848                 goto out_fw;
1849         }
1850
1851         if (!dsp->ops->validate_version(dsp, header->ver)) {
1852                 adsp_err(dsp, "%s: unknown file format %d\n",
1853                          file, header->ver);
1854                 goto out_fw;
1855         }
1856
1857         adsp_info(dsp, "Firmware version: %d\n", header->ver);
1858         dsp->fw_ver = header->ver;
1859
1860         if (header->core != dsp->type) {
1861                 adsp_err(dsp, "%s: invalid core %d != %d\n",
1862                          file, header->core, dsp->type);
1863                 goto out_fw;
1864         }
1865
1866         pos = sizeof(*header);
1867         pos = dsp->ops->parse_sizes(dsp, file, pos, firmware);
1868
1869         footer = (void *)&firmware->data[pos];
1870         pos += sizeof(*footer);
1871
1872         if (le32_to_cpu(header->len) != pos) {
1873                 adsp_err(dsp, "%s: unexpected header length %d\n",
1874                          file, le32_to_cpu(header->len));
1875                 goto out_fw;
1876         }
1877
1878         adsp_dbg(dsp, "%s: timestamp %llu\n", file,
1879                  le64_to_cpu(footer->timestamp));
1880
1881         while (pos < firmware->size &&
1882                sizeof(*region) < firmware->size - pos) {
1883                 region = (void *)&(firmware->data[pos]);
1884                 region_name = "Unknown";
1885                 reg = 0;
1886                 text = NULL;
1887                 offset = le32_to_cpu(region->offset) & 0xffffff;
1888                 type = be32_to_cpu(region->type) & 0xff;
1889
1890                 switch (type) {
1891                 case WMFW_NAME_TEXT:
1892                         region_name = "Firmware name";
1893                         text = kzalloc(le32_to_cpu(region->len) + 1,
1894                                        GFP_KERNEL);
1895                         break;
1896                 case WMFW_ALGORITHM_DATA:
1897                         region_name = "Algorithm";
1898                         ret = wm_adsp_parse_coeff(dsp, region);
1899                         if (ret != 0)
1900                                 goto out_fw;
1901                         break;
1902                 case WMFW_INFO_TEXT:
1903                         region_name = "Information";
1904                         text = kzalloc(le32_to_cpu(region->len) + 1,
1905                                        GFP_KERNEL);
1906                         break;
1907                 case WMFW_ABSOLUTE:
1908                         region_name = "Absolute";
1909                         reg = offset;
1910                         break;
1911                 case WMFW_ADSP1_PM:
1912                 case WMFW_ADSP1_DM:
1913                 case WMFW_ADSP2_XM:
1914                 case WMFW_ADSP2_YM:
1915                 case WMFW_ADSP1_ZM:
1916                 case WMFW_HALO_PM_PACKED:
1917                 case WMFW_HALO_XM_PACKED:
1918                 case WMFW_HALO_YM_PACKED:
1919                         mem = wm_adsp_find_region(dsp, type);
1920                         if (!mem) {
1921                                 adsp_err(dsp, "No region of type: %x\n", type);
1922                                 ret = -EINVAL;
1923                                 goto out_fw;
1924                         }
1925
1926                         region_name = wm_adsp_mem_region_name(type);
1927                         reg = dsp->ops->region_to_reg(mem, offset);
1928                         break;
1929                 default:
1930                         adsp_warn(dsp,
1931                                   "%s.%d: Unknown region type %x at %d(%x)\n",
1932                                   file, regions, type, pos, pos);
1933                         break;
1934                 }
1935
1936                 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
1937                          regions, le32_to_cpu(region->len), offset,
1938                          region_name);
1939
1940                 if (le32_to_cpu(region->len) >
1941                     firmware->size - pos - sizeof(*region)) {
1942                         adsp_err(dsp,
1943                                  "%s.%d: %s region len %d bytes exceeds file length %zu\n",
1944                                  file, regions, region_name,
1945                                  le32_to_cpu(region->len), firmware->size);
1946                         ret = -EINVAL;
1947                         goto out_fw;
1948                 }
1949
1950                 if (text) {
1951                         memcpy(text, region->data, le32_to_cpu(region->len));
1952                         adsp_info(dsp, "%s: %s\n", file, text);
1953                         kfree(text);
1954                         text = NULL;
1955                 }
1956
1957                 if (reg) {
1958                         buf = wm_adsp_buf_alloc(region->data,
1959                                                 le32_to_cpu(region->len),
1960                                                 &buf_list);
1961                         if (!buf) {
1962                                 adsp_err(dsp, "Out of memory\n");
1963                                 ret = -ENOMEM;
1964                                 goto out_fw;
1965                         }
1966
1967                         ret = regmap_raw_write_async(regmap, reg, buf->buf,
1968                                                      le32_to_cpu(region->len));
1969                         if (ret != 0) {
1970                                 adsp_err(dsp,
1971                                         "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
1972                                         file, regions,
1973                                         le32_to_cpu(region->len), offset,
1974                                         region_name, ret);
1975                                 goto out_fw;
1976                         }
1977                 }
1978
1979                 pos += le32_to_cpu(region->len) + sizeof(*region);
1980                 regions++;
1981         }
1982
1983         ret = regmap_async_complete(regmap);
1984         if (ret != 0) {
1985                 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1986                 goto out_fw;
1987         }
1988
1989         if (pos > firmware->size)
1990                 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1991                           file, regions, pos - firmware->size);
1992
1993         wm_adsp_debugfs_save_wmfwname(dsp, file);
1994
1995 out_fw:
1996         regmap_async_complete(regmap);
1997         wm_adsp_buf_free(&buf_list);
1998         release_firmware(firmware);
1999         kfree(text);
2000 out:
2001         kfree(file);
2002
2003         return ret;
2004 }
2005
2006 /*
2007  * Find wm_coeff_ctl with input name as its subname
2008  * If not found, return NULL
2009  */
2010 static struct wm_coeff_ctl *wm_adsp_get_ctl(struct wm_adsp *dsp,
2011                                              const char *name, int type,
2012                                              unsigned int alg)
2013 {
2014         struct wm_coeff_ctl *pos, *rslt = NULL;
2015         const char *fw_txt = wm_adsp_fw_text[dsp->fw];
2016
2017         list_for_each_entry(pos, &dsp->ctl_list, list) {
2018                 if (!pos->subname)
2019                         continue;
2020                 if (strncmp(pos->subname, name, pos->subname_len) == 0 &&
2021                     pos->fw_name == fw_txt &&
2022                     pos->alg_region.alg == alg &&
2023                     pos->alg_region.type == type) {
2024                         rslt = pos;
2025                         break;
2026                 }
2027         }
2028
2029         return rslt;
2030 }
2031
2032 int wm_adsp_write_ctl(struct wm_adsp *dsp, const char *name, int type,
2033                       unsigned int alg, void *buf, size_t len)
2034 {
2035         struct wm_coeff_ctl *ctl;
2036         struct snd_kcontrol *kcontrol;
2037         char ctl_name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
2038         int ret;
2039
2040         ctl = wm_adsp_get_ctl(dsp, name, type, alg);
2041         if (!ctl)
2042                 return -EINVAL;
2043
2044         if (len > ctl->len)
2045                 return -EINVAL;
2046
2047         ret = wm_coeff_write_ctrl(ctl, buf, len);
2048         if (ret)
2049                 return ret;
2050
2051         if (ctl->flags & WMFW_CTL_FLAG_SYS)
2052                 return 0;
2053
2054         if (dsp->component->name_prefix)
2055                 snprintf(ctl_name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "%s %s",
2056                          dsp->component->name_prefix, ctl->name);
2057         else
2058                 snprintf(ctl_name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "%s",
2059                          ctl->name);
2060
2061         kcontrol = snd_soc_card_get_kcontrol(dsp->component->card, ctl_name);
2062         if (!kcontrol) {
2063                 adsp_err(dsp, "Can't find kcontrol %s\n", ctl_name);
2064                 return -EINVAL;
2065         }
2066
2067         snd_ctl_notify(dsp->component->card->snd_card,
2068                        SNDRV_CTL_EVENT_MASK_VALUE, &kcontrol->id);
2069
2070         return 0;
2071 }
2072 EXPORT_SYMBOL_GPL(wm_adsp_write_ctl);
2073
2074 int wm_adsp_read_ctl(struct wm_adsp *dsp, const char *name, int type,
2075                      unsigned int alg, void *buf, size_t len)
2076 {
2077         struct wm_coeff_ctl *ctl;
2078
2079         ctl = wm_adsp_get_ctl(dsp, name, type, alg);
2080         if (!ctl)
2081                 return -EINVAL;
2082
2083         if (len > ctl->len)
2084                 return -EINVAL;
2085
2086         return wm_coeff_read_ctrl(ctl, buf, len);
2087 }
2088 EXPORT_SYMBOL_GPL(wm_adsp_read_ctl);
2089
2090 static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp,
2091                                   const struct wm_adsp_alg_region *alg_region)
2092 {
2093         struct wm_coeff_ctl *ctl;
2094
2095         list_for_each_entry(ctl, &dsp->ctl_list, list) {
2096                 if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] &&
2097                     alg_region->alg == ctl->alg_region.alg &&
2098                     alg_region->type == ctl->alg_region.type) {
2099                         ctl->alg_region.base = alg_region->base;
2100                 }
2101         }
2102 }
2103
2104 static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs,
2105                                const struct wm_adsp_region *mem,
2106                                unsigned int pos, unsigned int len)
2107 {
2108         void *alg;
2109         unsigned int reg;
2110         int ret;
2111         __be32 val;
2112
2113         if (n_algs == 0) {
2114                 adsp_err(dsp, "No algorithms\n");
2115                 return ERR_PTR(-EINVAL);
2116         }
2117
2118         if (n_algs > 1024) {
2119                 adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs);
2120                 return ERR_PTR(-EINVAL);
2121         }
2122
2123         /* Read the terminator first to validate the length */
2124         reg = dsp->ops->region_to_reg(mem, pos + len);
2125
2126         ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
2127         if (ret != 0) {
2128                 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
2129                         ret);
2130                 return ERR_PTR(ret);
2131         }
2132
2133         if (be32_to_cpu(val) != 0xbedead)
2134                 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbedead\n",
2135                           reg, be32_to_cpu(val));
2136
2137         /* Convert length from DSP words to bytes */
2138         len *= sizeof(u32);
2139
2140         alg = kzalloc(len, GFP_KERNEL | GFP_DMA);
2141         if (!alg)
2142                 return ERR_PTR(-ENOMEM);
2143
2144         reg = dsp->ops->region_to_reg(mem, pos);
2145
2146         ret = regmap_raw_read(dsp->regmap, reg, alg, len);
2147         if (ret != 0) {
2148                 adsp_err(dsp, "Failed to read algorithm list: %d\n", ret);
2149                 kfree(alg);
2150                 return ERR_PTR(ret);
2151         }
2152
2153         return alg;
2154 }
2155
2156 static struct wm_adsp_alg_region *
2157         wm_adsp_find_alg_region(struct wm_adsp *dsp, int type, unsigned int id)
2158 {
2159         struct wm_adsp_alg_region *alg_region;
2160
2161         list_for_each_entry(alg_region, &dsp->alg_regions, list) {
2162                 if (id == alg_region->alg && type == alg_region->type)
2163                         return alg_region;
2164         }
2165
2166         return NULL;
2167 }
2168
2169 static struct wm_adsp_alg_region *wm_adsp_create_region(struct wm_adsp *dsp,
2170                                                         int type, __be32 id,
2171                                                         __be32 base)
2172 {
2173         struct wm_adsp_alg_region *alg_region;
2174
2175         alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL);
2176         if (!alg_region)
2177                 return ERR_PTR(-ENOMEM);
2178
2179         alg_region->type = type;
2180         alg_region->alg = be32_to_cpu(id);
2181         alg_region->base = be32_to_cpu(base);
2182
2183         list_add_tail(&alg_region->list, &dsp->alg_regions);
2184
2185         if (dsp->fw_ver > 0)
2186                 wm_adsp_ctl_fixup_base(dsp, alg_region);
2187
2188         return alg_region;
2189 }
2190
2191 static void wm_adsp_free_alg_regions(struct wm_adsp *dsp)
2192 {
2193         struct wm_adsp_alg_region *alg_region;
2194
2195         while (!list_empty(&dsp->alg_regions)) {
2196                 alg_region = list_first_entry(&dsp->alg_regions,
2197                                               struct wm_adsp_alg_region,
2198                                               list);
2199                 list_del(&alg_region->list);
2200                 kfree(alg_region);
2201         }
2202 }
2203
2204 static void wmfw_parse_id_header(struct wm_adsp *dsp,
2205                                  struct wmfw_id_hdr *fw, int nalgs)
2206 {
2207         dsp->fw_id = be32_to_cpu(fw->id);
2208         dsp->fw_id_version = be32_to_cpu(fw->ver);
2209
2210         adsp_info(dsp, "Firmware: %x v%d.%d.%d, %d algorithms\n",
2211                   dsp->fw_id, (dsp->fw_id_version & 0xff0000) >> 16,
2212                   (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff,
2213                   nalgs);
2214 }
2215
2216 static void wmfw_v3_parse_id_header(struct wm_adsp *dsp,
2217                                     struct wmfw_v3_id_hdr *fw, int nalgs)
2218 {
2219         dsp->fw_id = be32_to_cpu(fw->id);
2220         dsp->fw_id_version = be32_to_cpu(fw->ver);
2221         dsp->fw_vendor_id = be32_to_cpu(fw->vendor_id);
2222
2223         adsp_info(dsp, "Firmware: %x vendor: 0x%x v%d.%d.%d, %d algorithms\n",
2224                   dsp->fw_id, dsp->fw_vendor_id,
2225                   (dsp->fw_id_version & 0xff0000) >> 16,
2226                   (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff,
2227                   nalgs);
2228 }
2229
2230 static int wm_adsp_create_regions(struct wm_adsp *dsp, __be32 id, int nregions,
2231                                 const int *type, __be32 *base)
2232 {
2233         struct wm_adsp_alg_region *alg_region;
2234         int i;
2235
2236         for (i = 0; i < nregions; i++) {
2237                 alg_region = wm_adsp_create_region(dsp, type[i], id, base[i]);
2238                 if (IS_ERR(alg_region))
2239                         return PTR_ERR(alg_region);
2240         }
2241
2242         return 0;
2243 }
2244
2245 static int wm_adsp1_setup_algs(struct wm_adsp *dsp)
2246 {
2247         struct wmfw_adsp1_id_hdr adsp1_id;
2248         struct wmfw_adsp1_alg_hdr *adsp1_alg;
2249         struct wm_adsp_alg_region *alg_region;
2250         const struct wm_adsp_region *mem;
2251         unsigned int pos, len;
2252         size_t n_algs;
2253         int i, ret;
2254
2255         mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
2256         if (WARN_ON(!mem))
2257                 return -EINVAL;
2258
2259         ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id,
2260                               sizeof(adsp1_id));
2261         if (ret != 0) {
2262                 adsp_err(dsp, "Failed to read algorithm info: %d\n",
2263                          ret);
2264                 return ret;
2265         }
2266
2267         n_algs = be32_to_cpu(adsp1_id.n_algs);
2268
2269         wmfw_parse_id_header(dsp, &adsp1_id.fw, n_algs);
2270
2271         alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
2272                                            adsp1_id.fw.id, adsp1_id.zm);
2273         if (IS_ERR(alg_region))
2274                 return PTR_ERR(alg_region);
2275
2276         alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
2277                                            adsp1_id.fw.id, adsp1_id.dm);
2278         if (IS_ERR(alg_region))
2279                 return PTR_ERR(alg_region);
2280
2281         /* Calculate offset and length in DSP words */
2282         pos = sizeof(adsp1_id) / sizeof(u32);
2283         len = (sizeof(*adsp1_alg) * n_algs) / sizeof(u32);
2284
2285         adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len);
2286         if (IS_ERR(adsp1_alg))
2287                 return PTR_ERR(adsp1_alg);
2288
2289         for (i = 0; i < n_algs; i++) {
2290                 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
2291                           i, be32_to_cpu(adsp1_alg[i].alg.id),
2292                           (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
2293                           (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
2294                           be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
2295                           be32_to_cpu(adsp1_alg[i].dm),
2296                           be32_to_cpu(adsp1_alg[i].zm));
2297
2298                 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
2299                                                    adsp1_alg[i].alg.id,
2300                                                    adsp1_alg[i].dm);
2301                 if (IS_ERR(alg_region)) {
2302                         ret = PTR_ERR(alg_region);
2303                         goto out;
2304                 }
2305                 if (dsp->fw_ver == 0) {
2306                         if (i + 1 < n_algs) {
2307                                 len = be32_to_cpu(adsp1_alg[i + 1].dm);
2308                                 len -= be32_to_cpu(adsp1_alg[i].dm);
2309                                 len *= 4;
2310                                 wm_adsp_create_control(dsp, alg_region, 0,
2311                                                      len, NULL, 0, 0,
2312                                                      WMFW_CTL_TYPE_BYTES);
2313                         } else {
2314                                 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
2315                                           be32_to_cpu(adsp1_alg[i].alg.id));
2316                         }
2317                 }
2318
2319                 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
2320                                                    adsp1_alg[i].alg.id,
2321                                                    adsp1_alg[i].zm);
2322                 if (IS_ERR(alg_region)) {
2323                         ret = PTR_ERR(alg_region);
2324                         goto out;
2325                 }
2326                 if (dsp->fw_ver == 0) {
2327                         if (i + 1 < n_algs) {
2328                                 len = be32_to_cpu(adsp1_alg[i + 1].zm);
2329                                 len -= be32_to_cpu(adsp1_alg[i].zm);
2330                                 len *= 4;
2331                                 wm_adsp_create_control(dsp, alg_region, 0,
2332                                                      len, NULL, 0, 0,
2333                                                      WMFW_CTL_TYPE_BYTES);
2334                         } else {
2335                                 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
2336                                           be32_to_cpu(adsp1_alg[i].alg.id));
2337                         }
2338                 }
2339         }
2340
2341 out:
2342         kfree(adsp1_alg);
2343         return ret;
2344 }
2345
2346 static int wm_adsp2_setup_algs(struct wm_adsp *dsp)
2347 {
2348         struct wmfw_adsp2_id_hdr adsp2_id;
2349         struct wmfw_adsp2_alg_hdr *adsp2_alg;
2350         struct wm_adsp_alg_region *alg_region;
2351         const struct wm_adsp_region *mem;
2352         unsigned int pos, len;
2353         size_t n_algs;
2354         int i, ret;
2355
2356         mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
2357         if (WARN_ON(!mem))
2358                 return -EINVAL;
2359
2360         ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id,
2361                               sizeof(adsp2_id));
2362         if (ret != 0) {
2363                 adsp_err(dsp, "Failed to read algorithm info: %d\n",
2364                          ret);
2365                 return ret;
2366         }
2367
2368         n_algs = be32_to_cpu(adsp2_id.n_algs);
2369
2370         wmfw_parse_id_header(dsp, &adsp2_id.fw, n_algs);
2371
2372         alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
2373                                            adsp2_id.fw.id, adsp2_id.xm);
2374         if (IS_ERR(alg_region))
2375                 return PTR_ERR(alg_region);
2376
2377         alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
2378                                            adsp2_id.fw.id, adsp2_id.ym);
2379         if (IS_ERR(alg_region))
2380                 return PTR_ERR(alg_region);
2381
2382         alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
2383                                            adsp2_id.fw.id, adsp2_id.zm);
2384         if (IS_ERR(alg_region))
2385                 return PTR_ERR(alg_region);
2386
2387         /* Calculate offset and length in DSP words */
2388         pos = sizeof(adsp2_id) / sizeof(u32);
2389         len = (sizeof(*adsp2_alg) * n_algs) / sizeof(u32);
2390
2391         adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len);
2392         if (IS_ERR(adsp2_alg))
2393                 return PTR_ERR(adsp2_alg);
2394
2395         for (i = 0; i < n_algs; i++) {
2396                 adsp_info(dsp,
2397                           "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
2398                           i, be32_to_cpu(adsp2_alg[i].alg.id),
2399                           (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
2400                           (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
2401                           be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
2402                           be32_to_cpu(adsp2_alg[i].xm),
2403                           be32_to_cpu(adsp2_alg[i].ym),
2404                           be32_to_cpu(adsp2_alg[i].zm));
2405
2406                 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
2407                                                    adsp2_alg[i].alg.id,
2408                                                    adsp2_alg[i].xm);
2409                 if (IS_ERR(alg_region)) {
2410                         ret = PTR_ERR(alg_region);
2411                         goto out;
2412                 }
2413                 if (dsp->fw_ver == 0) {
2414                         if (i + 1 < n_algs) {
2415                                 len = be32_to_cpu(adsp2_alg[i + 1].xm);
2416                                 len -= be32_to_cpu(adsp2_alg[i].xm);
2417                                 len *= 4;
2418                                 wm_adsp_create_control(dsp, alg_region, 0,
2419                                                      len, NULL, 0, 0,
2420                                                      WMFW_CTL_TYPE_BYTES);
2421                         } else {
2422                                 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
2423                                           be32_to_cpu(adsp2_alg[i].alg.id));
2424                         }
2425                 }
2426
2427                 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
2428                                                    adsp2_alg[i].alg.id,
2429                                                    adsp2_alg[i].ym);
2430                 if (IS_ERR(alg_region)) {
2431                         ret = PTR_ERR(alg_region);
2432                         goto out;
2433                 }
2434                 if (dsp->fw_ver == 0) {
2435                         if (i + 1 < n_algs) {
2436                                 len = be32_to_cpu(adsp2_alg[i + 1].ym);
2437                                 len -= be32_to_cpu(adsp2_alg[i].ym);
2438                                 len *= 4;
2439                                 wm_adsp_create_control(dsp, alg_region, 0,
2440                                                      len, NULL, 0, 0,
2441                                                      WMFW_CTL_TYPE_BYTES);
2442                         } else {
2443                                 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
2444                                           be32_to_cpu(adsp2_alg[i].alg.id));
2445                         }
2446                 }
2447
2448                 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
2449                                                    adsp2_alg[i].alg.id,
2450                                                    adsp2_alg[i].zm);
2451                 if (IS_ERR(alg_region)) {
2452                         ret = PTR_ERR(alg_region);
2453                         goto out;
2454                 }
2455                 if (dsp->fw_ver == 0) {
2456                         if (i + 1 < n_algs) {
2457                                 len = be32_to_cpu(adsp2_alg[i + 1].zm);
2458                                 len -= be32_to_cpu(adsp2_alg[i].zm);
2459                                 len *= 4;
2460                                 wm_adsp_create_control(dsp, alg_region, 0,
2461                                                      len, NULL, 0, 0,
2462                                                      WMFW_CTL_TYPE_BYTES);
2463                         } else {
2464                                 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
2465                                           be32_to_cpu(adsp2_alg[i].alg.id));
2466                         }
2467                 }
2468         }
2469
2470 out:
2471         kfree(adsp2_alg);
2472         return ret;
2473 }
2474
2475 static int wm_halo_create_regions(struct wm_adsp *dsp, __be32 id,
2476                                   __be32 xm_base, __be32 ym_base)
2477 {
2478         static const int types[] = {
2479                 WMFW_ADSP2_XM, WMFW_HALO_XM_PACKED,
2480                 WMFW_ADSP2_YM, WMFW_HALO_YM_PACKED
2481         };
2482         __be32 bases[] = { xm_base, xm_base, ym_base, ym_base };
2483
2484         return wm_adsp_create_regions(dsp, id, ARRAY_SIZE(types), types, bases);
2485 }
2486
2487 static int wm_halo_setup_algs(struct wm_adsp *dsp)
2488 {
2489         struct wmfw_halo_id_hdr halo_id;
2490         struct wmfw_halo_alg_hdr *halo_alg;
2491         const struct wm_adsp_region *mem;
2492         unsigned int pos, len;
2493         size_t n_algs;
2494         int i, ret;
2495
2496         mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
2497         if (WARN_ON(!mem))
2498                 return -EINVAL;
2499
2500         ret = regmap_raw_read(dsp->regmap, mem->base, &halo_id,
2501                               sizeof(halo_id));
2502         if (ret != 0) {
2503                 adsp_err(dsp, "Failed to read algorithm info: %d\n",
2504                          ret);
2505                 return ret;
2506         }
2507
2508         n_algs = be32_to_cpu(halo_id.n_algs);
2509
2510         wmfw_v3_parse_id_header(dsp, &halo_id.fw, n_algs);
2511
2512         ret = wm_halo_create_regions(dsp, halo_id.fw.id,
2513                                      halo_id.xm_base, halo_id.ym_base);
2514         if (ret)
2515                 return ret;
2516
2517         /* Calculate offset and length in DSP words */
2518         pos = sizeof(halo_id) / sizeof(u32);
2519         len = (sizeof(*halo_alg) * n_algs) / sizeof(u32);
2520
2521         halo_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len);
2522         if (IS_ERR(halo_alg))
2523                 return PTR_ERR(halo_alg);
2524
2525         for (i = 0; i < n_algs; i++) {
2526                 adsp_info(dsp,
2527                           "%d: ID %x v%d.%d.%d XM@%x YM@%x\n",
2528                           i, be32_to_cpu(halo_alg[i].alg.id),
2529                           (be32_to_cpu(halo_alg[i].alg.ver) & 0xff0000) >> 16,
2530                           (be32_to_cpu(halo_alg[i].alg.ver) & 0xff00) >> 8,
2531                           be32_to_cpu(halo_alg[i].alg.ver) & 0xff,
2532                           be32_to_cpu(halo_alg[i].xm_base),
2533                           be32_to_cpu(halo_alg[i].ym_base));
2534
2535                 ret = wm_halo_create_regions(dsp, halo_alg[i].alg.id,
2536                                              halo_alg[i].xm_base,
2537                                              halo_alg[i].ym_base);
2538                 if (ret)
2539                         goto out;
2540         }
2541
2542 out:
2543         kfree(halo_alg);
2544         return ret;
2545 }
2546
2547 static int wm_adsp_load_coeff(struct wm_adsp *dsp)
2548 {
2549         LIST_HEAD(buf_list);
2550         struct regmap *regmap = dsp->regmap;
2551         struct wmfw_coeff_hdr *hdr;
2552         struct wmfw_coeff_item *blk;
2553         const struct firmware *firmware;
2554         const struct wm_adsp_region *mem;
2555         struct wm_adsp_alg_region *alg_region;
2556         const char *region_name;
2557         int ret, pos, blocks, type, offset, reg;
2558         char *file;
2559         struct wm_adsp_buf *buf;
2560
2561         file = kzalloc(PAGE_SIZE, GFP_KERNEL);
2562         if (file == NULL)
2563                 return -ENOMEM;
2564
2565         snprintf(file, PAGE_SIZE, "%s-%s-%s.bin", dsp->part, dsp->fwf_name,
2566                  wm_adsp_fw[dsp->fw].file);
2567         file[PAGE_SIZE - 1] = '\0';
2568
2569         ret = request_firmware(&firmware, file, dsp->dev);
2570         if (ret != 0) {
2571                 adsp_warn(dsp, "Failed to request '%s'\n", file);
2572                 ret = 0;
2573                 goto out;
2574         }
2575         ret = -EINVAL;
2576
2577         if (sizeof(*hdr) >= firmware->size) {
2578                 adsp_err(dsp, "%s: file too short, %zu bytes\n",
2579                         file, firmware->size);
2580                 goto out_fw;
2581         }
2582
2583         hdr = (void *)&firmware->data[0];
2584         if (memcmp(hdr->magic, "WMDR", 4) != 0) {
2585                 adsp_err(dsp, "%s: invalid magic\n", file);
2586                 goto out_fw;
2587         }
2588
2589         switch (be32_to_cpu(hdr->rev) & 0xff) {
2590         case 1:
2591                 break;
2592         default:
2593                 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
2594                          file, be32_to_cpu(hdr->rev) & 0xff);
2595                 ret = -EINVAL;
2596                 goto out_fw;
2597         }
2598
2599         adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
2600                 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
2601                 (le32_to_cpu(hdr->ver) >>  8) & 0xff,
2602                 le32_to_cpu(hdr->ver) & 0xff);
2603
2604         pos = le32_to_cpu(hdr->len);
2605
2606         blocks = 0;
2607         while (pos < firmware->size &&
2608                sizeof(*blk) < firmware->size - pos) {
2609                 blk = (void *)(&firmware->data[pos]);
2610
2611                 type = le16_to_cpu(blk->type);
2612                 offset = le16_to_cpu(blk->offset);
2613
2614                 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
2615                          file, blocks, le32_to_cpu(blk->id),
2616                          (le32_to_cpu(blk->ver) >> 16) & 0xff,
2617                          (le32_to_cpu(blk->ver) >>  8) & 0xff,
2618                          le32_to_cpu(blk->ver) & 0xff);
2619                 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
2620                          file, blocks, le32_to_cpu(blk->len), offset, type);
2621
2622                 reg = 0;
2623                 region_name = "Unknown";
2624                 switch (type) {
2625                 case (WMFW_NAME_TEXT << 8):
2626                 case (WMFW_INFO_TEXT << 8):
2627                 case (WMFW_METADATA << 8):
2628                         break;
2629                 case (WMFW_ABSOLUTE << 8):
2630                         /*
2631                          * Old files may use this for global
2632                          * coefficients.
2633                          */
2634                         if (le32_to_cpu(blk->id) == dsp->fw_id &&
2635                             offset == 0) {
2636                                 region_name = "global coefficients";
2637                                 mem = wm_adsp_find_region(dsp, type);
2638                                 if (!mem) {
2639                                         adsp_err(dsp, "No ZM\n");
2640                                         break;
2641                                 }
2642                                 reg = dsp->ops->region_to_reg(mem, 0);
2643
2644                         } else {
2645                                 region_name = "register";
2646                                 reg = offset;
2647                         }
2648                         break;
2649
2650                 case WMFW_ADSP1_DM:
2651                 case WMFW_ADSP1_ZM:
2652                 case WMFW_ADSP2_XM:
2653                 case WMFW_ADSP2_YM:
2654                 case WMFW_HALO_XM_PACKED:
2655                 case WMFW_HALO_YM_PACKED:
2656                 case WMFW_HALO_PM_PACKED:
2657                         adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
2658                                  file, blocks, le32_to_cpu(blk->len),
2659                                  type, le32_to_cpu(blk->id));
2660
2661                         mem = wm_adsp_find_region(dsp, type);
2662                         if (!mem) {
2663                                 adsp_err(dsp, "No base for region %x\n", type);
2664                                 break;
2665                         }
2666
2667                         alg_region = wm_adsp_find_alg_region(dsp, type,
2668                                                 le32_to_cpu(blk->id));
2669                         if (alg_region) {
2670                                 reg = alg_region->base;
2671                                 reg = dsp->ops->region_to_reg(mem, reg);
2672                                 reg += offset;
2673                         } else {
2674                                 adsp_err(dsp, "No %x for algorithm %x\n",
2675                                          type, le32_to_cpu(blk->id));
2676                         }
2677                         break;
2678
2679                 default:
2680                         adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
2681                                  file, blocks, type, pos);
2682                         break;
2683                 }
2684
2685                 if (reg) {
2686                         if (le32_to_cpu(blk->len) >
2687                             firmware->size - pos - sizeof(*blk)) {
2688                                 adsp_err(dsp,
2689                                          "%s.%d: %s region len %d bytes exceeds file length %zu\n",
2690                                          file, blocks, region_name,
2691                                          le32_to_cpu(blk->len),
2692                                          firmware->size);
2693                                 ret = -EINVAL;
2694                                 goto out_fw;
2695                         }
2696
2697                         buf = wm_adsp_buf_alloc(blk->data,
2698                                                 le32_to_cpu(blk->len),
2699                                                 &buf_list);
2700                         if (!buf) {
2701                                 adsp_err(dsp, "Out of memory\n");
2702                                 ret = -ENOMEM;
2703                                 goto out_fw;
2704                         }
2705
2706                         adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
2707                                  file, blocks, le32_to_cpu(blk->len),
2708                                  reg);
2709                         ret = regmap_raw_write_async(regmap, reg, buf->buf,
2710                                                      le32_to_cpu(blk->len));
2711                         if (ret != 0) {
2712                                 adsp_err(dsp,
2713                                         "%s.%d: Failed to write to %x in %s: %d\n",
2714                                         file, blocks, reg, region_name, ret);
2715                         }
2716                 }
2717
2718                 pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03;
2719                 blocks++;
2720         }
2721
2722         ret = regmap_async_complete(regmap);
2723         if (ret != 0)
2724                 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
2725
2726         if (pos > firmware->size)
2727                 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
2728                           file, blocks, pos - firmware->size);
2729
2730         wm_adsp_debugfs_save_binname(dsp, file);
2731
2732 out_fw:
2733         regmap_async_complete(regmap);
2734         release_firmware(firmware);
2735         wm_adsp_buf_free(&buf_list);
2736 out:
2737         kfree(file);
2738         return ret;
2739 }
2740
2741 static int wm_adsp_create_name(struct wm_adsp *dsp)
2742 {
2743         char *p;
2744
2745         if (!dsp->name) {
2746                 dsp->name = devm_kasprintf(dsp->dev, GFP_KERNEL, "DSP%d",
2747                                            dsp->num);
2748                 if (!dsp->name)
2749                         return -ENOMEM;
2750         }
2751
2752         if (!dsp->fwf_name) {
2753                 p = devm_kstrdup(dsp->dev, dsp->name, GFP_KERNEL);
2754                 if (!p)
2755                         return -ENOMEM;
2756
2757                 dsp->fwf_name = p;
2758                 for (; *p != 0; ++p)
2759                         *p = tolower(*p);
2760         }
2761
2762         return 0;
2763 }
2764
2765 static int wm_adsp_common_init(struct wm_adsp *dsp)
2766 {
2767         int ret;
2768
2769         ret = wm_adsp_create_name(dsp);
2770         if (ret)
2771                 return ret;
2772
2773         INIT_LIST_HEAD(&dsp->alg_regions);
2774         INIT_LIST_HEAD(&dsp->ctl_list);
2775         INIT_LIST_HEAD(&dsp->compr_list);
2776         INIT_LIST_HEAD(&dsp->buffer_list);
2777
2778         mutex_init(&dsp->pwr_lock);
2779
2780         return 0;
2781 }
2782
2783 int wm_adsp1_init(struct wm_adsp *dsp)
2784 {
2785         dsp->ops = &wm_adsp1_ops;
2786
2787         return wm_adsp_common_init(dsp);
2788 }
2789 EXPORT_SYMBOL_GPL(wm_adsp1_init);
2790
2791 int wm_adsp1_event(struct snd_soc_dapm_widget *w,
2792                    struct snd_kcontrol *kcontrol,
2793                    int event)
2794 {
2795         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2796         struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
2797         struct wm_adsp *dsp = &dsps[w->shift];
2798         struct wm_coeff_ctl *ctl;
2799         int ret;
2800         unsigned int val;
2801
2802         dsp->component = component;
2803
2804         mutex_lock(&dsp->pwr_lock);
2805
2806         switch (event) {
2807         case SND_SOC_DAPM_POST_PMU:
2808                 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2809                                    ADSP1_SYS_ENA, ADSP1_SYS_ENA);
2810
2811                 /*
2812                  * For simplicity set the DSP clock rate to be the
2813                  * SYSCLK rate rather than making it configurable.
2814                  */
2815                 if (dsp->sysclk_reg) {
2816                         ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
2817                         if (ret != 0) {
2818                                 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
2819                                 ret);
2820                                 goto err_mutex;
2821                         }
2822
2823                         val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift;
2824
2825                         ret = regmap_update_bits(dsp->regmap,
2826                                                  dsp->base + ADSP1_CONTROL_31,
2827                                                  ADSP1_CLK_SEL_MASK, val);
2828                         if (ret != 0) {
2829                                 adsp_err(dsp, "Failed to set clock rate: %d\n",
2830                                          ret);
2831                                 goto err_mutex;
2832                         }
2833                 }
2834
2835                 ret = wm_adsp_load(dsp);
2836                 if (ret != 0)
2837                         goto err_ena;
2838
2839                 ret = wm_adsp1_setup_algs(dsp);
2840                 if (ret != 0)
2841                         goto err_ena;
2842
2843                 ret = wm_adsp_load_coeff(dsp);
2844                 if (ret != 0)
2845                         goto err_ena;
2846
2847                 /* Initialize caches for enabled and unset controls */
2848                 ret = wm_coeff_init_control_caches(dsp);
2849                 if (ret != 0)
2850                         goto err_ena;
2851
2852                 /* Sync set controls */
2853                 ret = wm_coeff_sync_controls(dsp);
2854                 if (ret != 0)
2855                         goto err_ena;
2856
2857                 dsp->booted = true;
2858
2859                 /* Start the core running */
2860                 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2861                                    ADSP1_CORE_ENA | ADSP1_START,
2862                                    ADSP1_CORE_ENA | ADSP1_START);
2863
2864                 dsp->running = true;
2865                 break;
2866
2867         case SND_SOC_DAPM_PRE_PMD:
2868                 dsp->running = false;
2869                 dsp->booted = false;
2870
2871                 /* Halt the core */
2872                 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2873                                    ADSP1_CORE_ENA | ADSP1_START, 0);
2874
2875                 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
2876                                    ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
2877
2878                 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2879                                    ADSP1_SYS_ENA, 0);
2880
2881                 list_for_each_entry(ctl, &dsp->ctl_list, list)
2882                         ctl->enabled = 0;
2883
2884
2885                 wm_adsp_free_alg_regions(dsp);
2886                 break;
2887
2888         default:
2889                 break;
2890         }
2891
2892         mutex_unlock(&dsp->pwr_lock);
2893
2894         return 0;
2895
2896 err_ena:
2897         regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2898                            ADSP1_SYS_ENA, 0);
2899 err_mutex:
2900         mutex_unlock(&dsp->pwr_lock);
2901
2902         return ret;
2903 }
2904 EXPORT_SYMBOL_GPL(wm_adsp1_event);
2905
2906 static int wm_adsp2v2_enable_core(struct wm_adsp *dsp)
2907 {
2908         unsigned int val;
2909         int ret, count;
2910
2911         /* Wait for the RAM to start, should be near instantaneous */
2912         for (count = 0; count < 10; ++count) {
2913                 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val);
2914                 if (ret != 0)
2915                         return ret;
2916
2917                 if (val & ADSP2_RAM_RDY)
2918                         break;
2919
2920                 usleep_range(250, 500);
2921         }
2922
2923         if (!(val & ADSP2_RAM_RDY)) {
2924                 adsp_err(dsp, "Failed to start DSP RAM\n");
2925                 return -EBUSY;
2926         }
2927
2928         adsp_dbg(dsp, "RAM ready after %d polls\n", count);
2929
2930         return 0;
2931 }
2932
2933 static int wm_adsp2_enable_core(struct wm_adsp *dsp)
2934 {
2935         int ret;
2936
2937         ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL,
2938                                        ADSP2_SYS_ENA, ADSP2_SYS_ENA);
2939         if (ret != 0)
2940                 return ret;
2941
2942         return wm_adsp2v2_enable_core(dsp);
2943 }
2944
2945 static int wm_adsp2_lock(struct wm_adsp *dsp, unsigned int lock_regions)
2946 {
2947         struct regmap *regmap = dsp->regmap;
2948         unsigned int code0, code1, lock_reg;
2949
2950         if (!(lock_regions & WM_ADSP2_REGION_ALL))
2951                 return 0;
2952
2953         lock_regions &= WM_ADSP2_REGION_ALL;
2954         lock_reg = dsp->base + ADSP2_LOCK_REGION_1_LOCK_REGION_0;
2955
2956         while (lock_regions) {
2957                 code0 = code1 = 0;
2958                 if (lock_regions & BIT(0)) {
2959                         code0 = ADSP2_LOCK_CODE_0;
2960                         code1 = ADSP2_LOCK_CODE_1;
2961                 }
2962                 if (lock_regions & BIT(1)) {
2963                         code0 |= ADSP2_LOCK_CODE_0 << ADSP2_LOCK_REGION_SHIFT;
2964                         code1 |= ADSP2_LOCK_CODE_1 << ADSP2_LOCK_REGION_SHIFT;
2965                 }
2966                 regmap_write(regmap, lock_reg, code0);
2967                 regmap_write(regmap, lock_reg, code1);
2968                 lock_regions >>= 2;
2969                 lock_reg += 2;
2970         }
2971
2972         return 0;
2973 }
2974
2975 static int wm_adsp2_enable_memory(struct wm_adsp *dsp)
2976 {
2977         return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2978                                   ADSP2_MEM_ENA, ADSP2_MEM_ENA);
2979 }
2980
2981 static void wm_adsp2_disable_memory(struct wm_adsp *dsp)
2982 {
2983         regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2984                            ADSP2_MEM_ENA, 0);
2985 }
2986
2987 static void wm_adsp2_disable_core(struct wm_adsp *dsp)
2988 {
2989         regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2990         regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2991         regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
2992
2993         regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2994                            ADSP2_SYS_ENA, 0);
2995 }
2996
2997 static void wm_adsp2v2_disable_core(struct wm_adsp *dsp)
2998 {
2999         regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
3000         regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
3001         regmap_write(dsp->regmap, dsp->base + ADSP2V2_WDMA_CONFIG_2, 0);
3002 }
3003
3004 static void wm_adsp_boot_work(struct work_struct *work)
3005 {
3006         struct wm_adsp *dsp = container_of(work,
3007                                            struct wm_adsp,
3008                                            boot_work);
3009         int ret;
3010
3011         mutex_lock(&dsp->pwr_lock);
3012
3013         if (dsp->ops->enable_memory) {
3014                 ret = dsp->ops->enable_memory(dsp);
3015                 if (ret != 0)
3016                         goto err_mutex;
3017         }
3018
3019         if (dsp->ops->enable_core) {
3020                 ret = dsp->ops->enable_core(dsp);
3021                 if (ret != 0)
3022                         goto err_mem;
3023         }
3024
3025         ret = wm_adsp_load(dsp);
3026         if (ret != 0)
3027                 goto err_ena;
3028
3029         ret = dsp->ops->setup_algs(dsp);
3030         if (ret != 0)
3031                 goto err_ena;
3032
3033         ret = wm_adsp_load_coeff(dsp);
3034         if (ret != 0)
3035                 goto err_ena;
3036
3037         /* Initialize caches for enabled and unset controls */
3038         ret = wm_coeff_init_control_caches(dsp);
3039         if (ret != 0)
3040                 goto err_ena;
3041
3042         if (dsp->ops->disable_core)
3043                 dsp->ops->disable_core(dsp);
3044
3045         dsp->booted = true;
3046
3047         mutex_unlock(&dsp->pwr_lock);
3048
3049         return;
3050
3051 err_ena:
3052         if (dsp->ops->disable_core)
3053                 dsp->ops->disable_core(dsp);
3054 err_mem:
3055         if (dsp->ops->disable_memory)
3056                 dsp->ops->disable_memory(dsp);
3057 err_mutex:
3058         mutex_unlock(&dsp->pwr_lock);
3059 }
3060
3061 static int wm_halo_configure_mpu(struct wm_adsp *dsp, unsigned int lock_regions)
3062 {
3063         struct reg_sequence config[] = {
3064                 { dsp->base + HALO_MPU_LOCK_CONFIG,     0x5555 },
3065                 { dsp->base + HALO_MPU_LOCK_CONFIG,     0xAAAA },
3066                 { dsp->base + HALO_MPU_XMEM_ACCESS_0,   0xFFFFFFFF },
3067                 { dsp->base + HALO_MPU_YMEM_ACCESS_0,   0xFFFFFFFF },
3068                 { dsp->base + HALO_MPU_WINDOW_ACCESS_0, lock_regions },
3069                 { dsp->base + HALO_MPU_XREG_ACCESS_0,   lock_regions },
3070                 { dsp->base + HALO_MPU_YREG_ACCESS_0,   lock_regions },
3071                 { dsp->base + HALO_MPU_XMEM_ACCESS_1,   0xFFFFFFFF },
3072                 { dsp->base + HALO_MPU_YMEM_ACCESS_1,   0xFFFFFFFF },
3073                 { dsp->base + HALO_MPU_WINDOW_ACCESS_1, lock_regions },
3074                 { dsp->base + HALO_MPU_XREG_ACCESS_1,   lock_regions },
3075                 { dsp->base + HALO_MPU_YREG_ACCESS_1,   lock_regions },
3076                 { dsp->base + HALO_MPU_XMEM_ACCESS_2,   0xFFFFFFFF },
3077                 { dsp->base + HALO_MPU_YMEM_ACCESS_2,   0xFFFFFFFF },
3078                 { dsp->base + HALO_MPU_WINDOW_ACCESS_2, lock_regions },
3079                 { dsp->base + HALO_MPU_XREG_ACCESS_2,   lock_regions },
3080                 { dsp->base + HALO_MPU_YREG_ACCESS_2,   lock_regions },
3081                 { dsp->base + HALO_MPU_XMEM_ACCESS_3,   0xFFFFFFFF },
3082                 { dsp->base + HALO_MPU_YMEM_ACCESS_3,   0xFFFFFFFF },
3083                 { dsp->base + HALO_MPU_WINDOW_ACCESS_3, lock_regions },
3084                 { dsp->base + HALO_MPU_XREG_ACCESS_3,   lock_regions },
3085                 { dsp->base + HALO_MPU_YREG_ACCESS_3,   lock_regions },
3086                 { dsp->base + HALO_MPU_LOCK_CONFIG,     0 },
3087         };
3088
3089         return regmap_multi_reg_write(dsp->regmap, config, ARRAY_SIZE(config));
3090 }
3091
3092 int wm_adsp2_set_dspclk(struct snd_soc_dapm_widget *w, unsigned int freq)
3093 {
3094         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
3095         struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
3096         struct wm_adsp *dsp = &dsps[w->shift];
3097         int ret;
3098
3099         ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CLOCKING,
3100                                  ADSP2_CLK_SEL_MASK,
3101                                  freq << ADSP2_CLK_SEL_SHIFT);
3102         if (ret)
3103                 adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
3104
3105         return ret;
3106 }
3107 EXPORT_SYMBOL_GPL(wm_adsp2_set_dspclk);
3108
3109 int wm_adsp2_preloader_get(struct snd_kcontrol *kcontrol,
3110                            struct snd_ctl_elem_value *ucontrol)
3111 {
3112         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
3113         struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
3114         struct soc_mixer_control *mc =
3115                 (struct soc_mixer_control *)kcontrol->private_value;
3116         struct wm_adsp *dsp = &dsps[mc->shift - 1];
3117
3118         ucontrol->value.integer.value[0] = dsp->preloaded;
3119
3120         return 0;
3121 }
3122 EXPORT_SYMBOL_GPL(wm_adsp2_preloader_get);
3123
3124 int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol,
3125                            struct snd_ctl_elem_value *ucontrol)
3126 {
3127         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
3128         struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
3129         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3130         struct soc_mixer_control *mc =
3131                 (struct soc_mixer_control *)kcontrol->private_value;
3132         struct wm_adsp *dsp = &dsps[mc->shift - 1];
3133         char preload[32];
3134
3135         snprintf(preload, ARRAY_SIZE(preload), "%s Preload", dsp->name);
3136
3137         dsp->preloaded = ucontrol->value.integer.value[0];
3138
3139         if (ucontrol->value.integer.value[0])
3140                 snd_soc_component_force_enable_pin(component, preload);
3141         else
3142                 snd_soc_component_disable_pin(component, preload);
3143
3144         snd_soc_dapm_sync(dapm);
3145
3146         flush_work(&dsp->boot_work);
3147
3148         return 0;
3149 }
3150 EXPORT_SYMBOL_GPL(wm_adsp2_preloader_put);
3151
3152 static void wm_adsp_stop_watchdog(struct wm_adsp *dsp)
3153 {
3154         regmap_update_bits(dsp->regmap, dsp->base + ADSP2_WATCHDOG,
3155                            ADSP2_WDT_ENA_MASK, 0);
3156 }
3157
3158 static void wm_halo_stop_watchdog(struct wm_adsp *dsp)
3159 {
3160         regmap_update_bits(dsp->regmap, dsp->base + HALO_WDT_CONTROL,
3161                            HALO_WDT_EN_MASK, 0);
3162 }
3163
3164 int wm_adsp_early_event(struct snd_soc_dapm_widget *w,
3165                         struct snd_kcontrol *kcontrol, int event)
3166 {
3167         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
3168         struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
3169         struct wm_adsp *dsp = &dsps[w->shift];
3170         struct wm_coeff_ctl *ctl;
3171
3172         switch (event) {
3173         case SND_SOC_DAPM_PRE_PMU:
3174                 queue_work(system_unbound_wq, &dsp->boot_work);
3175                 break;
3176         case SND_SOC_DAPM_PRE_PMD:
3177                 mutex_lock(&dsp->pwr_lock);
3178
3179                 wm_adsp_debugfs_clear(dsp);
3180
3181                 dsp->fw_id = 0;
3182                 dsp->fw_id_version = 0;
3183
3184                 dsp->booted = false;
3185
3186                 if (dsp->ops->disable_memory)
3187                         dsp->ops->disable_memory(dsp);
3188
3189                 list_for_each_entry(ctl, &dsp->ctl_list, list)
3190                         ctl->enabled = 0;
3191
3192                 wm_adsp_free_alg_regions(dsp);
3193
3194                 mutex_unlock(&dsp->pwr_lock);
3195
3196                 adsp_dbg(dsp, "Shutdown complete\n");
3197                 break;
3198         default:
3199                 break;
3200         }
3201
3202         return 0;
3203 }
3204 EXPORT_SYMBOL_GPL(wm_adsp_early_event);
3205
3206 static int wm_adsp2_start_core(struct wm_adsp *dsp)
3207 {
3208         return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
3209                                  ADSP2_CORE_ENA | ADSP2_START,
3210                                  ADSP2_CORE_ENA | ADSP2_START);
3211 }
3212
3213 static void wm_adsp2_stop_core(struct wm_adsp *dsp)
3214 {
3215         regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
3216                            ADSP2_CORE_ENA | ADSP2_START, 0);
3217 }
3218
3219 int wm_adsp_event(struct snd_soc_dapm_widget *w,
3220                   struct snd_kcontrol *kcontrol, int event)
3221 {
3222         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
3223         struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
3224         struct wm_adsp *dsp = &dsps[w->shift];
3225         int ret;
3226
3227         switch (event) {
3228         case SND_SOC_DAPM_POST_PMU:
3229                 flush_work(&dsp->boot_work);
3230
3231                 mutex_lock(&dsp->pwr_lock);
3232
3233                 if (!dsp->booted) {
3234                         ret = -EIO;
3235                         goto err;
3236                 }
3237
3238                 if (dsp->ops->enable_core) {
3239                         ret = dsp->ops->enable_core(dsp);
3240                         if (ret != 0)
3241                                 goto err;
3242                 }
3243
3244                 /* Sync set controls */
3245                 ret = wm_coeff_sync_controls(dsp);
3246                 if (ret != 0)
3247                         goto err;
3248
3249                 if (dsp->ops->lock_memory) {
3250                         ret = dsp->ops->lock_memory(dsp, dsp->lock_regions);
3251                         if (ret != 0) {
3252                                 adsp_err(dsp, "Error configuring MPU: %d\n",
3253                                          ret);
3254                                 goto err;
3255                         }
3256                 }
3257
3258                 if (dsp->ops->start_core) {
3259                         ret = dsp->ops->start_core(dsp);
3260                         if (ret != 0)
3261                                 goto err;
3262                 }
3263
3264                 dsp->running = true;
3265
3266                 if (wm_adsp_fw[dsp->fw].num_caps != 0) {
3267                         ret = wm_adsp_buffer_init(dsp);
3268                         if (ret < 0)
3269                                 goto err;
3270                 }
3271
3272                 mutex_unlock(&dsp->pwr_lock);
3273                 break;
3274
3275         case SND_SOC_DAPM_PRE_PMD:
3276                 /* Tell the firmware to cleanup */
3277                 wm_adsp_signal_event_controls(dsp, WM_ADSP_FW_EVENT_SHUTDOWN);
3278
3279                 if (dsp->ops->stop_watchdog)
3280                         dsp->ops->stop_watchdog(dsp);
3281
3282                 /* Log firmware state, it can be useful for analysis */
3283                 if (dsp->ops->show_fw_status)
3284                         dsp->ops->show_fw_status(dsp);
3285
3286                 mutex_lock(&dsp->pwr_lock);
3287
3288                 dsp->running = false;
3289
3290                 if (dsp->ops->stop_core)
3291                         dsp->ops->stop_core(dsp);
3292                 if (dsp->ops->disable_core)
3293                         dsp->ops->disable_core(dsp);
3294
3295                 if (wm_adsp_fw[dsp->fw].num_caps != 0)
3296                         wm_adsp_buffer_free(dsp);
3297
3298                 dsp->fatal_error = false;
3299
3300                 mutex_unlock(&dsp->pwr_lock);
3301
3302                 adsp_dbg(dsp, "Execution stopped\n");
3303                 break;
3304
3305         default:
3306                 break;
3307         }
3308
3309         return 0;
3310 err:
3311         if (dsp->ops->stop_core)
3312                 dsp->ops->stop_core(dsp);
3313         if (dsp->ops->disable_core)
3314                 dsp->ops->disable_core(dsp);
3315         mutex_unlock(&dsp->pwr_lock);
3316         return ret;
3317 }
3318 EXPORT_SYMBOL_GPL(wm_adsp_event);
3319
3320 static int wm_halo_start_core(struct wm_adsp *dsp)
3321 {
3322         return regmap_update_bits(dsp->regmap,
3323                                   dsp->base + HALO_CCM_CORE_CONTROL,
3324                                   HALO_CORE_RESET | HALO_CORE_EN,
3325                                   HALO_CORE_RESET | HALO_CORE_EN);
3326 }
3327
3328 static void wm_halo_stop_core(struct wm_adsp *dsp)
3329 {
3330         regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL,
3331                            HALO_CORE_EN, 0);
3332
3333         /* reset halo core with CORE_SOFT_RESET */
3334         regmap_update_bits(dsp->regmap, dsp->base + HALO_CORE_SOFT_RESET,
3335                            HALO_CORE_SOFT_RESET_MASK, 1);
3336 }
3337
3338 int wm_adsp2_component_probe(struct wm_adsp *dsp, struct snd_soc_component *component)
3339 {
3340         char preload[32];
3341
3342         snprintf(preload, ARRAY_SIZE(preload), "%s Preload", dsp->name);
3343         snd_soc_component_disable_pin(component, preload);
3344
3345         wm_adsp2_init_debugfs(dsp, component);
3346
3347         dsp->component = component;
3348
3349         return 0;
3350 }
3351 EXPORT_SYMBOL_GPL(wm_adsp2_component_probe);
3352
3353 int wm_adsp2_component_remove(struct wm_adsp *dsp, struct snd_soc_component *component)
3354 {
3355         wm_adsp2_cleanup_debugfs(dsp);
3356
3357         return 0;
3358 }
3359 EXPORT_SYMBOL_GPL(wm_adsp2_component_remove);
3360
3361 int wm_adsp2_init(struct wm_adsp *dsp)
3362 {
3363         int ret;
3364
3365         ret = wm_adsp_common_init(dsp);
3366         if (ret)
3367                 return ret;
3368
3369         switch (dsp->rev) {
3370         case 0:
3371                 /*
3372                  * Disable the DSP memory by default when in reset for a small
3373                  * power saving.
3374                  */
3375                 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
3376                                          ADSP2_MEM_ENA, 0);
3377                 if (ret) {
3378                         adsp_err(dsp,
3379                                  "Failed to clear memory retention: %d\n", ret);
3380                         return ret;
3381                 }
3382
3383                 dsp->ops = &wm_adsp2_ops[0];
3384                 break;
3385         case 1:
3386                 dsp->ops = &wm_adsp2_ops[1];
3387                 break;
3388         default:
3389                 dsp->ops = &wm_adsp2_ops[2];
3390                 break;
3391         }
3392
3393         INIT_WORK(&dsp->boot_work, wm_adsp_boot_work);
3394
3395         return 0;
3396 }
3397 EXPORT_SYMBOL_GPL(wm_adsp2_init);
3398
3399 int wm_halo_init(struct wm_adsp *dsp)
3400 {
3401         int ret;
3402
3403         ret = wm_adsp_common_init(dsp);
3404         if (ret)
3405                 return ret;
3406
3407         dsp->ops = &wm_halo_ops;
3408
3409         INIT_WORK(&dsp->boot_work, wm_adsp_boot_work);
3410
3411         return 0;
3412 }
3413 EXPORT_SYMBOL_GPL(wm_halo_init);
3414
3415 void wm_adsp2_remove(struct wm_adsp *dsp)
3416 {
3417         struct wm_coeff_ctl *ctl;
3418
3419         while (!list_empty(&dsp->ctl_list)) {
3420                 ctl = list_first_entry(&dsp->ctl_list, struct wm_coeff_ctl,
3421                                         list);
3422                 list_del(&ctl->list);
3423                 wm_adsp_free_ctl_blk(ctl);
3424         }
3425 }
3426 EXPORT_SYMBOL_GPL(wm_adsp2_remove);
3427
3428 static inline int wm_adsp_compr_attached(struct wm_adsp_compr *compr)
3429 {
3430         return compr->buf != NULL;
3431 }
3432
3433 static int wm_adsp_compr_attach(struct wm_adsp_compr *compr)
3434 {
3435         struct wm_adsp_compr_buf *buf = NULL, *tmp;
3436
3437         if (compr->dsp->fatal_error)
3438                 return -EINVAL;
3439
3440         list_for_each_entry(tmp, &compr->dsp->buffer_list, list) {
3441                 if (!tmp->name || !strcmp(compr->name, tmp->name)) {
3442                         buf = tmp;
3443                         break;
3444                 }
3445         }
3446
3447         if (!buf)
3448                 return -EINVAL;
3449
3450         compr->buf = buf;
3451         buf->compr = compr;
3452
3453         return 0;
3454 }
3455
3456 static void wm_adsp_compr_detach(struct wm_adsp_compr *compr)
3457 {
3458         if (!compr)
3459                 return;
3460
3461         /* Wake the poll so it can see buffer is no longer attached */
3462         if (compr->stream)
3463                 snd_compr_fragment_elapsed(compr->stream);
3464
3465         if (wm_adsp_compr_attached(compr)) {
3466                 compr->buf->compr = NULL;
3467                 compr->buf = NULL;
3468         }
3469 }
3470
3471 int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream)
3472 {
3473         struct wm_adsp_compr *compr, *tmp;
3474         struct snd_soc_pcm_runtime *rtd = stream->private_data;
3475         int ret = 0;
3476
3477         mutex_lock(&dsp->pwr_lock);
3478
3479         if (wm_adsp_fw[dsp->fw].num_caps == 0) {
3480                 adsp_err(dsp, "%s: Firmware does not support compressed API\n",
3481                          asoc_rtd_to_codec(rtd, 0)->name);
3482                 ret = -ENXIO;
3483                 goto out;
3484         }
3485
3486         if (wm_adsp_fw[dsp->fw].compr_direction != stream->direction) {
3487                 adsp_err(dsp, "%s: Firmware does not support stream direction\n",
3488                          asoc_rtd_to_codec(rtd, 0)->name);
3489                 ret = -EINVAL;
3490                 goto out;
3491         }
3492
3493         list_for_each_entry(tmp, &dsp->compr_list, list) {
3494                 if (!strcmp(tmp->name, asoc_rtd_to_codec(rtd, 0)->name)) {
3495                         adsp_err(dsp, "%s: Only a single stream supported per dai\n",
3496                                  asoc_rtd_to_codec(rtd, 0)->name);
3497                         ret = -EBUSY;
3498                         goto out;
3499                 }
3500         }
3501
3502         compr = kzalloc(sizeof(*compr), GFP_KERNEL);
3503         if (!compr) {
3504                 ret = -ENOMEM;
3505                 goto out;
3506         }
3507
3508         compr->dsp = dsp;
3509         compr->stream = stream;
3510         compr->name = asoc_rtd_to_codec(rtd, 0)->name;
3511
3512         list_add_tail(&compr->list, &dsp->compr_list);
3513
3514         stream->runtime->private_data = compr;
3515
3516 out:
3517         mutex_unlock(&dsp->pwr_lock);
3518
3519         return ret;
3520 }
3521 EXPORT_SYMBOL_GPL(wm_adsp_compr_open);
3522
3523 int wm_adsp_compr_free(struct snd_soc_component *component,
3524                        struct snd_compr_stream *stream)
3525 {
3526         struct wm_adsp_compr *compr = stream->runtime->private_data;
3527         struct wm_adsp *dsp = compr->dsp;
3528
3529         mutex_lock(&dsp->pwr_lock);
3530
3531         wm_adsp_compr_detach(compr);
3532         list_del(&compr->list);
3533
3534         kfree(compr->raw_buf);
3535         kfree(compr);
3536
3537         mutex_unlock(&dsp->pwr_lock);
3538
3539         return 0;
3540 }
3541 EXPORT_SYMBOL_GPL(wm_adsp_compr_free);
3542
3543 static int wm_adsp_compr_check_params(struct snd_compr_stream *stream,
3544                                       struct snd_compr_params *params)
3545 {
3546         struct wm_adsp_compr *compr = stream->runtime->private_data;
3547         struct wm_adsp *dsp = compr->dsp;
3548         const struct wm_adsp_fw_caps *caps;
3549         const struct snd_codec_desc *desc;
3550         int i, j;
3551
3552         if (params->buffer.fragment_size < WM_ADSP_MIN_FRAGMENT_SIZE ||
3553             params->buffer.fragment_size > WM_ADSP_MAX_FRAGMENT_SIZE ||
3554             params->buffer.fragments < WM_ADSP_MIN_FRAGMENTS ||
3555             params->buffer.fragments > WM_ADSP_MAX_FRAGMENTS ||
3556             params->buffer.fragment_size % WM_ADSP_DATA_WORD_SIZE) {
3557                 compr_err(compr, "Invalid buffer fragsize=%d fragments=%d\n",
3558                           params->buffer.fragment_size,
3559                           params->buffer.fragments);
3560
3561                 return -EINVAL;
3562         }
3563
3564         for (i = 0; i < wm_adsp_fw[dsp->fw].num_caps; i++) {
3565                 caps = &wm_adsp_fw[dsp->fw].caps[i];
3566                 desc = &caps->desc;
3567
3568                 if (caps->id != params->codec.id)
3569                         continue;
3570
3571                 if (stream->direction == SND_COMPRESS_PLAYBACK) {
3572                         if (desc->max_ch < params->codec.ch_out)
3573                                 continue;
3574                 } else {
3575                         if (desc->max_ch < params->codec.ch_in)
3576                                 continue;
3577                 }
3578
3579                 if (!(desc->formats & (1 << params->codec.format)))
3580                         continue;
3581
3582                 for (j = 0; j < desc->num_sample_rates; ++j)
3583                         if (desc->sample_rates[j] == params->codec.sample_rate)
3584                                 return 0;
3585         }
3586
3587         compr_err(compr, "Invalid params id=%u ch=%u,%u rate=%u fmt=%u\n",
3588                   params->codec.id, params->codec.ch_in, params->codec.ch_out,
3589                   params->codec.sample_rate, params->codec.format);
3590         return -EINVAL;
3591 }
3592
3593 static inline unsigned int wm_adsp_compr_frag_words(struct wm_adsp_compr *compr)
3594 {
3595         return compr->size.fragment_size / WM_ADSP_DATA_WORD_SIZE;
3596 }
3597
3598 int wm_adsp_compr_set_params(struct snd_soc_component *component,
3599                              struct snd_compr_stream *stream,
3600                              struct snd_compr_params *params)
3601 {
3602         struct wm_adsp_compr *compr = stream->runtime->private_data;
3603         unsigned int size;
3604         int ret;
3605
3606         ret = wm_adsp_compr_check_params(stream, params);
3607         if (ret)
3608                 return ret;
3609
3610         compr->size = params->buffer;
3611
3612         compr_dbg(compr, "fragment_size=%d fragments=%d\n",
3613                   compr->size.fragment_size, compr->size.fragments);
3614
3615         size = wm_adsp_compr_frag_words(compr) * sizeof(*compr->raw_buf);
3616         compr->raw_buf = kmalloc(size, GFP_DMA | GFP_KERNEL);
3617         if (!compr->raw_buf)
3618                 return -ENOMEM;
3619
3620         compr->sample_rate = params->codec.sample_rate;
3621
3622         return 0;
3623 }
3624 EXPORT_SYMBOL_GPL(wm_adsp_compr_set_params);
3625
3626 int wm_adsp_compr_get_caps(struct snd_soc_component *component,
3627                            struct snd_compr_stream *stream,
3628                            struct snd_compr_caps *caps)
3629 {
3630         struct wm_adsp_compr *compr = stream->runtime->private_data;
3631         int fw = compr->dsp->fw;
3632         int i;
3633
3634         if (wm_adsp_fw[fw].caps) {
3635                 for (i = 0; i < wm_adsp_fw[fw].num_caps; i++)
3636                         caps->codecs[i] = wm_adsp_fw[fw].caps[i].id;
3637
3638                 caps->num_codecs = i;
3639                 caps->direction = wm_adsp_fw[fw].compr_direction;
3640
3641                 caps->min_fragment_size = WM_ADSP_MIN_FRAGMENT_SIZE;
3642                 caps->max_fragment_size = WM_ADSP_MAX_FRAGMENT_SIZE;
3643                 caps->min_fragments = WM_ADSP_MIN_FRAGMENTS;
3644                 caps->max_fragments = WM_ADSP_MAX_FRAGMENTS;
3645         }
3646
3647         return 0;
3648 }
3649 EXPORT_SYMBOL_GPL(wm_adsp_compr_get_caps);
3650
3651 static int wm_adsp_read_raw_data_block(struct wm_adsp *dsp, int mem_type,
3652                                        unsigned int mem_addr,
3653                                        unsigned int num_words, __be32 *data)
3654 {
3655         struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
3656         unsigned int reg;
3657         int ret;
3658
3659         if (!mem)
3660                 return -EINVAL;
3661
3662         reg = dsp->ops->region_to_reg(mem, mem_addr);
3663
3664         ret = regmap_raw_read(dsp->regmap, reg, data,
3665                               sizeof(*data) * num_words);
3666         if (ret < 0)
3667                 return ret;
3668
3669         return 0;
3670 }
3671
3672 static inline int wm_adsp_read_data_word(struct wm_adsp *dsp, int mem_type,
3673                                          unsigned int mem_addr, u32 *data)
3674 {
3675         __be32 raw;
3676         int ret;
3677
3678         ret = wm_adsp_read_raw_data_block(dsp, mem_type, mem_addr, 1, &raw);
3679         if (ret < 0)
3680                 return ret;
3681
3682         *data = be32_to_cpu(raw) & 0x00ffffffu;
3683
3684         return 0;
3685 }
3686
3687 static int wm_adsp_write_data_word(struct wm_adsp *dsp, int mem_type,
3688                                    unsigned int mem_addr, u32 data)
3689 {
3690         struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
3691         __be32 val = cpu_to_be32(data & 0x00ffffffu);
3692         unsigned int reg;
3693
3694         if (!mem)
3695                 return -EINVAL;
3696
3697         reg = dsp->ops->region_to_reg(mem, mem_addr);
3698
3699         return regmap_raw_write(dsp->regmap, reg, &val, sizeof(val));
3700 }
3701
3702 static inline int wm_adsp_buffer_read(struct wm_adsp_compr_buf *buf,
3703                                       unsigned int field_offset, u32 *data)
3704 {
3705         return wm_adsp_read_data_word(buf->dsp, buf->host_buf_mem_type,
3706                                       buf->host_buf_ptr + field_offset, data);
3707 }
3708
3709 static inline int wm_adsp_buffer_write(struct wm_adsp_compr_buf *buf,
3710                                        unsigned int field_offset, u32 data)
3711 {
3712         return wm_adsp_write_data_word(buf->dsp, buf->host_buf_mem_type,
3713                                        buf->host_buf_ptr + field_offset, data);
3714 }
3715
3716 static void wm_adsp_remove_padding(u32 *buf, int nwords)
3717 {
3718         const __be32 *pack_in = (__be32 *)buf;
3719         u8 *pack_out = (u8 *)buf;
3720         int i;
3721
3722         /*
3723          * DSP words from the register map have pad bytes and the data bytes
3724          * are in swapped order. This swaps back to the original little-endian
3725          * order and strips the pad bytes.
3726          */
3727         for (i = 0; i < nwords; i++) {
3728                 u32 word = be32_to_cpu(*pack_in++);
3729                 *pack_out++ = (u8)word;
3730                 *pack_out++ = (u8)(word >> 8);
3731                 *pack_out++ = (u8)(word >> 16);
3732         }
3733 }
3734
3735 static int wm_adsp_buffer_populate(struct wm_adsp_compr_buf *buf)
3736 {
3737         const struct wm_adsp_fw_caps *caps = wm_adsp_fw[buf->dsp->fw].caps;
3738         struct wm_adsp_buffer_region *region;
3739         u32 offset = 0;
3740         int i, ret;
3741
3742         buf->regions = kcalloc(caps->num_regions, sizeof(*buf->regions),
3743                                GFP_KERNEL);
3744         if (!buf->regions)
3745                 return -ENOMEM;
3746
3747         for (i = 0; i < caps->num_regions; ++i) {
3748                 region = &buf->regions[i];
3749
3750                 region->offset = offset;
3751                 region->mem_type = caps->region_defs[i].mem_type;
3752
3753                 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].base_offset,
3754                                           &region->base_addr);
3755                 if (ret < 0)
3756                         return ret;
3757
3758                 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].size_offset,
3759                                           &offset);
3760                 if (ret < 0)
3761                         return ret;
3762
3763                 region->cumulative_size = offset;
3764
3765                 compr_dbg(buf,
3766                           "region=%d type=%d base=%08x off=%08x size=%08x\n",
3767                           i, region->mem_type, region->base_addr,
3768                           region->offset, region->cumulative_size);
3769         }
3770
3771         return 0;
3772 }
3773
3774 static void wm_adsp_buffer_clear(struct wm_adsp_compr_buf *buf)
3775 {
3776         buf->irq_count = 0xFFFFFFFF;
3777         buf->read_index = -1;
3778         buf->avail = 0;
3779 }
3780
3781 static struct wm_adsp_compr_buf *wm_adsp_buffer_alloc(struct wm_adsp *dsp)
3782 {
3783         struct wm_adsp_compr_buf *buf;
3784
3785         buf = kzalloc(sizeof(*buf), GFP_KERNEL);
3786         if (!buf)
3787                 return NULL;
3788
3789         buf->dsp = dsp;
3790
3791         wm_adsp_buffer_clear(buf);
3792
3793         list_add_tail(&buf->list, &dsp->buffer_list);
3794
3795         return buf;
3796 }
3797
3798 static int wm_adsp_buffer_parse_legacy(struct wm_adsp *dsp)
3799 {
3800         struct wm_adsp_alg_region *alg_region;
3801         struct wm_adsp_compr_buf *buf;
3802         u32 xmalg, addr, magic;
3803         int i, ret;
3804
3805         alg_region = wm_adsp_find_alg_region(dsp, WMFW_ADSP2_XM, dsp->fw_id);
3806         if (!alg_region) {
3807                 adsp_err(dsp, "No algorithm region found\n");
3808                 return -EINVAL;
3809         }
3810
3811         buf = wm_adsp_buffer_alloc(dsp);
3812         if (!buf)
3813                 return -ENOMEM;
3814
3815         xmalg = dsp->ops->sys_config_size / sizeof(__be32);
3816
3817         addr = alg_region->base + xmalg + ALG_XM_FIELD(magic);
3818         ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, &magic);
3819         if (ret < 0)
3820                 return ret;
3821
3822         if (magic != WM_ADSP_ALG_XM_STRUCT_MAGIC)
3823                 return -ENODEV;
3824
3825         addr = alg_region->base + xmalg + ALG_XM_FIELD(host_buf_ptr);
3826         for (i = 0; i < 5; ++i) {
3827                 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr,
3828                                              &buf->host_buf_ptr);
3829                 if (ret < 0)
3830                         return ret;
3831
3832                 if (buf->host_buf_ptr)
3833                         break;
3834
3835                 usleep_range(1000, 2000);
3836         }
3837
3838         if (!buf->host_buf_ptr)
3839                 return -EIO;
3840
3841         buf->host_buf_mem_type = WMFW_ADSP2_XM;
3842
3843         ret = wm_adsp_buffer_populate(buf);
3844         if (ret < 0)
3845                 return ret;
3846
3847         compr_dbg(buf, "legacy host_buf_ptr=%x\n", buf->host_buf_ptr);
3848
3849         return 0;
3850 }
3851
3852 static int wm_adsp_buffer_parse_coeff(struct wm_coeff_ctl *ctl)
3853 {
3854         struct wm_adsp_host_buf_coeff_v1 coeff_v1;
3855         struct wm_adsp_compr_buf *buf;
3856         unsigned int version;
3857         int ret, i;
3858
3859         for (i = 0; i < 5; ++i) {
3860                 ret = wm_coeff_read_ctrl(ctl, &coeff_v1, sizeof(coeff_v1));
3861                 if (ret < 0)
3862                         return ret;
3863
3864                 if (coeff_v1.host_buf_ptr)
3865                         break;
3866
3867                 usleep_range(1000, 2000);
3868         }
3869
3870         if (!coeff_v1.host_buf_ptr) {
3871                 adsp_err(ctl->dsp, "Failed to acquire host buffer\n");
3872                 return -EIO;
3873         }
3874
3875         buf = wm_adsp_buffer_alloc(ctl->dsp);
3876         if (!buf)
3877                 return -ENOMEM;
3878
3879         buf->host_buf_mem_type = ctl->alg_region.type;
3880         buf->host_buf_ptr = be32_to_cpu(coeff_v1.host_buf_ptr);
3881
3882         ret = wm_adsp_buffer_populate(buf);
3883         if (ret < 0)
3884                 return ret;
3885
3886         /*
3887          * v0 host_buffer coefficients didn't have versioning, so if the
3888          * control is one word, assume version 0.
3889          */
3890         if (ctl->len == 4) {
3891                 compr_dbg(buf, "host_buf_ptr=%x\n", buf->host_buf_ptr);
3892                 return 0;
3893         }
3894
3895         version = be32_to_cpu(coeff_v1.versions) & HOST_BUF_COEFF_COMPAT_VER_MASK;
3896         version >>= HOST_BUF_COEFF_COMPAT_VER_SHIFT;
3897
3898         if (version > HOST_BUF_COEFF_SUPPORTED_COMPAT_VER) {
3899                 adsp_err(ctl->dsp,
3900                          "Host buffer coeff ver %u > supported version %u\n",
3901                          version, HOST_BUF_COEFF_SUPPORTED_COMPAT_VER);
3902                 return -EINVAL;
3903         }
3904
3905         wm_adsp_remove_padding((u32 *)&coeff_v1.name, ARRAY_SIZE(coeff_v1.name));
3906
3907         buf->name = kasprintf(GFP_KERNEL, "%s-dsp-%s", ctl->dsp->part,
3908                               (char *)&coeff_v1.name);
3909
3910         compr_dbg(buf, "host_buf_ptr=%x coeff version %u\n",
3911                   buf->host_buf_ptr, version);
3912
3913         return version;
3914 }
3915
3916 static int wm_adsp_buffer_init(struct wm_adsp *dsp)
3917 {
3918         struct wm_coeff_ctl *ctl;
3919         int ret;
3920
3921         list_for_each_entry(ctl, &dsp->ctl_list, list) {
3922                 if (ctl->type != WMFW_CTL_TYPE_HOST_BUFFER)
3923                         continue;
3924
3925                 if (!ctl->enabled)
3926                         continue;
3927
3928                 ret = wm_adsp_buffer_parse_coeff(ctl);
3929                 if (ret < 0) {
3930                         adsp_err(dsp, "Failed to parse coeff: %d\n", ret);
3931                         goto error;
3932                 } else if (ret == 0) {
3933                         /* Only one buffer supported for version 0 */
3934                         return 0;
3935                 }
3936         }
3937
3938         if (list_empty(&dsp->buffer_list)) {
3939                 /* Fall back to legacy support */
3940                 ret = wm_adsp_buffer_parse_legacy(dsp);
3941                 if (ret) {
3942                         adsp_err(dsp, "Failed to parse legacy: %d\n", ret);
3943                         goto error;
3944                 }
3945         }
3946
3947         return 0;
3948
3949 error:
3950         wm_adsp_buffer_free(dsp);
3951         return ret;
3952 }
3953
3954 static int wm_adsp_buffer_free(struct wm_adsp *dsp)
3955 {
3956         struct wm_adsp_compr_buf *buf, *tmp;
3957
3958         list_for_each_entry_safe(buf, tmp, &dsp->buffer_list, list) {
3959                 wm_adsp_compr_detach(buf->compr);
3960
3961                 kfree(buf->name);
3962                 kfree(buf->regions);
3963                 list_del(&buf->list);
3964                 kfree(buf);
3965         }
3966
3967         return 0;
3968 }
3969
3970 static int wm_adsp_buffer_get_error(struct wm_adsp_compr_buf *buf)
3971 {
3972         int ret;
3973
3974         ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(error), &buf->error);
3975         if (ret < 0) {
3976                 compr_err(buf, "Failed to check buffer error: %d\n", ret);
3977                 return ret;
3978         }
3979         if (buf->error != 0) {
3980                 compr_err(buf, "Buffer error occurred: %d\n", buf->error);
3981                 return -EIO;
3982         }
3983
3984         return 0;
3985 }
3986
3987 int wm_adsp_compr_trigger(struct snd_soc_component *component,
3988                           struct snd_compr_stream *stream, int cmd)
3989 {
3990         struct wm_adsp_compr *compr = stream->runtime->private_data;
3991         struct wm_adsp *dsp = compr->dsp;
3992         int ret = 0;
3993
3994         compr_dbg(compr, "Trigger: %d\n", cmd);
3995
3996         mutex_lock(&dsp->pwr_lock);
3997
3998         switch (cmd) {
3999         case SNDRV_PCM_TRIGGER_START:
4000                 if (!wm_adsp_compr_attached(compr)) {
4001                         ret = wm_adsp_compr_attach(compr);
4002                         if (ret < 0) {
4003                                 compr_err(compr, "Failed to link buffer and stream: %d\n",
4004                                           ret);
4005                                 break;
4006                         }
4007                 }
4008
4009                 ret = wm_adsp_buffer_get_error(compr->buf);
4010                 if (ret < 0)
4011                         break;
4012
4013                 /* Trigger the IRQ at one fragment of data */
4014                 ret = wm_adsp_buffer_write(compr->buf,
4015                                            HOST_BUFFER_FIELD(high_water_mark),
4016                                            wm_adsp_compr_frag_words(compr));
4017                 if (ret < 0) {
4018                         compr_err(compr, "Failed to set high water mark: %d\n",
4019                                   ret);
4020                         break;
4021                 }
4022                 break;
4023         case SNDRV_PCM_TRIGGER_STOP:
4024                 if (wm_adsp_compr_attached(compr))
4025                         wm_adsp_buffer_clear(compr->buf);
4026                 break;
4027         default:
4028                 ret = -EINVAL;
4029                 break;
4030         }
4031
4032         mutex_unlock(&dsp->pwr_lock);
4033
4034         return ret;
4035 }
4036 EXPORT_SYMBOL_GPL(wm_adsp_compr_trigger);
4037
4038 static inline int wm_adsp_buffer_size(struct wm_adsp_compr_buf *buf)
4039 {
4040         int last_region = wm_adsp_fw[buf->dsp->fw].caps->num_regions - 1;
4041
4042         return buf->regions[last_region].cumulative_size;
4043 }
4044
4045 static int wm_adsp_buffer_update_avail(struct wm_adsp_compr_buf *buf)
4046 {
4047         u32 next_read_index, next_write_index;
4048         int write_index, read_index, avail;
4049         int ret;
4050
4051         /* Only sync read index if we haven't already read a valid index */
4052         if (buf->read_index < 0) {
4053                 ret = wm_adsp_buffer_read(buf,
4054                                 HOST_BUFFER_FIELD(next_read_index),
4055                                 &next_read_index);
4056                 if (ret < 0)
4057                         return ret;
4058
4059                 read_index = sign_extend32(next_read_index, 23);
4060
4061                 if (read_index < 0) {
4062                         compr_dbg(buf, "Avail check on unstarted stream\n");
4063                         return 0;
4064                 }
4065
4066                 buf->read_index = read_index;
4067         }
4068
4069         ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(next_write_index),
4070                         &next_write_index);
4071         if (ret < 0)
4072                 return ret;
4073
4074         write_index = sign_extend32(next_write_index, 23);
4075
4076         avail = write_index - buf->read_index;
4077         if (avail < 0)
4078                 avail += wm_adsp_buffer_size(buf);
4079
4080         compr_dbg(buf, "readindex=0x%x, writeindex=0x%x, avail=%d\n",
4081                   buf->read_index, write_index, avail * WM_ADSP_DATA_WORD_SIZE);
4082
4083         buf->avail = avail;
4084
4085         return 0;
4086 }
4087
4088 int wm_adsp_compr_handle_irq(struct wm_adsp *dsp)
4089 {
4090         struct wm_adsp_compr_buf *buf;
4091         struct wm_adsp_compr *compr;
4092         int ret = 0;
4093
4094         mutex_lock(&dsp->pwr_lock);
4095
4096         if (list_empty(&dsp->buffer_list)) {
4097                 ret = -ENODEV;
4098                 goto out;
4099         }
4100
4101         adsp_dbg(dsp, "Handling buffer IRQ\n");
4102
4103         list_for_each_entry(buf, &dsp->buffer_list, list) {
4104                 compr = buf->compr;
4105
4106                 ret = wm_adsp_buffer_get_error(buf);
4107                 if (ret < 0)
4108                         goto out_notify; /* Wake poll to report error */
4109
4110                 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(irq_count),
4111                                           &buf->irq_count);
4112                 if (ret < 0) {
4113                         compr_err(buf, "Failed to get irq_count: %d\n", ret);
4114                         goto out;
4115                 }
4116
4117                 ret = wm_adsp_buffer_update_avail(buf);
4118                 if (ret < 0) {
4119                         compr_err(buf, "Error reading avail: %d\n", ret);
4120                         goto out;
4121                 }
4122
4123                 if (wm_adsp_fw[dsp->fw].voice_trigger && buf->irq_count == 2)
4124                         ret = WM_ADSP_COMPR_VOICE_TRIGGER;
4125
4126 out_notify:
4127                 if (compr && compr->stream)
4128                         snd_compr_fragment_elapsed(compr->stream);
4129         }
4130
4131 out:
4132         mutex_unlock(&dsp->pwr_lock);
4133
4134         return ret;
4135 }
4136 EXPORT_SYMBOL_GPL(wm_adsp_compr_handle_irq);
4137
4138 static int wm_adsp_buffer_reenable_irq(struct wm_adsp_compr_buf *buf)
4139 {
4140         if (buf->irq_count & 0x01)
4141                 return 0;
4142
4143         compr_dbg(buf, "Enable IRQ(0x%x) for next fragment\n", buf->irq_count);
4144
4145         buf->irq_count |= 0x01;
4146
4147         return wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(irq_ack),
4148                                     buf->irq_count);
4149 }
4150
4151 int wm_adsp_compr_pointer(struct snd_soc_component *component,
4152                           struct snd_compr_stream *stream,
4153                           struct snd_compr_tstamp *tstamp)
4154 {
4155         struct wm_adsp_compr *compr = stream->runtime->private_data;
4156         struct wm_adsp *dsp = compr->dsp;
4157         struct wm_adsp_compr_buf *buf;
4158         int ret = 0;
4159
4160         compr_dbg(compr, "Pointer request\n");
4161
4162         mutex_lock(&dsp->pwr_lock);
4163
4164         buf = compr->buf;
4165
4166         if (dsp->fatal_error || !buf || buf->error) {
4167                 snd_compr_stop_error(stream, SNDRV_PCM_STATE_XRUN);
4168                 ret = -EIO;
4169                 goto out;
4170         }
4171
4172         if (buf->avail < wm_adsp_compr_frag_words(compr)) {
4173                 ret = wm_adsp_buffer_update_avail(buf);
4174                 if (ret < 0) {
4175                         compr_err(compr, "Error reading avail: %d\n", ret);
4176                         goto out;
4177                 }
4178
4179                 /*
4180                  * If we really have less than 1 fragment available tell the
4181                  * DSP to inform us once a whole fragment is available.
4182                  */
4183                 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
4184                         ret = wm_adsp_buffer_get_error(buf);
4185                         if (ret < 0) {
4186                                 if (buf->error)
4187                                         snd_compr_stop_error(stream,
4188                                                         SNDRV_PCM_STATE_XRUN);
4189                                 goto out;
4190                         }
4191
4192                         ret = wm_adsp_buffer_reenable_irq(buf);
4193                         if (ret < 0) {
4194                                 compr_err(compr, "Failed to re-enable buffer IRQ: %d\n",
4195                                           ret);
4196                                 goto out;
4197                         }
4198                 }
4199         }
4200
4201         tstamp->copied_total = compr->copied_total;
4202         tstamp->copied_total += buf->avail * WM_ADSP_DATA_WORD_SIZE;
4203         tstamp->sampling_rate = compr->sample_rate;
4204
4205 out:
4206         mutex_unlock(&dsp->pwr_lock);
4207
4208         return ret;
4209 }
4210 EXPORT_SYMBOL_GPL(wm_adsp_compr_pointer);
4211
4212 static int wm_adsp_buffer_capture_block(struct wm_adsp_compr *compr, int target)
4213 {
4214         struct wm_adsp_compr_buf *buf = compr->buf;
4215         unsigned int adsp_addr;
4216         int mem_type, nwords, max_read;
4217         int i, ret;
4218
4219         /* Calculate read parameters */
4220         for (i = 0; i < wm_adsp_fw[buf->dsp->fw].caps->num_regions; ++i)
4221                 if (buf->read_index < buf->regions[i].cumulative_size)
4222                         break;
4223
4224         if (i == wm_adsp_fw[buf->dsp->fw].caps->num_regions)
4225                 return -EINVAL;
4226
4227         mem_type = buf->regions[i].mem_type;
4228         adsp_addr = buf->regions[i].base_addr +
4229                     (buf->read_index - buf->regions[i].offset);
4230
4231         max_read = wm_adsp_compr_frag_words(compr);
4232         nwords = buf->regions[i].cumulative_size - buf->read_index;
4233
4234         if (nwords > target)
4235                 nwords = target;
4236         if (nwords > buf->avail)
4237                 nwords = buf->avail;
4238         if (nwords > max_read)
4239                 nwords = max_read;
4240         if (!nwords)
4241                 return 0;
4242
4243         /* Read data from DSP */
4244         ret = wm_adsp_read_raw_data_block(buf->dsp, mem_type, adsp_addr,
4245                                           nwords, (__be32 *)compr->raw_buf);
4246         if (ret < 0)
4247                 return ret;
4248
4249         wm_adsp_remove_padding(compr->raw_buf, nwords);
4250
4251         /* update read index to account for words read */
4252         buf->read_index += nwords;
4253         if (buf->read_index == wm_adsp_buffer_size(buf))
4254                 buf->read_index = 0;
4255
4256         ret = wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(next_read_index),
4257                                    buf->read_index);
4258         if (ret < 0)
4259                 return ret;
4260
4261         /* update avail to account for words read */
4262         buf->avail -= nwords;
4263
4264         return nwords;
4265 }
4266
4267 static int wm_adsp_compr_read(struct wm_adsp_compr *compr,
4268                               char __user *buf, size_t count)
4269 {
4270         struct wm_adsp *dsp = compr->dsp;
4271         int ntotal = 0;
4272         int nwords, nbytes;
4273
4274         compr_dbg(compr, "Requested read of %zu bytes\n", count);
4275
4276         if (dsp->fatal_error || !compr->buf || compr->buf->error) {
4277                 snd_compr_stop_error(compr->stream, SNDRV_PCM_STATE_XRUN);
4278                 return -EIO;
4279         }
4280
4281         count /= WM_ADSP_DATA_WORD_SIZE;
4282
4283         do {
4284                 nwords = wm_adsp_buffer_capture_block(compr, count);
4285                 if (nwords < 0) {
4286                         compr_err(compr, "Failed to capture block: %d\n",
4287                                   nwords);
4288                         return nwords;
4289                 }
4290
4291                 nbytes = nwords * WM_ADSP_DATA_WORD_SIZE;
4292
4293                 compr_dbg(compr, "Read %d bytes\n", nbytes);
4294
4295                 if (copy_to_user(buf + ntotal, compr->raw_buf, nbytes)) {
4296                         compr_err(compr, "Failed to copy data to user: %d, %d\n",
4297                                   ntotal, nbytes);
4298                         return -EFAULT;
4299                 }
4300
4301                 count -= nwords;
4302                 ntotal += nbytes;
4303         } while (nwords > 0 && count > 0);
4304
4305         compr->copied_total += ntotal;
4306
4307         return ntotal;
4308 }
4309
4310 int wm_adsp_compr_copy(struct snd_soc_component *component,
4311                        struct snd_compr_stream *stream, char __user *buf,
4312                        size_t count)
4313 {
4314         struct wm_adsp_compr *compr = stream->runtime->private_data;
4315         struct wm_adsp *dsp = compr->dsp;
4316         int ret;
4317
4318         mutex_lock(&dsp->pwr_lock);
4319
4320         if (stream->direction == SND_COMPRESS_CAPTURE)
4321                 ret = wm_adsp_compr_read(compr, buf, count);
4322         else
4323                 ret = -ENOTSUPP;
4324
4325         mutex_unlock(&dsp->pwr_lock);
4326
4327         return ret;
4328 }
4329 EXPORT_SYMBOL_GPL(wm_adsp_compr_copy);
4330
4331 static void wm_adsp_fatal_error(struct wm_adsp *dsp)
4332 {
4333         struct wm_adsp_compr *compr;
4334
4335         dsp->fatal_error = true;
4336
4337         list_for_each_entry(compr, &dsp->compr_list, list) {
4338                 if (compr->stream)
4339                         snd_compr_fragment_elapsed(compr->stream);
4340         }
4341 }
4342
4343 irqreturn_t wm_adsp2_bus_error(int irq, void *data)
4344 {
4345         struct wm_adsp *dsp = (struct wm_adsp *)data;
4346         unsigned int val;
4347         struct regmap *regmap = dsp->regmap;
4348         int ret = 0;
4349
4350         mutex_lock(&dsp->pwr_lock);
4351
4352         ret = regmap_read(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, &val);
4353         if (ret) {
4354                 adsp_err(dsp,
4355                         "Failed to read Region Lock Ctrl register: %d\n", ret);
4356                 goto error;
4357         }
4358
4359         if (val & ADSP2_WDT_TIMEOUT_STS_MASK) {
4360                 adsp_err(dsp, "watchdog timeout error\n");
4361                 dsp->ops->stop_watchdog(dsp);
4362                 wm_adsp_fatal_error(dsp);
4363         }
4364
4365         if (val & (ADSP2_ADDR_ERR_MASK | ADSP2_REGION_LOCK_ERR_MASK)) {
4366                 if (val & ADSP2_ADDR_ERR_MASK)
4367                         adsp_err(dsp, "bus error: address error\n");
4368                 else
4369                         adsp_err(dsp, "bus error: region lock error\n");
4370
4371                 ret = regmap_read(regmap, dsp->base + ADSP2_BUS_ERR_ADDR, &val);
4372                 if (ret) {
4373                         adsp_err(dsp,
4374                                  "Failed to read Bus Err Addr register: %d\n",
4375                                  ret);
4376                         goto error;
4377                 }
4378
4379                 adsp_err(dsp, "bus error address = 0x%x\n",
4380                          val & ADSP2_BUS_ERR_ADDR_MASK);
4381
4382                 ret = regmap_read(regmap,
4383                                   dsp->base + ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR,
4384                                   &val);
4385                 if (ret) {
4386                         adsp_err(dsp,
4387                                  "Failed to read Pmem Xmem Err Addr register: %d\n",
4388                                  ret);
4389                         goto error;
4390                 }
4391
4392                 adsp_err(dsp, "xmem error address = 0x%x\n",
4393                          val & ADSP2_XMEM_ERR_ADDR_MASK);
4394                 adsp_err(dsp, "pmem error address = 0x%x\n",
4395                          (val & ADSP2_PMEM_ERR_ADDR_MASK) >>
4396                          ADSP2_PMEM_ERR_ADDR_SHIFT);
4397         }
4398
4399         regmap_update_bits(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL,
4400                            ADSP2_CTRL_ERR_EINT, ADSP2_CTRL_ERR_EINT);
4401
4402 error:
4403         mutex_unlock(&dsp->pwr_lock);
4404
4405         return IRQ_HANDLED;
4406 }
4407 EXPORT_SYMBOL_GPL(wm_adsp2_bus_error);
4408
4409 irqreturn_t wm_halo_bus_error(int irq, void *data)
4410 {
4411         struct wm_adsp *dsp = (struct wm_adsp *)data;
4412         struct regmap *regmap = dsp->regmap;
4413         unsigned int fault[6];
4414         struct reg_sequence clear[] = {
4415                 { dsp->base + HALO_MPU_XM_VIO_STATUS,     0x0 },
4416                 { dsp->base + HALO_MPU_YM_VIO_STATUS,     0x0 },
4417                 { dsp->base + HALO_MPU_PM_VIO_STATUS,     0x0 },
4418         };
4419         int ret;
4420
4421         mutex_lock(&dsp->pwr_lock);
4422
4423         ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_1,
4424                           fault);
4425         if (ret) {
4426                 adsp_warn(dsp, "Failed to read AHB DEBUG_1: %d\n", ret);
4427                 goto exit_unlock;
4428         }
4429
4430         adsp_warn(dsp, "AHB: STATUS: 0x%x ADDR: 0x%x\n",
4431                   *fault & HALO_AHBM_FLAGS_ERR_MASK,
4432                   (*fault & HALO_AHBM_CORE_ERR_ADDR_MASK) >>
4433                   HALO_AHBM_CORE_ERR_ADDR_SHIFT);
4434
4435         ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_0,
4436                           fault);
4437         if (ret) {
4438                 adsp_warn(dsp, "Failed to read AHB DEBUG_0: %d\n", ret);
4439                 goto exit_unlock;
4440         }
4441
4442         adsp_warn(dsp, "AHB: SYS_ADDR: 0x%x\n", *fault);
4443
4444         ret = regmap_bulk_read(regmap, dsp->base + HALO_MPU_XM_VIO_ADDR,
4445                                fault, ARRAY_SIZE(fault));
4446         if (ret) {
4447                 adsp_warn(dsp, "Failed to read MPU fault info: %d\n", ret);
4448                 goto exit_unlock;
4449         }
4450
4451         adsp_warn(dsp, "XM: STATUS:0x%x ADDR:0x%x\n", fault[1], fault[0]);
4452         adsp_warn(dsp, "YM: STATUS:0x%x ADDR:0x%x\n", fault[3], fault[2]);
4453         adsp_warn(dsp, "PM: STATUS:0x%x ADDR:0x%x\n", fault[5], fault[4]);
4454
4455         ret = regmap_multi_reg_write(dsp->regmap, clear, ARRAY_SIZE(clear));
4456         if (ret)
4457                 adsp_warn(dsp, "Failed to clear MPU status: %d\n", ret);
4458
4459 exit_unlock:
4460         mutex_unlock(&dsp->pwr_lock);
4461
4462         return IRQ_HANDLED;
4463 }
4464 EXPORT_SYMBOL_GPL(wm_halo_bus_error);
4465
4466 irqreturn_t wm_halo_wdt_expire(int irq, void *data)
4467 {
4468         struct wm_adsp *dsp = data;
4469
4470         mutex_lock(&dsp->pwr_lock);
4471
4472         adsp_warn(dsp, "WDT Expiry Fault\n");
4473         dsp->ops->stop_watchdog(dsp);
4474         wm_adsp_fatal_error(dsp);
4475
4476         mutex_unlock(&dsp->pwr_lock);
4477
4478         return IRQ_HANDLED;
4479 }
4480 EXPORT_SYMBOL_GPL(wm_halo_wdt_expire);
4481
4482 static const struct wm_adsp_ops wm_adsp1_ops = {
4483         .validate_version = wm_adsp_validate_version,
4484         .parse_sizes = wm_adsp1_parse_sizes,
4485         .region_to_reg = wm_adsp_region_to_reg,
4486 };
4487
4488 static const struct wm_adsp_ops wm_adsp2_ops[] = {
4489         {
4490                 .sys_config_size = sizeof(struct wm_adsp_system_config_xm_hdr),
4491                 .parse_sizes = wm_adsp2_parse_sizes,
4492                 .validate_version = wm_adsp_validate_version,
4493                 .setup_algs = wm_adsp2_setup_algs,
4494                 .region_to_reg = wm_adsp_region_to_reg,
4495
4496                 .show_fw_status = wm_adsp2_show_fw_status,
4497
4498                 .enable_memory = wm_adsp2_enable_memory,
4499                 .disable_memory = wm_adsp2_disable_memory,
4500
4501                 .enable_core = wm_adsp2_enable_core,
4502                 .disable_core = wm_adsp2_disable_core,
4503
4504                 .start_core = wm_adsp2_start_core,
4505                 .stop_core = wm_adsp2_stop_core,
4506
4507         },
4508         {
4509                 .sys_config_size = sizeof(struct wm_adsp_system_config_xm_hdr),
4510                 .parse_sizes = wm_adsp2_parse_sizes,
4511                 .validate_version = wm_adsp_validate_version,
4512                 .setup_algs = wm_adsp2_setup_algs,
4513                 .region_to_reg = wm_adsp_region_to_reg,
4514
4515                 .show_fw_status = wm_adsp2v2_show_fw_status,
4516
4517                 .enable_memory = wm_adsp2_enable_memory,
4518                 .disable_memory = wm_adsp2_disable_memory,
4519                 .lock_memory = wm_adsp2_lock,
4520
4521                 .enable_core = wm_adsp2v2_enable_core,
4522                 .disable_core = wm_adsp2v2_disable_core,
4523
4524                 .start_core = wm_adsp2_start_core,
4525                 .stop_core = wm_adsp2_stop_core,
4526         },
4527         {
4528                 .sys_config_size = sizeof(struct wm_adsp_system_config_xm_hdr),
4529                 .parse_sizes = wm_adsp2_parse_sizes,
4530                 .validate_version = wm_adsp_validate_version,
4531                 .setup_algs = wm_adsp2_setup_algs,
4532                 .region_to_reg = wm_adsp_region_to_reg,
4533
4534                 .show_fw_status = wm_adsp2v2_show_fw_status,
4535                 .stop_watchdog = wm_adsp_stop_watchdog,
4536
4537                 .enable_memory = wm_adsp2_enable_memory,
4538                 .disable_memory = wm_adsp2_disable_memory,
4539                 .lock_memory = wm_adsp2_lock,
4540
4541                 .enable_core = wm_adsp2v2_enable_core,
4542                 .disable_core = wm_adsp2v2_disable_core,
4543
4544                 .start_core = wm_adsp2_start_core,
4545                 .stop_core = wm_adsp2_stop_core,
4546         },
4547 };
4548
4549 static const struct wm_adsp_ops wm_halo_ops = {
4550         .sys_config_size = sizeof(struct wm_halo_system_config_xm_hdr),
4551         .parse_sizes = wm_adsp2_parse_sizes,
4552         .validate_version = wm_halo_validate_version,
4553         .setup_algs = wm_halo_setup_algs,
4554         .region_to_reg = wm_halo_region_to_reg,
4555
4556         .show_fw_status = wm_halo_show_fw_status,
4557         .stop_watchdog = wm_halo_stop_watchdog,
4558
4559         .lock_memory = wm_halo_configure_mpu,
4560
4561         .start_core = wm_halo_start_core,
4562         .stop_core = wm_halo_stop_core,
4563 };
4564
4565 MODULE_LICENSE("GPL v2");