sound/soc/codecs/wm_adsp.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * wm_adsp.c  --  Wolfson ADSP support
   4  *
   5  * Copyright 2012 Wolfson Microelectronics plc
   6  *
   7  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   8  */
   9
  10 #include <linux/ctype.h>
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/init.h>
  14 #include <linux/delay.h>
  15 #include <linux/firmware.h>
  16 #include <linux/list.h>
  17 #include <linux/pm.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/regmap.h>
  20 #include <linux/regulator/consumer.h>
  21 #include <linux/slab.h>
  22 #include <linux/vmalloc.h>
  23 #include <linux/workqueue.h>
  24 #include <linux/debugfs.h>
  25 #include <sound/core.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/jack.h>
  30 #include <sound/initval.h>
  31 #include <sound/tlv.h>
  32
  33 #include "wm_adsp.h"
  34
  35 #define adsp_crit(_dsp, fmt, ...) \
  36         dev_crit(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
  37 #define adsp_err(_dsp, fmt, ...) \
  38         dev_err(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
  39 #define adsp_warn(_dsp, fmt, ...) \
  40         dev_warn(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
  41 #define adsp_info(_dsp, fmt, ...) \
  42         dev_info(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
  43 #define adsp_dbg(_dsp, fmt, ...) \
  44         dev_dbg(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
  45
  46 #define compr_err(_obj, fmt, ...) \
  47         adsp_err(_obj->dsp, "%s: " fmt, _obj->name ? _obj->name : "legacy", \
  48                  ##__VA_ARGS__)
  49 #define compr_dbg(_obj, fmt, ...) \
  50         adsp_dbg(_obj->dsp, "%s: " fmt, _obj->name ? _obj->name : "legacy", \
  51                  ##__VA_ARGS__)
  52
  53 #define ADSP1_CONTROL_1                   0x00
  54 #define ADSP1_CONTROL_2                   0x02
  55 #define ADSP1_CONTROL_3                   0x03
  56 #define ADSP1_CONTROL_4                   0x04
  57 #define ADSP1_CONTROL_5                   0x06
  58 #define ADSP1_CONTROL_6                   0x07
  59 #define ADSP1_CONTROL_7                   0x08
  60 #define ADSP1_CONTROL_8                   0x09
  61 #define ADSP1_CONTROL_9                   0x0A
  62 #define ADSP1_CONTROL_10                  0x0B
  63 #define ADSP1_CONTROL_11                  0x0C
  64 #define ADSP1_CONTROL_12                  0x0D
  65 #define ADSP1_CONTROL_13                  0x0F
  66 #define ADSP1_CONTROL_14                  0x10
  67 #define ADSP1_CONTROL_15                  0x11
  68 #define ADSP1_CONTROL_16                  0x12
  69 #define ADSP1_CONTROL_17                  0x13
  70 #define ADSP1_CONTROL_18                  0x14
  71 #define ADSP1_CONTROL_19                  0x16
  72 #define ADSP1_CONTROL_20                  0x17
  73 #define ADSP1_CONTROL_21                  0x18
  74 #define ADSP1_CONTROL_22                  0x1A
  75 #define ADSP1_CONTROL_23                  0x1B
  76 #define ADSP1_CONTROL_24                  0x1C
  77 #define ADSP1_CONTROL_25                  0x1E
  78 #define ADSP1_CONTROL_26                  0x20
  79 #define ADSP1_CONTROL_27                  0x21
  80 #define ADSP1_CONTROL_28                  0x22
  81 #define ADSP1_CONTROL_29                  0x23
  82 #define ADSP1_CONTROL_30                  0x24
  83 #define ADSP1_CONTROL_31                  0x26
  84
  85 /*
  86  * ADSP1 Control 19
  87  */
  88 #define ADSP1_WDMA_BUFFER_LENGTH_MASK     0x00FF  /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
  89 #define ADSP1_WDMA_BUFFER_LENGTH_SHIFT         0  /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
  90 #define ADSP1_WDMA_BUFFER_LENGTH_WIDTH         8  /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
  91
  92
  93 /*
  94  * ADSP1 Control 30
  95  */
  96 #define ADSP1_DBG_CLK_ENA                 0x0008  /* DSP1_DBG_CLK_ENA */
  97 #define ADSP1_DBG_CLK_ENA_MASK            0x0008  /* DSP1_DBG_CLK_ENA */
  98 #define ADSP1_DBG_CLK_ENA_SHIFT                3  /* DSP1_DBG_CLK_ENA */
  99 #define ADSP1_DBG_CLK_ENA_WIDTH                1  /* DSP1_DBG_CLK_ENA */
 100 #define ADSP1_SYS_ENA                     0x0004  /* DSP1_SYS_ENA */
 101 #define ADSP1_SYS_ENA_MASK                0x0004  /* DSP1_SYS_ENA */
 102 #define ADSP1_SYS_ENA_SHIFT                    2  /* DSP1_SYS_ENA */
 103 #define ADSP1_SYS_ENA_WIDTH                    1  /* DSP1_SYS_ENA */
 104 #define ADSP1_CORE_ENA                    0x0002  /* DSP1_CORE_ENA */
 105 #define ADSP1_CORE_ENA_MASK               0x0002  /* DSP1_CORE_ENA */
 106 #define ADSP1_CORE_ENA_SHIFT                   1  /* DSP1_CORE_ENA */
 107 #define ADSP1_CORE_ENA_WIDTH                   1  /* DSP1_CORE_ENA */
 108 #define ADSP1_START                       0x0001  /* DSP1_START */
 109 #define ADSP1_START_MASK                  0x0001  /* DSP1_START */
 110 #define ADSP1_START_SHIFT                      0  /* DSP1_START */
 111 #define ADSP1_START_WIDTH                      1  /* DSP1_START */
 112
 113 /*
 114  * ADSP1 Control 31
 115  */
 116 #define ADSP1_CLK_SEL_MASK                0x0007  /* CLK_SEL_ENA */
 117 #define ADSP1_CLK_SEL_SHIFT                    0  /* CLK_SEL_ENA */
 118 #define ADSP1_CLK_SEL_WIDTH                    3  /* CLK_SEL_ENA */
 119
 120 #define ADSP2_CONTROL                     0x0
 121 #define ADSP2_CLOCKING                    0x1
 122 #define ADSP2V2_CLOCKING                  0x2
 123 #define ADSP2_STATUS1                     0x4
 124 #define ADSP2_WDMA_CONFIG_1               0x30
 125 #define ADSP2_WDMA_CONFIG_2               0x31
 126 #define ADSP2V2_WDMA_CONFIG_2             0x32
 127 #define ADSP2_RDMA_CONFIG_1               0x34
 128
 129 #define ADSP2_SCRATCH0                    0x40
 130 #define ADSP2_SCRATCH1                    0x41
 131 #define ADSP2_SCRATCH2                    0x42
 132 #define ADSP2_SCRATCH3                    0x43
 133
 134 #define ADSP2V2_SCRATCH0_1                0x40
 135 #define ADSP2V2_SCRATCH2_3                0x42
 136
 137 /*
 138  * ADSP2 Control
 139  */
 140
 141 #define ADSP2_MEM_ENA                     0x0010  /* DSP1_MEM_ENA */
 142 #define ADSP2_MEM_ENA_MASK                0x0010  /* DSP1_MEM_ENA */
 143 #define ADSP2_MEM_ENA_SHIFT                    4  /* DSP1_MEM_ENA */
 144 #define ADSP2_MEM_ENA_WIDTH                    1  /* DSP1_MEM_ENA */
 145 #define ADSP2_SYS_ENA                     0x0004  /* DSP1_SYS_ENA */
 146 #define ADSP2_SYS_ENA_MASK                0x0004  /* DSP1_SYS_ENA */
 147 #define ADSP2_SYS_ENA_SHIFT                    2  /* DSP1_SYS_ENA */
 148 #define ADSP2_SYS_ENA_WIDTH                    1  /* DSP1_SYS_ENA */
 149 #define ADSP2_CORE_ENA                    0x0002  /* DSP1_CORE_ENA */
 150 #define ADSP2_CORE_ENA_MASK               0x0002  /* DSP1_CORE_ENA */
 151 #define ADSP2_CORE_ENA_SHIFT                   1  /* DSP1_CORE_ENA */
 152 #define ADSP2_CORE_ENA_WIDTH                   1  /* DSP1_CORE_ENA */
 153 #define ADSP2_START                       0x0001  /* DSP1_START */
 154 #define ADSP2_START_MASK                  0x0001  /* DSP1_START */
 155 #define ADSP2_START_SHIFT                      0  /* DSP1_START */
 156 #define ADSP2_START_WIDTH                      1  /* DSP1_START */
 157
 158 /*
 159  * ADSP2 clocking
 160  */
 161 #define ADSP2_CLK_SEL_MASK                0x0007  /* CLK_SEL_ENA */
 162 #define ADSP2_CLK_SEL_SHIFT                    0  /* CLK_SEL_ENA */
 163 #define ADSP2_CLK_SEL_WIDTH                    3  /* CLK_SEL_ENA */
 164
 165 /*
 166  * ADSP2V2 clocking
 167  */
 168 #define ADSP2V2_CLK_SEL_MASK             0x70000  /* CLK_SEL_ENA */
 169 #define ADSP2V2_CLK_SEL_SHIFT                 16  /* CLK_SEL_ENA */
 170 #define ADSP2V2_CLK_SEL_WIDTH                  3  /* CLK_SEL_ENA */
 171
 172 #define ADSP2V2_RATE_MASK                 0x7800  /* DSP_RATE */
 173 #define ADSP2V2_RATE_SHIFT                    11  /* DSP_RATE */
 174 #define ADSP2V2_RATE_WIDTH                     4  /* DSP_RATE */
 175
 176 /*
 177  * ADSP2 Status 1
 178  */
 179 #define ADSP2_RAM_RDY                     0x0001
 180 #define ADSP2_RAM_RDY_MASK                0x0001
 181 #define ADSP2_RAM_RDY_SHIFT                    0
 182 #define ADSP2_RAM_RDY_WIDTH                    1
 183
 184 /*
 185  * ADSP2 Lock support
 186  */
 187 #define ADSP2_LOCK_CODE_0                    0x5555
 188 #define ADSP2_LOCK_CODE_1                    0xAAAA
 189
 190 #define ADSP2_WATCHDOG                       0x0A
 191 #define ADSP2_BUS_ERR_ADDR                   0x52
 192 #define ADSP2_REGION_LOCK_STATUS             0x64
 193 #define ADSP2_LOCK_REGION_1_LOCK_REGION_0    0x66
 194 #define ADSP2_LOCK_REGION_3_LOCK_REGION_2    0x68
 195 #define ADSP2_LOCK_REGION_5_LOCK_REGION_4    0x6A
 196 #define ADSP2_LOCK_REGION_7_LOCK_REGION_6    0x6C
 197 #define ADSP2_LOCK_REGION_9_LOCK_REGION_8    0x6E
 198 #define ADSP2_LOCK_REGION_CTRL               0x7A
 199 #define ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR    0x7C
 200
 201 #define ADSP2_REGION_LOCK_ERR_MASK           0x8000
 202 #define ADSP2_SLAVE_ERR_MASK                 0x4000
 203 #define ADSP2_WDT_TIMEOUT_STS_MASK           0x2000
 204 #define ADSP2_CTRL_ERR_PAUSE_ENA             0x0002
 205 #define ADSP2_CTRL_ERR_EINT                  0x0001
 206
 207 #define ADSP2_BUS_ERR_ADDR_MASK              0x00FFFFFF
 208 #define ADSP2_XMEM_ERR_ADDR_MASK             0x0000FFFF
 209 #define ADSP2_PMEM_ERR_ADDR_MASK             0x7FFF0000
 210 #define ADSP2_PMEM_ERR_ADDR_SHIFT            16
 211 #define ADSP2_WDT_ENA_MASK                   0xFFFFFFFD
 212
 213 #define ADSP2_LOCK_REGION_SHIFT              16
 214
 215 #define ADSP_MAX_STD_CTRL_SIZE               512
 216
 217 #define WM_ADSP_ACKED_CTL_TIMEOUT_MS         100
 218 #define WM_ADSP_ACKED_CTL_N_QUICKPOLLS       10
 219 #define WM_ADSP_ACKED_CTL_MIN_VALUE          0
 220 #define WM_ADSP_ACKED_CTL_MAX_VALUE          0xFFFFFF
 221
 222 /*
 223  * Event control messages
 224  */
 225 #define WM_ADSP_FW_EVENT_SHUTDOWN            0x000001
 226
 227 /*
 228  * HALO system info
 229  */
 230 #define HALO_AHBM_WINDOW_DEBUG_0             0x02040
 231 #define HALO_AHBM_WINDOW_DEBUG_1             0x02044
 232
 233 /*
 234  * HALO core
 235  */
 236 #define HALO_SCRATCH1                        0x005c0
 237 #define HALO_SCRATCH2                        0x005c8
 238 #define HALO_SCRATCH3                        0x005d0
 239 #define HALO_SCRATCH4                        0x005d8
 240 #define HALO_CCM_CORE_CONTROL                0x41000
 241 #define HALO_CORE_SOFT_RESET                 0x00010
 242 #define HALO_WDT_CONTROL                     0x47000
 243
 244 /*
 245  * HALO MPU banks
 246  */
 247 #define HALO_MPU_XMEM_ACCESS_0               0x43000
 248 #define HALO_MPU_YMEM_ACCESS_0               0x43004
 249 #define HALO_MPU_WINDOW_ACCESS_0             0x43008
 250 #define HALO_MPU_XREG_ACCESS_0               0x4300C
 251 #define HALO_MPU_YREG_ACCESS_0               0x43014
 252 #define HALO_MPU_XMEM_ACCESS_1               0x43018
 253 #define HALO_MPU_YMEM_ACCESS_1               0x4301C
 254 #define HALO_MPU_WINDOW_ACCESS_1             0x43020
 255 #define HALO_MPU_XREG_ACCESS_1               0x43024
 256 #define HALO_MPU_YREG_ACCESS_1               0x4302C
 257 #define HALO_MPU_XMEM_ACCESS_2               0x43030
 258 #define HALO_MPU_YMEM_ACCESS_2               0x43034
 259 #define HALO_MPU_WINDOW_ACCESS_2             0x43038
 260 #define HALO_MPU_XREG_ACCESS_2               0x4303C
 261 #define HALO_MPU_YREG_ACCESS_2               0x43044
 262 #define HALO_MPU_XMEM_ACCESS_3               0x43048
 263 #define HALO_MPU_YMEM_ACCESS_3               0x4304C
 264 #define HALO_MPU_WINDOW_ACCESS_3             0x43050
 265 #define HALO_MPU_XREG_ACCESS_3               0x43054
 266 #define HALO_MPU_YREG_ACCESS_3               0x4305C
 267 #define HALO_MPU_XM_VIO_ADDR                 0x43100
 268 #define HALO_MPU_XM_VIO_STATUS               0x43104
 269 #define HALO_MPU_YM_VIO_ADDR                 0x43108
 270 #define HALO_MPU_YM_VIO_STATUS               0x4310C
 271 #define HALO_MPU_PM_VIO_ADDR                 0x43110
 272 #define HALO_MPU_PM_VIO_STATUS               0x43114
 273 #define HALO_MPU_LOCK_CONFIG                 0x43140
 274
 275 /*
 276  * HALO_AHBM_WINDOW_DEBUG_1
 277  */
 278 #define HALO_AHBM_CORE_ERR_ADDR_MASK         0x0fffff00
 279 #define HALO_AHBM_CORE_ERR_ADDR_SHIFT                 8
 280 #define HALO_AHBM_FLAGS_ERR_MASK             0x000000ff
 281
 282 /*
 283  * HALO_CCM_CORE_CONTROL
 284  */
 285 #define HALO_CORE_EN                        0x00000001
 286
 287 /*
 288  * HALO_CORE_SOFT_RESET
 289  */
 290 #define HALO_CORE_SOFT_RESET_MASK           0x00000001
 291
 292 /*
 293  * HALO_WDT_CONTROL
 294  */
 295 #define HALO_WDT_EN_MASK                    0x00000001
 296
 297 /*
 298  * HALO_MPU_?M_VIO_STATUS
 299  */
 300 #define HALO_MPU_VIO_STS_MASK               0x007e0000
 301 #define HALO_MPU_VIO_STS_SHIFT                      17
 302 #define HALO_MPU_VIO_ERR_WR_MASK            0x00008000
 303 #define HALO_MPU_VIO_ERR_SRC_MASK           0x00007fff
 304 #define HALO_MPU_VIO_ERR_SRC_SHIFT                   0
 305
 306 static struct wm_adsp_ops wm_adsp1_ops;
 307 static struct wm_adsp_ops wm_adsp2_ops[];
 308 static struct wm_adsp_ops wm_halo_ops;
 309
 310 struct wm_adsp_buf {
 311         struct list_head list;
 312         void *buf;
 313 };
 314
 315 static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
 316                                              struct list_head *list)
 317 {
 318         struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
 319
 320         if (buf == NULL)
 321                 return NULL;
 322
 323         buf->buf = vmalloc(len);
 324         if (!buf->buf) {
 325                 kfree(buf);
 326                 return NULL;
 327         }
 328         memcpy(buf->buf, src, len);
 329
 330         if (list)
 331                 list_add_tail(&buf->list, list);
 332
 333         return buf;
 334 }
 335
 336 static void wm_adsp_buf_free(struct list_head *list)
 337 {
 338         while (!list_empty(list)) {
 339                 struct wm_adsp_buf *buf = list_first_entry(list,
 340                                                            struct wm_adsp_buf,
 341                                                            list);
 342                 list_del(&buf->list);
 343                 vfree(buf->buf);
 344                 kfree(buf);
 345         }
 346 }
 347
 348 #define WM_ADSP_FW_MBC_VSS  0
 349 #define WM_ADSP_FW_HIFI     1
 350 #define WM_ADSP_FW_TX       2
 351 #define WM_ADSP_FW_TX_SPK   3
 352 #define WM_ADSP_FW_RX       4
 353 #define WM_ADSP_FW_RX_ANC   5
 354 #define WM_ADSP_FW_CTRL     6
 355 #define WM_ADSP_FW_ASR      7
 356 #define WM_ADSP_FW_TRACE    8
 357 #define WM_ADSP_FW_SPK_PROT 9
 358 #define WM_ADSP_FW_SPK_CALI 10
 359 #define WM_ADSP_FW_SPK_DIAG 11
 360 #define WM_ADSP_FW_MISC     12
 361
 362 #define WM_ADSP_NUM_FW      13
 363
 364 static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
 365         [WM_ADSP_FW_MBC_VSS] =  "MBC/VSS",
 366         [WM_ADSP_FW_HIFI] =     "MasterHiFi",
 367         [WM_ADSP_FW_TX] =       "Tx",
 368         [WM_ADSP_FW_TX_SPK] =   "Tx Speaker",
 369         [WM_ADSP_FW_RX] =       "Rx",
 370         [WM_ADSP_FW_RX_ANC] =   "Rx ANC",
 371         [WM_ADSP_FW_CTRL] =     "Voice Ctrl",
 372         [WM_ADSP_FW_ASR] =      "ASR Assist",
 373         [WM_ADSP_FW_TRACE] =    "Dbg Trace",
 374         [WM_ADSP_FW_SPK_PROT] = "Protection",
 375         [WM_ADSP_FW_SPK_CALI] = "Calibration",
 376         [WM_ADSP_FW_SPK_DIAG] = "Diagnostic",
 377         [WM_ADSP_FW_MISC] =     "Misc",
 378 };
 379
 380 struct wm_adsp_system_config_xm_hdr {
 381         __be32 sys_enable;
 382         __be32 fw_id;
 383         __be32 fw_rev;
 384         __be32 boot_status;
 385         __be32 watchdog;
 386         __be32 dma_buffer_size;
 387         __be32 rdma[6];
 388         __be32 wdma[8];
 389         __be32 build_job_name[3];
 390         __be32 build_job_number;
 391 };
 392
 393 struct wm_halo_system_config_xm_hdr {
 394         __be32 halo_heartbeat;
 395         __be32 build_job_name[3];
 396         __be32 build_job_number;
 397 };
 398
 399 struct wm_adsp_alg_xm_struct {
 400         __be32 magic;
 401         __be32 smoothing;
 402         __be32 threshold;
 403         __be32 host_buf_ptr;
 404         __be32 start_seq;
 405         __be32 high_water_mark;
 406         __be32 low_water_mark;
 407         __be64 smoothed_power;
 408 };
 409
 410 struct wm_adsp_host_buf_coeff_v1 {
 411         __be32 host_buf_ptr;            /* Host buffer pointer */
 412         __be32 versions;                /* Version numbers */
 413         __be32 name[4];                 /* The buffer name */
 414 };
 415
 416 struct wm_adsp_buffer {
 417         __be32 buf1_base;               /* Base addr of first buffer area */
 418         __be32 buf1_size;               /* Size of buf1 area in DSP words */
 419         __be32 buf2_base;               /* Base addr of 2nd buffer area */
 420         __be32 buf1_buf2_size;          /* Size of buf1+buf2 in DSP words */
 421         __be32 buf3_base;               /* Base addr of buf3 area */
 422         __be32 buf_total_size;          /* Size of buf1+buf2+buf3 in DSP words */
 423         __be32 high_water_mark;         /* Point at which IRQ is asserted */
 424         __be32 irq_count;               /* bits 1-31 count IRQ assertions */
 425         __be32 irq_ack;                 /* acked IRQ count, bit 0 enables IRQ */
 426         __be32 next_write_index;        /* word index of next write */
 427         __be32 next_read_index;         /* word index of next read */
 428         __be32 error;                   /* error if any */
 429         __be32 oldest_block_index;      /* word index of oldest surviving */
 430         __be32 requested_rewind;        /* how many blocks rewind was done */
 431         __be32 reserved_space;          /* internal */
 432         __be32 min_free;                /* min free space since stream start */
 433         __be32 blocks_written[2];       /* total blocks written (64 bit) */
 434         __be32 words_written[2];        /* total words written (64 bit) */
 435 };
 436
 437 struct wm_adsp_compr;
 438
 439 struct wm_adsp_compr_buf {
 440         struct list_head list;
 441         struct wm_adsp *dsp;
 442         struct wm_adsp_compr *compr;
 443
 444         struct wm_adsp_buffer_region *regions;
 445         u32 host_buf_ptr;
 446
 447         u32 error;
 448         u32 irq_count;
 449         int read_index;
 450         int avail;
 451         int host_buf_mem_type;
 452
 453         char *name;
 454 };
 455
 456 struct wm_adsp_compr {
 457         struct list_head list;
 458         struct wm_adsp *dsp;
 459         struct wm_adsp_compr_buf *buf;
 460
 461         struct snd_compr_stream *stream;
 462         struct snd_compressed_buffer size;
 463
 464         u32 *raw_buf;
 465         unsigned int copied_total;
 466
 467         unsigned int sample_rate;
 468
 469         const char *name;
 470 };
 471
 472 #define WM_ADSP_DATA_WORD_SIZE         3
 473
 474 #define WM_ADSP_MIN_FRAGMENTS          1
 475 #define WM_ADSP_MAX_FRAGMENTS          256
 476 #define WM_ADSP_MIN_FRAGMENT_SIZE      (64 * WM_ADSP_DATA_WORD_SIZE)
 477 #define WM_ADSP_MAX_FRAGMENT_SIZE      (4096 * WM_ADSP_DATA_WORD_SIZE)
 478
 479 #define WM_ADSP_ALG_XM_STRUCT_MAGIC    0x49aec7
 480
 481 #define HOST_BUFFER_FIELD(field) \
 482         (offsetof(struct wm_adsp_buffer, field) / sizeof(__be32))
 483
 484 #define ALG_XM_FIELD(field) \
 485         (offsetof(struct wm_adsp_alg_xm_struct, field) / sizeof(__be32))
 486
 487 #define HOST_BUF_COEFF_SUPPORTED_COMPAT_VER     1
 488
 489 #define HOST_BUF_COEFF_COMPAT_VER_MASK          0xFF00
 490 #define HOST_BUF_COEFF_COMPAT_VER_SHIFT         8
 491
 492 static int wm_adsp_buffer_init(struct wm_adsp *dsp);
 493 static int wm_adsp_buffer_free(struct wm_adsp *dsp);
 494
 495 struct wm_adsp_buffer_region {
 496         unsigned int offset;
 497         unsigned int cumulative_size;
 498         unsigned int mem_type;
 499         unsigned int base_addr;
 500 };
 501
 502 struct wm_adsp_buffer_region_def {
 503         unsigned int mem_type;
 504         unsigned int base_offset;
 505         unsigned int size_offset;
 506 };
 507
 508 static const struct wm_adsp_buffer_region_def default_regions[] = {
 509         {
 510                 .mem_type = WMFW_ADSP2_XM,
 511                 .base_offset = HOST_BUFFER_FIELD(buf1_base),
 512                 .size_offset = HOST_BUFFER_FIELD(buf1_size),
 513         },
 514         {
 515                 .mem_type = WMFW_ADSP2_XM,
 516                 .base_offset = HOST_BUFFER_FIELD(buf2_base),
 517                 .size_offset = HOST_BUFFER_FIELD(buf1_buf2_size),
 518         },
 519         {
 520                 .mem_type = WMFW_ADSP2_YM,
 521                 .base_offset = HOST_BUFFER_FIELD(buf3_base),
 522                 .size_offset = HOST_BUFFER_FIELD(buf_total_size),
 523         },
 524 };
 525
 526 struct wm_adsp_fw_caps {
 527         u32 id;
 528         struct snd_codec_desc desc;
 529         int num_regions;
 530         const struct wm_adsp_buffer_region_def *region_defs;
 531 };
 532
 533 static const struct wm_adsp_fw_caps ctrl_caps[] = {
 534         {
 535                 .id = SND_AUDIOCODEC_BESPOKE,
 536                 .desc = {
 537                         .max_ch = 8,
 538                         .sample_rates = { 16000 },
 539                         .num_sample_rates = 1,
 540                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
 541                 },
 542                 .num_regions = ARRAY_SIZE(default_regions),
 543                 .region_defs = default_regions,
 544         },
 545 };
 546
 547 static const struct wm_adsp_fw_caps trace_caps[] = {
 548         {
 549                 .id = SND_AUDIOCODEC_BESPOKE,
 550                 .desc = {
 551                         .max_ch = 8,
 552                         .sample_rates = {
 553                                 4000, 8000, 11025, 12000, 16000, 22050,
 554                                 24000, 32000, 44100, 48000, 64000, 88200,
 555                                 96000, 176400, 192000
 556                         },
 557                         .num_sample_rates = 15,
 558                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
 559                 },
 560                 .num_regions = ARRAY_SIZE(default_regions),
 561                 .region_defs = default_regions,
 562         },
 563 };
 564
 565 static const struct {
 566         const char *file;
 567         int compr_direction;
 568         int num_caps;
 569         const struct wm_adsp_fw_caps *caps;
 570         bool voice_trigger;
 571 } wm_adsp_fw[WM_ADSP_NUM_FW] = {
 572         [WM_ADSP_FW_MBC_VSS] =  { .file = "mbc-vss" },
 573         [WM_ADSP_FW_HIFI] =     { .file = "hifi" },
 574         [WM_ADSP_FW_TX] =       { .file = "tx" },
 575         [WM_ADSP_FW_TX_SPK] =   { .file = "tx-spk" },
 576         [WM_ADSP_FW_RX] =       { .file = "rx" },
 577         [WM_ADSP_FW_RX_ANC] =   { .file = "rx-anc" },
 578         [WM_ADSP_FW_CTRL] =     {
 579                 .file = "ctrl",
 580                 .compr_direction = SND_COMPRESS_CAPTURE,
 581                 .num_caps = ARRAY_SIZE(ctrl_caps),
 582                 .caps = ctrl_caps,
 583                 .voice_trigger = true,
 584         },
 585         [WM_ADSP_FW_ASR] =      { .file = "asr" },
 586         [WM_ADSP_FW_TRACE] =    {
 587                 .file = "trace",
 588                 .compr_direction = SND_COMPRESS_CAPTURE,
 589                 .num_caps = ARRAY_SIZE(trace_caps),
 590                 .caps = trace_caps,
 591         },
 592         [WM_ADSP_FW_SPK_PROT] = { .file = "spk-prot" },
 593         [WM_ADSP_FW_SPK_CALI] = { .file = "spk-cali" },
 594         [WM_ADSP_FW_SPK_DIAG] = { .file = "spk-diag" },
 595         [WM_ADSP_FW_MISC] =     { .file = "misc" },
 596 };
 597
 598 struct wm_coeff_ctl_ops {
 599         int (*xget)(struct snd_kcontrol *kcontrol,
 600                     struct snd_ctl_elem_value *ucontrol);
 601         int (*xput)(struct snd_kcontrol *kcontrol,
 602                     struct snd_ctl_elem_value *ucontrol);
 603 };
 604
 605 struct wm_coeff_ctl {
 606         const char *name;
 607         const char *fw_name;
 608         /* Subname is needed to match with firmware */
 609         const char *subname;
 610         unsigned int subname_len;
 611         struct wm_adsp_alg_region alg_region;
 612         struct wm_coeff_ctl_ops ops;
 613         struct wm_adsp *dsp;
 614         unsigned int enabled:1;
 615         struct list_head list;
 616         void *cache;
 617         unsigned int offset;
 618         size_t len;
 619         unsigned int set:1;
 620         struct soc_bytes_ext bytes_ext;
 621         unsigned int flags;
 622         unsigned int type;
 623 };
 624
 625 static const char *wm_adsp_mem_region_name(unsigned int type)
 626 {
 627         switch (type) {
 628         case WMFW_ADSP1_PM:
 629                 return "PM";
 630         case WMFW_HALO_PM_PACKED:
 631                 return "PM_PACKED";
 632         case WMFW_ADSP1_DM:
 633                 return "DM";
 634         case WMFW_ADSP2_XM:
 635                 return "XM";
 636         case WMFW_HALO_XM_PACKED:
 637                 return "XM_PACKED";
 638         case WMFW_ADSP2_YM:
 639                 return "YM";
 640         case WMFW_HALO_YM_PACKED:
 641                 return "YM_PACKED";
 642         case WMFW_ADSP1_ZM:
 643                 return "ZM";
 644         default:
 645                 return NULL;
 646         }
 647 }
 648
 649 #ifdef CONFIG_DEBUG_FS
 650 static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s)
 651 {
 652         char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
 653
 654         kfree(dsp->wmfw_file_name);
 655         dsp->wmfw_file_name = tmp;
 656 }
 657
 658 static void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, const char *s)
 659 {
 660         char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
 661
 662         kfree(dsp->bin_file_name);
 663         dsp->bin_file_name = tmp;
 664 }
 665
 666 static void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
 667 {
 668         kfree(dsp->wmfw_file_name);
 669         kfree(dsp->bin_file_name);
 670         dsp->wmfw_file_name = NULL;
 671         dsp->bin_file_name = NULL;
 672 }
 673
 674 static ssize_t wm_adsp_debugfs_wmfw_read(struct file *file,
 675                                          char __user *user_buf,
 676                                          size_t count, loff_t *ppos)
 677 {
 678         struct wm_adsp *dsp = file->private_data;
 679         ssize_t ret;
 680
 681         mutex_lock(&dsp->pwr_lock);
 682
 683         if (!dsp->wmfw_file_name || !dsp->booted)
 684                 ret = 0;
 685         else
 686                 ret = simple_read_from_buffer(user_buf, count, ppos,
 687                                               dsp->wmfw_file_name,
 688                                               strlen(dsp->wmfw_file_name));
 689
 690         mutex_unlock(&dsp->pwr_lock);
 691         return ret;
 692 }
 693
 694 static ssize_t wm_adsp_debugfs_bin_read(struct file *file,
 695                                         char __user *user_buf,
 696                                         size_t count, loff_t *ppos)
 697 {
 698         struct wm_adsp *dsp = file->private_data;
 699         ssize_t ret;
 700
 701         mutex_lock(&dsp->pwr_lock);
 702
 703         if (!dsp->bin_file_name || !dsp->booted)
 704                 ret = 0;
 705         else
 706                 ret = simple_read_from_buffer(user_buf, count, ppos,
 707                                               dsp->bin_file_name,
 708                                               strlen(dsp->bin_file_name));
 709
 710         mutex_unlock(&dsp->pwr_lock);
 711         return ret;
 712 }
 713
 714 static const struct {
 715         const char *name;
 716         const struct file_operations fops;
 717 } wm_adsp_debugfs_fops[] = {
 718         {
 719                 .name = "wmfw_file_name",
 720                 .fops = {
 721                         .open = simple_open,
 722                         .read = wm_adsp_debugfs_wmfw_read,
 723                 },
 724         },
 725         {
 726                 .name = "bin_file_name",
 727                 .fops = {
 728                         .open = simple_open,
 729                         .read = wm_adsp_debugfs_bin_read,
 730                 },
 731         },
 732 };
 733
 734 static void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
 735                                   struct snd_soc_component *component)
 736 {
 737         struct dentry *root = NULL;
 738         int i;
 739
 740         root = debugfs_create_dir(dsp->name, component->debugfs_root);
 741
 742         debugfs_create_bool("booted", 0444, root, &dsp->booted);
 743         debugfs_create_bool("running", 0444, root, &dsp->running);
 744         debugfs_create_x32("fw_id", 0444, root, &dsp->fw_id);
 745         debugfs_create_x32("fw_version", 0444, root, &dsp->fw_id_version);
 746
 747         for (i = 0; i < ARRAY_SIZE(wm_adsp_debugfs_fops); ++i)
 748                 debugfs_create_file(wm_adsp_debugfs_fops[i].name, 0444, root,
 749                                     dsp, &wm_adsp_debugfs_fops[i].fops);
 750
 751         dsp->debugfs_root = root;
 752 }
 753
 754 static void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
 755 {
 756         wm_adsp_debugfs_clear(dsp);
 757         debugfs_remove_recursive(dsp->debugfs_root);
 758 }
 759 #else
 760 static inline void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
 761                                          struct snd_soc_component *component)
 762 {
 763 }
 764
 765 static inline void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
 766 {
 767 }
 768
 769 static inline void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp,
 770                                                  const char *s)
 771 {
 772 }
 773
 774 static inline void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp,
 775                                                 const char *s)
 776 {
 777 }
 778
 779 static inline void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
 780 {
 781 }
 782 #endif
 783
 784 int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
 785                    struct snd_ctl_elem_value *ucontrol)
 786 {
 787         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 788         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
 789         struct wm_adsp *dsp = snd_soc_component_get_drvdata(component);
 790
 791         ucontrol->value.enumerated.item[0] = dsp[e->shift_l].fw;
 792
 793         return 0;
 794 }
 795 EXPORT_SYMBOL_GPL(wm_adsp_fw_get);
 796
 797 int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
 798                    struct snd_ctl_elem_value *ucontrol)
 799 {
 800         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 801         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
 802         struct wm_adsp *dsp = snd_soc_component_get_drvdata(component);
 803         int ret = 0;
 804
 805         if (ucontrol->value.enumerated.item[0] == dsp[e->shift_l].fw)
 806                 return 0;
 807
 808         if (ucontrol->value.enumerated.item[0] >= WM_ADSP_NUM_FW)
 809                 return -EINVAL;
 810
 811         mutex_lock(&dsp[e->shift_l].pwr_lock);
 812
 813         if (dsp[e->shift_l].booted || !list_empty(&dsp[e->shift_l].compr_list))
 814                 ret = -EBUSY;
 815         else
 816                 dsp[e->shift_l].fw = ucontrol->value.enumerated.item[0];
 817
 818         mutex_unlock(&dsp[e->shift_l].pwr_lock);
 819
 820         return ret;
 821 }
 822 EXPORT_SYMBOL_GPL(wm_adsp_fw_put);
 823
 824 const struct soc_enum wm_adsp_fw_enum[] = {
 825         SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
 826         SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
 827         SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
 828         SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
 829         SOC_ENUM_SINGLE(0, 4, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
 830         SOC_ENUM_SINGLE(0, 5, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
 831         SOC_ENUM_SINGLE(0, 6, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
 832 };
 833 EXPORT_SYMBOL_GPL(wm_adsp_fw_enum);
 834
 835 static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
 836                                                         int type)
 837 {
 838         int i;
 839
 840         for (i = 0; i < dsp->num_mems; i++)
 841                 if (dsp->mem[i].type == type)
 842                         return &dsp->mem[i];
 843
 844         return NULL;
 845 }
 846
 847 static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem,
 848                                           unsigned int offset)
 849 {
 850         switch (mem->type) {
 851         case WMFW_ADSP1_PM:
 852                 return mem->base + (offset * 3);
 853         case WMFW_ADSP1_DM:
 854         case WMFW_ADSP2_XM:
 855         case WMFW_ADSP2_YM:
 856         case WMFW_ADSP1_ZM:
 857                 return mem->base + (offset * 2);
 858         default:
 859                 WARN(1, "Unknown memory region type");
 860                 return offset;
 861         }
 862 }
 863
 864 static unsigned int wm_halo_region_to_reg(struct wm_adsp_region const *mem,
 865                                           unsigned int offset)
 866 {
 867         switch (mem->type) {
 868         case WMFW_ADSP2_XM:
 869         case WMFW_ADSP2_YM:
 870                 return mem->base + (offset * 4);
 871         case WMFW_HALO_XM_PACKED:
 872         case WMFW_HALO_YM_PACKED:
 873                 return (mem->base + (offset * 3)) & ~0x3;
 874         case WMFW_HALO_PM_PACKED:
 875                 return mem->base + (offset * 5);
 876         default:
 877                 WARN(1, "Unknown memory region type");
 878                 return offset;
 879         }
 880 }
 881
 882 static void wm_adsp_read_fw_status(struct wm_adsp *dsp,
 883                                    int noffs, unsigned int *offs)
 884 {
 885         unsigned int i;
 886         int ret;
 887
 888         for (i = 0; i < noffs; ++i) {
 889                 ret = regmap_read(dsp->regmap, dsp->base + offs[i], &offs[i]);
 890                 if (ret) {
 891                         adsp_err(dsp, "Failed to read SCRATCH%u: %d\n", i, ret);
 892                         return;
 893                 }
 894         }
 895 }
 896
 897 static void wm_adsp2_show_fw_status(struct wm_adsp *dsp)
 898 {
 899         unsigned int offs[] = {
 900                 ADSP2_SCRATCH0, ADSP2_SCRATCH1, ADSP2_SCRATCH2, ADSP2_SCRATCH3,
 901         };
 902
 903         wm_adsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs);
 904
 905         adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
 906                  offs[0], offs[1], offs[2], offs[3]);
 907 }
 908
 909 static void wm_adsp2v2_show_fw_status(struct wm_adsp *dsp)
 910 {
 911         unsigned int offs[] = { ADSP2V2_SCRATCH0_1, ADSP2V2_SCRATCH2_3 };
 912
 913         wm_adsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs);
 914
 915         adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
 916                  offs[0] & 0xFFFF, offs[0] >> 16,
 917                  offs[1] & 0xFFFF, offs[1] >> 16);
 918 }
 919
 920 static void wm_halo_show_fw_status(struct wm_adsp *dsp)
 921 {
 922         unsigned int offs[] = {
 923                 HALO_SCRATCH1, HALO_SCRATCH2, HALO_SCRATCH3, HALO_SCRATCH4,
 924         };
 925
 926         wm_adsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs);
 927
 928         adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
 929                  offs[0], offs[1], offs[2], offs[3]);
 930 }
 931
 932 static inline struct wm_coeff_ctl *bytes_ext_to_ctl(struct soc_bytes_ext *ext)
 933 {
 934         return container_of(ext, struct wm_coeff_ctl, bytes_ext);
 935 }
 936
 937 static int wm_coeff_base_reg(struct wm_coeff_ctl *ctl, unsigned int *reg)
 938 {
 939         const struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
 940         struct wm_adsp *dsp = ctl->dsp;
 941         const struct wm_adsp_region *mem;
 942
 943         mem = wm_adsp_find_region(dsp, alg_region->type);
 944         if (!mem) {
 945                 adsp_err(dsp, "No base for region %x\n",
 946                          alg_region->type);
 947                 return -EINVAL;
 948         }
 949
 950         *reg = dsp->ops->region_to_reg(mem, ctl->alg_region.base + ctl->offset);
 951
 952         return 0;
 953 }
 954
 955 static int wm_coeff_info(struct snd_kcontrol *kctl,
 956                          struct snd_ctl_elem_info *uinfo)
 957 {
 958         struct soc_bytes_ext *bytes_ext =
 959                 (struct soc_bytes_ext *)kctl->private_value;
 960         struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
 961
 962         switch (ctl->type) {
 963         case WMFW_CTL_TYPE_ACKED:
 964                 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 965                 uinfo->value.integer.min = WM_ADSP_ACKED_CTL_MIN_VALUE;
 966                 uinfo->value.integer.max = WM_ADSP_ACKED_CTL_MAX_VALUE;
 967                 uinfo->value.integer.step = 1;
 968                 uinfo->count = 1;
 969                 break;
 970         default:
 971                 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
 972                 uinfo->count = ctl->len;
 973                 break;
 974         }
 975
 976         return 0;
 977 }
 978
 979 static int wm_coeff_write_acked_control(struct wm_coeff_ctl *ctl,
 980                                         unsigned int event_id)
 981 {
 982         struct wm_adsp *dsp = ctl->dsp;
 983         u32 val = cpu_to_be32(event_id);
 984         unsigned int reg;
 985         int i, ret;
 986
 987         ret = wm_coeff_base_reg(ctl, &reg);
 988         if (ret)
 989                 return ret;
 990
 991         adsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n",
 992                  event_id, ctl->alg_region.alg,
 993                  wm_adsp_mem_region_name(ctl->alg_region.type), ctl->offset);
 994
 995         ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val));
 996         if (ret) {
 997                 adsp_err(dsp, "Failed to write %x: %d\n", reg, ret);
 998                 return ret;
 999         }
1000
1001         /*
1002          * Poll for ack, we initially poll at ~1ms intervals for firmwares
1003          * that respond quickly, then go to ~10ms polls. A firmware is unlikely
1004          * to ack instantly so we do the first 1ms delay before reading the
1005          * control to avoid a pointless bus transaction
1006          */
1007         for (i = 0; i < WM_ADSP_ACKED_CTL_TIMEOUT_MS;) {
1008                 switch (i) {
1009                 case 0 ... WM_ADSP_ACKED_CTL_N_QUICKPOLLS - 1:
1010                         usleep_range(1000, 2000);
1011                         i++;
1012                         break;
1013                 default:
1014                         usleep_range(10000, 20000);
1015                         i += 10;
1016                         break;
1017                 }
1018
1019                 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
1020                 if (ret) {
1021                         adsp_err(dsp, "Failed to read %x: %d\n", reg, ret);
1022                         return ret;
1023                 }
1024
1025                 if (val == 0) {
1026                         adsp_dbg(dsp, "Acked control ACKED at poll %u\n", i);
1027                         return 0;
1028                 }
1029         }
1030
1031         adsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n",
1032                   reg, ctl->alg_region.alg,
1033                   wm_adsp_mem_region_name(ctl->alg_region.type),
1034                   ctl->offset);
1035
1036         return -ETIMEDOUT;
1037 }
1038
1039 static int wm_coeff_write_ctrl_raw(struct wm_coeff_ctl *ctl,
1040                                    const void *buf, size_t len)
1041 {
1042         struct wm_adsp *dsp = ctl->dsp;
1043         void *scratch;
1044         int ret;
1045         unsigned int reg;
1046
1047         ret = wm_coeff_base_reg(ctl, &reg);
1048         if (ret)
1049                 return ret;
1050
1051         scratch = kmemdup(buf, len, GFP_KERNEL | GFP_DMA);
1052         if (!scratch)
1053                 return -ENOMEM;
1054
1055         ret = regmap_raw_write(dsp->regmap, reg, scratch,
1056                                len);
1057         if (ret) {
1058                 adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n",
1059                          len, reg, ret);
1060                 kfree(scratch);
1061                 return ret;
1062         }
1063         adsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg);
1064
1065         kfree(scratch);
1066
1067         return 0;
1068 }
1069
1070 static int wm_coeff_write_ctrl(struct wm_coeff_ctl *ctl,
1071                                const void *buf, size_t len)
1072 {
1073         int ret = 0;
1074
1075         if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
1076                 ret = -EPERM;
1077         else if (buf != ctl->cache)
1078                 memcpy(ctl->cache, buf, len);
1079
1080         ctl->set = 1;
1081         if (ctl->enabled && ctl->dsp->running)
1082                 ret = wm_coeff_write_ctrl_raw(ctl, buf, len);
1083
1084         return ret;
1085 }
1086
1087 static int wm_coeff_put(struct snd_kcontrol *kctl,
1088                         struct snd_ctl_elem_value *ucontrol)
1089 {
1090         struct soc_bytes_ext *bytes_ext =
1091                 (struct soc_bytes_ext *)kctl->private_value;
1092         struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1093         char *p = ucontrol->value.bytes.data;
1094         int ret = 0;
1095
1096         mutex_lock(&ctl->dsp->pwr_lock);
1097         ret = wm_coeff_write_ctrl(ctl, p, ctl->len);
1098         mutex_unlock(&ctl->dsp->pwr_lock);
1099
1100         return ret;
1101 }
1102
1103 static int wm_coeff_tlv_put(struct snd_kcontrol *kctl,
1104                             const unsigned int __user *bytes, unsigned int size)
1105 {
1106         struct soc_bytes_ext *bytes_ext =
1107                 (struct soc_bytes_ext *)kctl->private_value;
1108         struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1109         int ret = 0;
1110
1111         mutex_lock(&ctl->dsp->pwr_lock);
1112
1113         if (copy_from_user(ctl->cache, bytes, size))
1114                 ret = -EFAULT;
1115         else
1116                 ret = wm_coeff_write_ctrl(ctl, ctl->cache, size);
1117
1118         mutex_unlock(&ctl->dsp->pwr_lock);
1119
1120         return ret;
1121 }
1122
1123 static int wm_coeff_put_acked(struct snd_kcontrol *kctl,
1124                               struct snd_ctl_elem_value *ucontrol)
1125 {
1126         struct soc_bytes_ext *bytes_ext =
1127                 (struct soc_bytes_ext *)kctl->private_value;
1128         struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1129         unsigned int val = ucontrol->value.integer.value[0];
1130         int ret;
1131
1132         if (val == 0)
1133                 return 0;       /* 0 means no event */
1134
1135         mutex_lock(&ctl->dsp->pwr_lock);
1136
1137         if (ctl->enabled && ctl->dsp->running)
1138                 ret = wm_coeff_write_acked_control(ctl, val);
1139         else
1140                 ret = -EPERM;
1141
1142         mutex_unlock(&ctl->dsp->pwr_lock);
1143
1144         return ret;
1145 }
1146
1147 static int wm_coeff_read_ctrl_raw(struct wm_coeff_ctl *ctl,
1148                                   void *buf, size_t len)
1149 {
1150         struct wm_adsp *dsp = ctl->dsp;
1151         void *scratch;
1152         int ret;
1153         unsigned int reg;
1154
1155         ret = wm_coeff_base_reg(ctl, &reg);
1156         if (ret)
1157                 return ret;
1158
1159         scratch = kmalloc(len, GFP_KERNEL | GFP_DMA);
1160         if (!scratch)
1161                 return -ENOMEM;
1162
1163         ret = regmap_raw_read(dsp->regmap, reg, scratch, len);
1164         if (ret) {
1165                 adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n",
1166                          len, reg, ret);
1167                 kfree(scratch);
1168                 return ret;
1169         }
1170         adsp_dbg(dsp, "Read %zu bytes from %x\n", len, reg);
1171
1172         memcpy(buf, scratch, len);
1173         kfree(scratch);
1174
1175         return 0;
1176 }
1177
1178 static int wm_coeff_read_ctrl(struct wm_coeff_ctl *ctl, void *buf, size_t len)
1179 {
1180         int ret = 0;
1181
1182         if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
1183                 if (ctl->enabled && ctl->dsp->running)
1184                         return wm_coeff_read_ctrl_raw(ctl, buf, len);
1185                 else
1186                         return -EPERM;
1187         } else {
1188                 if (!ctl->flags && ctl->enabled && ctl->dsp->running)
1189                         ret = wm_coeff_read_ctrl_raw(ctl, ctl->cache, ctl->len);
1190
1191                 if (buf != ctl->cache)
1192                         memcpy(buf, ctl->cache, len);
1193         }
1194
1195         return ret;
1196 }
1197
1198 static int wm_coeff_get(struct snd_kcontrol *kctl,
1199                         struct snd_ctl_elem_value *ucontrol)
1200 {
1201         struct soc_bytes_ext *bytes_ext =
1202                 (struct soc_bytes_ext *)kctl->private_value;
1203         struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1204         char *p = ucontrol->value.bytes.data;
1205         int ret;
1206
1207         mutex_lock(&ctl->dsp->pwr_lock);
1208         ret = wm_coeff_read_ctrl(ctl, p, ctl->len);
1209         mutex_unlock(&ctl->dsp->pwr_lock);
1210
1211         return ret;
1212 }
1213
1214 static int wm_coeff_tlv_get(struct snd_kcontrol *kctl,
1215                             unsigned int __user *bytes, unsigned int size)
1216 {
1217         struct soc_bytes_ext *bytes_ext =
1218                 (struct soc_bytes_ext *)kctl->private_value;
1219         struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1220         int ret = 0;
1221
1222         mutex_lock(&ctl->dsp->pwr_lock);
1223
1224         ret = wm_coeff_read_ctrl_raw(ctl, ctl->cache, size);
1225
1226         if (!ret && copy_to_user(bytes, ctl->cache, size))
1227                 ret = -EFAULT;
1228
1229         mutex_unlock(&ctl->dsp->pwr_lock);
1230
1231         return ret;
1232 }
1233
1234 static int wm_coeff_get_acked(struct snd_kcontrol *kcontrol,
1235                               struct snd_ctl_elem_value *ucontrol)
1236 {
1237         /*
1238          * Although it's not useful to read an acked control, we must satisfy
1239          * user-side assumptions that all controls are readable and that a
1240          * write of the same value should be filtered out (it's valid to send
1241          * the same event number again to the firmware). We therefore return 0,
1242          * meaning "no event" so valid event numbers will always be a change
1243          */
1244         ucontrol->value.integer.value[0] = 0;
1245
1246         return 0;
1247 }
1248
1249 struct wmfw_ctl_work {
1250         struct wm_adsp *dsp;
1251         struct wm_coeff_ctl *ctl;
1252         struct work_struct work;
1253 };
1254
1255 static unsigned int wmfw_convert_flags(unsigned int in, unsigned int len)
1256 {
1257         unsigned int out, rd, wr, vol;
1258
1259         if (len > ADSP_MAX_STD_CTRL_SIZE) {
1260                 rd = SNDRV_CTL_ELEM_ACCESS_TLV_READ;
1261                 wr = SNDRV_CTL_ELEM_ACCESS_TLV_WRITE;
1262                 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1263
1264                 out = SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK;
1265         } else {
1266                 rd = SNDRV_CTL_ELEM_ACCESS_READ;
1267                 wr = SNDRV_CTL_ELEM_ACCESS_WRITE;
1268                 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1269
1270                 out = 0;
1271         }
1272
1273         if (in) {
1274                 out |= rd;
1275                 if (in & WMFW_CTL_FLAG_WRITEABLE)
1276                         out |= wr;
1277                 if (in & WMFW_CTL_FLAG_VOLATILE)
1278                         out |= vol;
1279         } else {
1280                 out |= rd | wr | vol;
1281         }
1282
1283         return out;
1284 }
1285
1286 static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl)
1287 {
1288         struct snd_kcontrol_new *kcontrol;
1289         int ret;
1290
1291         if (!ctl || !ctl->name)
1292                 return -EINVAL;
1293
1294         kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
1295         if (!kcontrol)
1296                 return -ENOMEM;
1297
1298         kcontrol->name = ctl->name;
1299         kcontrol->info = wm_coeff_info;
1300         kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1301         kcontrol->tlv.c = snd_soc_bytes_tlv_callback;
1302         kcontrol->private_value = (unsigned long)&ctl->bytes_ext;
1303         kcontrol->access = wmfw_convert_flags(ctl->flags, ctl->len);
1304
1305         switch (ctl->type) {
1306         case WMFW_CTL_TYPE_ACKED:
1307                 kcontrol->get = wm_coeff_get_acked;
1308                 kcontrol->put = wm_coeff_put_acked;
1309                 break;
1310         default:
1311                 if (kcontrol->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
1312                         ctl->bytes_ext.max = ctl->len;
1313                         ctl->bytes_ext.get = wm_coeff_tlv_get;
1314                         ctl->bytes_ext.put = wm_coeff_tlv_put;
1315                 } else {
1316                         kcontrol->get = wm_coeff_get;
1317                         kcontrol->put = wm_coeff_put;
1318                 }
1319                 break;
1320         }
1321
1322         ret = snd_soc_add_component_controls(dsp->component, kcontrol, 1);
1323         if (ret < 0)
1324                 goto err_kcontrol;
1325
1326         kfree(kcontrol);
1327
1328         return 0;
1329
1330 err_kcontrol:
1331         kfree(kcontrol);
1332         return ret;
1333 }
1334
1335 static int wm_coeff_init_control_caches(struct wm_adsp *dsp)
1336 {
1337         struct wm_coeff_ctl *ctl;
1338         int ret;
1339
1340         list_for_each_entry(ctl, &dsp->ctl_list, list) {
1341                 if (!ctl->enabled || ctl->set)
1342                         continue;
1343                 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
1344                         continue;
1345
1346                 /*
1347                  * For readable controls populate the cache from the DSP memory.
1348                  * For non-readable controls the cache was zero-filled when
1349                  * created so we don't need to do anything.
1350                  */
1351                 if (!ctl->flags || (ctl->flags & WMFW_CTL_FLAG_READABLE)) {
1352                         ret = wm_coeff_read_ctrl_raw(ctl, ctl->cache, ctl->len);
1353                         if (ret < 0)
1354                                 return ret;
1355                 }
1356         }
1357
1358         return 0;
1359 }
1360
1361 static int wm_coeff_sync_controls(struct wm_adsp *dsp)
1362 {
1363         struct wm_coeff_ctl *ctl;
1364         int ret;
1365
1366         list_for_each_entry(ctl, &dsp->ctl_list, list) {
1367                 if (!ctl->enabled)
1368                         continue;
1369                 if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) {
1370                         ret = wm_coeff_write_ctrl_raw(ctl, ctl->cache,
1371                                                       ctl->len);
1372                         if (ret < 0)
1373                                 return ret;
1374                 }
1375         }
1376
1377         return 0;
1378 }
1379
1380 static void wm_adsp_signal_event_controls(struct wm_adsp *dsp,
1381                                           unsigned int event)
1382 {
1383         struct wm_coeff_ctl *ctl;
1384         int ret;
1385
1386         list_for_each_entry(ctl, &dsp->ctl_list, list) {
1387                 if (ctl->type != WMFW_CTL_TYPE_HOSTEVENT)
1388                         continue;
1389
1390                 if (!ctl->enabled)
1391                         continue;
1392
1393                 ret = wm_coeff_write_acked_control(ctl, event);
1394                 if (ret)
1395                         adsp_warn(dsp,
1396                                   "Failed to send 0x%x event to alg 0x%x (%d)\n",
1397                                   event, ctl->alg_region.alg, ret);
1398         }
1399 }
1400
1401 static void wm_adsp_ctl_work(struct work_struct *work)
1402 {
1403         struct wmfw_ctl_work *ctl_work = container_of(work,
1404                                                       struct wmfw_ctl_work,
1405                                                       work);
1406
1407         wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl);
1408         kfree(ctl_work);
1409 }
1410
1411 static void wm_adsp_free_ctl_blk(struct wm_coeff_ctl *ctl)
1412 {
1413         kfree(ctl->cache);
1414         kfree(ctl->name);
1415         kfree(ctl->subname);
1416         kfree(ctl);
1417 }
1418
1419 static int wm_adsp_create_control(struct wm_adsp *dsp,
1420                                   const struct wm_adsp_alg_region *alg_region,
1421                                   unsigned int offset, unsigned int len,
1422                                   const char *subname, unsigned int subname_len,
1423                                   unsigned int flags, unsigned int type)
1424 {
1425         struct wm_coeff_ctl *ctl;
1426         struct wmfw_ctl_work *ctl_work;
1427         char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
1428         const char *region_name;
1429         int ret;
1430
1431         region_name = wm_adsp_mem_region_name(alg_region->type);
1432         if (!region_name) {
1433                 adsp_err(dsp, "Unknown region type: %d\n", alg_region->type);
1434                 return -EINVAL;
1435         }
1436
1437         switch (dsp->fw_ver) {
1438         case 0:
1439         case 1:
1440                 snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "%s %s %x",
1441                          dsp->name, region_name, alg_region->alg);
1442                 subname = NULL; /* don't append subname */
1443                 break;
1444         case 2:
1445                 ret = scnprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
1446                                 "%s%c %.12s %x", dsp->name, *region_name,
1447                                 wm_adsp_fw_text[dsp->fw], alg_region->alg);
1448                 break;
1449         default:
1450                 ret = scnprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
1451                                 "%s %.12s %x", dsp->name,
1452                                 wm_adsp_fw_text[dsp->fw], alg_region->alg);
1453                 break;
1454         }
1455
1456         if (subname) {
1457                 int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2;
1458                 int skip = 0;
1459
1460                 if (dsp->component->name_prefix)
1461                         avail -= strlen(dsp->component->name_prefix) + 1;
1462
1463                 /* Truncate the subname from the start if it is too long */
1464                 if (subname_len > avail)
1465                         skip = subname_len - avail;
1466
1467                 snprintf(name + ret, SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret,
1468                          " %.*s", subname_len - skip, subname + skip);
1469         }
1470
1471         list_for_each_entry(ctl, &dsp->ctl_list, list) {
1472                 if (!strcmp(ctl->name, name)) {
1473                         if (!ctl->enabled)
1474                                 ctl->enabled = 1;
1475                         return 0;
1476                 }
1477         }
1478
1479         ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
1480         if (!ctl)
1481                 return -ENOMEM;
1482         ctl->fw_name = wm_adsp_fw_text[dsp->fw];
1483         ctl->alg_region = *alg_region;
1484         ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
1485         if (!ctl->name) {
1486                 ret = -ENOMEM;
1487                 goto err_ctl;
1488         }
1489         if (subname) {
1490                 ctl->subname_len = subname_len;
1491                 ctl->subname = kmemdup(subname,
1492                                        strlen(subname) + 1, GFP_KERNEL);
1493                 if (!ctl->subname) {
1494                         ret = -ENOMEM;
1495                         goto err_ctl_name;
1496                 }
1497         }
1498         ctl->enabled = 1;
1499         ctl->set = 0;
1500         ctl->ops.xget = wm_coeff_get;
1501         ctl->ops.xput = wm_coeff_put;
1502         ctl->dsp = dsp;
1503
1504         ctl->flags = flags;
1505         ctl->type = type;
1506         ctl->offset = offset;
1507         ctl->len = len;
1508         ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
1509         if (!ctl->cache) {
1510                 ret = -ENOMEM;
1511                 goto err_ctl_subname;
1512         }
1513
1514         list_add(&ctl->list, &dsp->ctl_list);
1515
1516         if (flags & WMFW_CTL_FLAG_SYS)
1517                 return 0;
1518
1519         ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL);
1520         if (!ctl_work) {
1521                 ret = -ENOMEM;
1522                 goto err_ctl_cache;
1523         }
1524
1525         ctl_work->dsp = dsp;
1526         ctl_work->ctl = ctl;
1527         INIT_WORK(&ctl_work->work, wm_adsp_ctl_work);
1528         schedule_work(&ctl_work->work);
1529
1530         return 0;
1531
1532 err_ctl_cache:
1533         kfree(ctl->cache);
1534 err_ctl_subname:
1535         kfree(ctl->subname);
1536 err_ctl_name:
1537         kfree(ctl->name);
1538 err_ctl:
1539         kfree(ctl);
1540
1541         return ret;
1542 }
1543
1544 struct wm_coeff_parsed_alg {
1545         int id;
1546         const u8 *name;
1547         int name_len;
1548         int ncoeff;
1549 };
1550
1551 struct wm_coeff_parsed_coeff {
1552         int offset;
1553         int mem_type;
1554         const u8 *name;
1555         int name_len;
1556         int ctl_type;
1557         int flags;
1558         int len;
1559 };
1560
1561 static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str)
1562 {
1563         int length;
1564
1565         switch (bytes) {
1566         case 1:
1567                 length = **pos;
1568                 break;
1569         case 2:
1570                 length = le16_to_cpu(*((__le16 *)*pos));
1571                 break;
1572         default:
1573                 return 0;
1574         }
1575
1576         if (str)
1577                 *str = *pos + bytes;
1578
1579         *pos += ((length + bytes) + 3) & ~0x03;
1580
1581         return length;
1582 }
1583
1584 static int wm_coeff_parse_int(int bytes, const u8 **pos)
1585 {
1586         int val = 0;
1587
1588         switch (bytes) {
1589         case 2:
1590                 val = le16_to_cpu(*((__le16 *)*pos));
1591                 break;
1592         case 4:
1593                 val = le32_to_cpu(*((__le32 *)*pos));
1594                 break;
1595         default:
1596                 break;
1597         }
1598
1599         *pos += bytes;
1600
1601         return val;
1602 }
1603
1604 static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data,
1605                                       struct wm_coeff_parsed_alg *blk)
1606 {
1607         const struct wmfw_adsp_alg_data *raw;
1608
1609         switch (dsp->fw_ver) {
1610         case 0:
1611         case 1:
1612                 raw = (const struct wmfw_adsp_alg_data *)*data;
1613                 *data = raw->data;
1614
1615                 blk->id = le32_to_cpu(raw->id);
1616                 blk->name = raw->name;
1617                 blk->name_len = strlen(raw->name);
1618                 blk->ncoeff = le32_to_cpu(raw->ncoeff);
1619                 break;
1620         default:
1621                 blk->id = wm_coeff_parse_int(sizeof(raw->id), data);
1622                 blk->name_len = wm_coeff_parse_string(sizeof(u8), data,
1623                                                       &blk->name);
1624                 wm_coeff_parse_string(sizeof(u16), data, NULL);
1625                 blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data);
1626                 break;
1627         }
1628
1629         adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id);
1630         adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name);
1631         adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff);
1632 }
1633
1634 static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data,
1635                                         struct wm_coeff_parsed_coeff *blk)
1636 {
1637         const struct wmfw_adsp_coeff_data *raw;
1638         const u8 *tmp;
1639         int length;
1640
1641         switch (dsp->fw_ver) {
1642         case 0:
1643         case 1:
1644                 raw = (const struct wmfw_adsp_coeff_data *)*data;
1645                 *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size);
1646
1647                 blk->offset = le16_to_cpu(raw->hdr.offset);
1648                 blk->mem_type = le16_to_cpu(raw->hdr.type);
1649                 blk->name = raw->name;
1650                 blk->name_len = strlen(raw->name);
1651                 blk->ctl_type = le16_to_cpu(raw->ctl_type);
1652                 blk->flags = le16_to_cpu(raw->flags);
1653                 blk->len = le32_to_cpu(raw->len);
1654                 break;
1655         default:
1656                 tmp = *data;
1657                 blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp);
1658                 blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp);
1659                 length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp);
1660                 blk->name_len = wm_coeff_parse_string(sizeof(u8), &tmp,
1661                                                       &blk->name);
1662                 wm_coeff_parse_string(sizeof(u8), &tmp, NULL);
1663                 wm_coeff_parse_string(sizeof(u16), &tmp, NULL);
1664                 blk->ctl_type = wm_coeff_parse_int(sizeof(raw->ctl_type), &tmp);
1665                 blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp);
1666                 blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp);
1667
1668                 *data = *data + sizeof(raw->hdr) + length;
1669                 break;
1670         }
1671
1672         adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type);
1673         adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset);
1674         adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name);
1675         adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags);
1676         adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type);
1677         adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len);
1678 }
1679
1680 static int wm_adsp_check_coeff_flags(struct wm_adsp *dsp,
1681                                 const struct wm_coeff_parsed_coeff *coeff_blk,
1682                                 unsigned int f_required,
1683                                 unsigned int f_illegal)
1684 {
1685         if ((coeff_blk->flags & f_illegal) ||
1686             ((coeff_blk->flags & f_required) != f_required)) {
1687                 adsp_err(dsp, "Illegal flags 0x%x for control type 0x%x\n",
1688                          coeff_blk->flags, coeff_blk->ctl_type);
1689                 return -EINVAL;
1690         }
1691
1692         return 0;
1693 }
1694
1695 static int wm_adsp_parse_coeff(struct wm_adsp *dsp,
1696                                const struct wmfw_region *region)
1697 {
1698         struct wm_adsp_alg_region alg_region = {};
1699         struct wm_coeff_parsed_alg alg_blk;
1700         struct wm_coeff_parsed_coeff coeff_blk;
1701         const u8 *data = region->data;
1702         int i, ret;
1703
1704         wm_coeff_parse_alg(dsp, &data, &alg_blk);
1705         for (i = 0; i < alg_blk.ncoeff; i++) {
1706                 wm_coeff_parse_coeff(dsp, &data, &coeff_blk);
1707
1708                 switch (coeff_blk.ctl_type) {
1709                 case SNDRV_CTL_ELEM_TYPE_BYTES:
1710                         break;
1711                 case WMFW_CTL_TYPE_ACKED:
1712                         if (coeff_blk.flags & WMFW_CTL_FLAG_SYS)
1713                                 continue;       /* ignore */
1714
1715                         ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1716                                                 WMFW_CTL_FLAG_VOLATILE |
1717                                                 WMFW_CTL_FLAG_WRITEABLE |
1718                                                 WMFW_CTL_FLAG_READABLE,
1719                                                 0);
1720                         if (ret)
1721                                 return -EINVAL;
1722                         break;
1723                 case WMFW_CTL_TYPE_HOSTEVENT:
1724                         ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1725                                                 WMFW_CTL_FLAG_SYS |
1726                                                 WMFW_CTL_FLAG_VOLATILE |
1727                                                 WMFW_CTL_FLAG_WRITEABLE |
1728                                                 WMFW_CTL_FLAG_READABLE,
1729                                                 0);
1730                         if (ret)
1731                                 return -EINVAL;
1732                         break;
1733                 case WMFW_CTL_TYPE_HOST_BUFFER:
1734                         ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1735                                                 WMFW_CTL_FLAG_SYS |
1736                                                 WMFW_CTL_FLAG_VOLATILE |
1737                                                 WMFW_CTL_FLAG_READABLE,
1738                                                 0);
1739                         if (ret)
1740                                 return -EINVAL;
1741                         break;
1742                 default:
1743                         adsp_err(dsp, "Unknown control type: %d\n",
1744                                  coeff_blk.ctl_type);
1745                         return -EINVAL;
1746                 }
1747
1748                 alg_region.type = coeff_blk.mem_type;
1749                 alg_region.alg = alg_blk.id;
1750
1751                 ret = wm_adsp_create_control(dsp, &alg_region,
1752                                              coeff_blk.offset,
1753                                              coeff_blk.len,
1754                                              coeff_blk.name,
1755                                              coeff_blk.name_len,
1756                                              coeff_blk.flags,
1757                                              coeff_blk.ctl_type);
1758                 if (ret < 0)
1759                         adsp_err(dsp, "Failed to create control: %.*s, %d\n",
1760                                  coeff_blk.name_len, coeff_blk.name, ret);
1761         }
1762
1763         return 0;
1764 }
1765
1766 static unsigned int wm_adsp1_parse_sizes(struct wm_adsp *dsp,
1767                                          const char * const file,
1768                                          unsigned int pos,
1769                                          const struct firmware *firmware)
1770 {
1771         const struct wmfw_adsp1_sizes *adsp1_sizes;
1772
1773         adsp1_sizes = (void *)&firmware->data[pos];
1774
1775         adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n", file,
1776                  le32_to_cpu(adsp1_sizes->dm), le32_to_cpu(adsp1_sizes->pm),
1777                  le32_to_cpu(adsp1_sizes->zm));
1778
1779         return pos + sizeof(*adsp1_sizes);
1780 }
1781
1782 static unsigned int wm_adsp2_parse_sizes(struct wm_adsp *dsp,
1783                                          const char * const file,
1784                                          unsigned int pos,
1785                                          const struct firmware *firmware)
1786 {
1787         const struct wmfw_adsp2_sizes *adsp2_sizes;
1788
1789         adsp2_sizes = (void *)&firmware->data[pos];
1790
1791         adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n", file,
1792                  le32_to_cpu(adsp2_sizes->xm), le32_to_cpu(adsp2_sizes->ym),
1793                  le32_to_cpu(adsp2_sizes->pm), le32_to_cpu(adsp2_sizes->zm));
1794
1795         return pos + sizeof(*adsp2_sizes);
1796 }
1797
1798 static bool wm_adsp_validate_version(struct wm_adsp *dsp, unsigned int version)
1799 {
1800         switch (version) {
1801         case 0:
1802                 adsp_warn(dsp, "Deprecated file format %d\n", version);
1803                 return true;
1804         case 1:
1805         case 2:
1806                 return true;
1807         default:
1808                 return false;
1809         }
1810 }
1811
1812 static bool wm_halo_validate_version(struct wm_adsp *dsp, unsigned int version)
1813 {
1814         switch (version) {
1815         case 3:
1816                 return true;
1817         default:
1818                 return false;
1819         }
1820 }
1821
1822 static int wm_adsp_load(struct wm_adsp *dsp)
1823 {
1824         LIST_HEAD(buf_list);
1825         const struct firmware *firmware;
1826         struct regmap *regmap = dsp->regmap;
1827         unsigned int pos = 0;
1828         const struct wmfw_header *header;
1829         const struct wmfw_adsp1_sizes *adsp1_sizes;
1830         const struct wmfw_footer *footer;
1831         const struct wmfw_region *region;
1832         const struct wm_adsp_region *mem;
1833         const char *region_name;
1834         char *file, *text = NULL;
1835         struct wm_adsp_buf *buf;
1836         unsigned int reg;
1837         int regions = 0;
1838         int ret, offset, type;
1839
1840         file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1841         if (file == NULL)
1842                 return -ENOMEM;
1843
1844         snprintf(file, PAGE_SIZE, "%s-%s-%s.wmfw", dsp->part, dsp->fwf_name,
1845                  wm_adsp_fw[dsp->fw].file);
1846         file[PAGE_SIZE - 1] = '\0';
1847
1848         ret = request_firmware(&firmware, file, dsp->dev);
1849         if (ret != 0) {
1850                 adsp_err(dsp, "Failed to request '%s'\n", file);
1851                 goto out;
1852         }
1853         ret = -EINVAL;
1854
1855         pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1856         if (pos >= firmware->size) {
1857                 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1858                          file, firmware->size);
1859                 goto out_fw;
1860         }
1861
1862         header = (void *)&firmware->data[0];
1863
1864         if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
1865                 adsp_err(dsp, "%s: invalid magic\n", file);
1866                 goto out_fw;
1867         }
1868
1869         if (!dsp->ops->validate_version(dsp, header->ver)) {
1870                 adsp_err(dsp, "%s: unknown file format %d\n",
1871                          file, header->ver);
1872                 goto out_fw;
1873         }
1874
1875         adsp_info(dsp, "Firmware version: %d\n", header->ver);
1876         dsp->fw_ver = header->ver;
1877
1878         if (header->core != dsp->type) {
1879                 adsp_err(dsp, "%s: invalid core %d != %d\n",
1880                          file, header->core, dsp->type);
1881                 goto out_fw;
1882         }
1883
1884         pos = sizeof(*header);
1885         pos = dsp->ops->parse_sizes(dsp, file, pos, firmware);
1886
1887         footer = (void *)&firmware->data[pos];
1888         pos += sizeof(*footer);
1889
1890         if (le32_to_cpu(header->len) != pos) {
1891                 adsp_err(dsp, "%s: unexpected header length %d\n",
1892                          file, le32_to_cpu(header->len));
1893                 goto out_fw;
1894         }
1895
1896         adsp_dbg(dsp, "%s: timestamp %llu\n", file,
1897                  le64_to_cpu(footer->timestamp));
1898
1899         while (pos < firmware->size &&
1900                sizeof(*region) < firmware->size - pos) {
1901                 region = (void *)&(firmware->data[pos]);
1902                 region_name = "Unknown";
1903                 reg = 0;
1904                 text = NULL;
1905                 offset = le32_to_cpu(region->offset) & 0xffffff;
1906                 type = be32_to_cpu(region->type) & 0xff;
1907
1908                 switch (type) {
1909                 case WMFW_NAME_TEXT:
1910                         region_name = "Firmware name";
1911                         text = kzalloc(le32_to_cpu(region->len) + 1,
1912                                        GFP_KERNEL);
1913                         break;
1914                 case WMFW_ALGORITHM_DATA:
1915                         region_name = "Algorithm";
1916                         ret = wm_adsp_parse_coeff(dsp, region);
1917                         if (ret != 0)
1918                                 goto out_fw;
1919                         break;
1920                 case WMFW_INFO_TEXT:
1921                         region_name = "Information";
1922                         text = kzalloc(le32_to_cpu(region->len) + 1,
1923                                        GFP_KERNEL);
1924                         break;
1925                 case WMFW_ABSOLUTE:
1926                         region_name = "Absolute";
1927                         reg = offset;
1928                         break;
1929                 case WMFW_ADSP1_PM:
1930                 case WMFW_ADSP1_DM:
1931                 case WMFW_ADSP2_XM:
1932                 case WMFW_ADSP2_YM:
1933                 case WMFW_ADSP1_ZM:
1934                 case WMFW_HALO_PM_PACKED:
1935                 case WMFW_HALO_XM_PACKED:
1936                 case WMFW_HALO_YM_PACKED:
1937                         mem = wm_adsp_find_region(dsp, type);
1938                         if (!mem) {
1939                                 adsp_err(dsp, "No region of type: %x\n", type);
1940                                 goto out_fw;
1941                         }
1942
1943                         region_name = wm_adsp_mem_region_name(type);
1944                         reg = dsp->ops->region_to_reg(mem, offset);
1945                         break;
1946                 default:
1947                         adsp_warn(dsp,
1948                                   "%s.%d: Unknown region type %x at %d(%x)\n",
1949                                   file, regions, type, pos, pos);
1950                         break;
1951                 }
1952
1953                 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
1954                          regions, le32_to_cpu(region->len), offset,
1955                          region_name);
1956
1957                 if (le32_to_cpu(region->len) >
1958                     firmware->size - pos - sizeof(*region)) {
1959                         adsp_err(dsp,
1960                                  "%s.%d: %s region len %d bytes exceeds file length %zu\n",
1961                                  file, regions, region_name,
1962                                  le32_to_cpu(region->len), firmware->size);
1963                         ret = -EINVAL;
1964                         goto out_fw;
1965                 }
1966
1967                 if (text) {
1968                         memcpy(text, region->data, le32_to_cpu(region->len));
1969                         adsp_info(dsp, "%s: %s\n", file, text);
1970                         kfree(text);
1971                         text = NULL;
1972                 }
1973
1974                 if (reg) {
1975                         buf = wm_adsp_buf_alloc(region->data,
1976                                                 le32_to_cpu(region->len),
1977                                                 &buf_list);
1978                         if (!buf) {
1979                                 adsp_err(dsp, "Out of memory\n");
1980                                 ret = -ENOMEM;
1981                                 goto out_fw;
1982                         }
1983
1984                         ret = regmap_raw_write_async(regmap, reg, buf->buf,
1985                                                      le32_to_cpu(region->len));
1986                         if (ret != 0) {
1987                                 adsp_err(dsp,
1988                                         "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
1989                                         file, regions,
1990                                         le32_to_cpu(region->len), offset,
1991                                         region_name, ret);
1992                                 goto out_fw;
1993                         }
1994                 }
1995
1996                 pos += le32_to_cpu(region->len) + sizeof(*region);
1997                 regions++;
1998         }
1999
2000         ret = regmap_async_complete(regmap);
2001         if (ret != 0) {
2002                 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
2003                 goto out_fw;
2004         }
2005
2006         if (pos > firmware->size)
2007                 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
2008                           file, regions, pos - firmware->size);
2009
2010         wm_adsp_debugfs_save_wmfwname(dsp, file);
2011
2012 out_fw:
2013         regmap_async_complete(regmap);
2014         wm_adsp_buf_free(&buf_list);
2015         release_firmware(firmware);
2016         kfree(text);
2017 out:
2018         kfree(file);
2019
2020         return ret;
2021 }
2022
2023 /*
2024  * Find wm_coeff_ctl with input name as its subname
2025  * If not found, return NULL
2026  */
2027 static struct wm_coeff_ctl *wm_adsp_get_ctl(struct wm_adsp *dsp,
2028                                              const char *name, int type,
2029                                              unsigned int alg)
2030 {
2031         struct wm_coeff_ctl *pos, *rslt = NULL;
2032
2033         list_for_each_entry(pos, &dsp->ctl_list, list) {
2034                 if (!pos->subname)
2035                         continue;
2036                 if (strncmp(pos->subname, name, pos->subname_len) == 0 &&
2037                                 pos->alg_region.alg == alg &&
2038                                 pos->alg_region.type == type) {
2039                         rslt = pos;
2040                         break;
2041                 }
2042         }
2043
2044         return rslt;
2045 }
2046
2047 int wm_adsp_write_ctl(struct wm_adsp *dsp, const char *name, int type,
2048                       unsigned int alg, void *buf, size_t len)
2049 {
2050         struct wm_coeff_ctl *ctl;
2051         struct snd_kcontrol *kcontrol;
2052         int ret;
2053
2054         ctl = wm_adsp_get_ctl(dsp, name, type, alg);
2055         if (!ctl)
2056                 return -EINVAL;
2057
2058         if (len > ctl->len)
2059                 return -EINVAL;
2060
2061         ret = wm_coeff_write_ctrl(ctl, buf, len);
2062
2063         kcontrol = snd_soc_card_get_kcontrol(dsp->component->card, ctl->name);
2064         snd_ctl_notify(dsp->component->card->snd_card,
2065                        SNDRV_CTL_EVENT_MASK_VALUE, &kcontrol->id);
2066
2067         return ret;
2068 }
2069 EXPORT_SYMBOL_GPL(wm_adsp_write_ctl);
2070
2071 int wm_adsp_read_ctl(struct wm_adsp *dsp, const char *name, int type,
2072                      unsigned int alg, void *buf, size_t len)
2073 {
2074         struct wm_coeff_ctl *ctl;
2075
2076         ctl = wm_adsp_get_ctl(dsp, name, type, alg);
2077         if (!ctl)
2078                 return -EINVAL;
2079
2080         if (len > ctl->len)
2081                 return -EINVAL;
2082
2083         return wm_coeff_read_ctrl(ctl, buf, len);
2084 }
2085 EXPORT_SYMBOL_GPL(wm_adsp_read_ctl);
2086
2087 static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp,
2088                                   const struct wm_adsp_alg_region *alg_region)
2089 {
2090         struct wm_coeff_ctl *ctl;
2091
2092         list_for_each_entry(ctl, &dsp->ctl_list, list) {
2093                 if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] &&
2094                     alg_region->alg == ctl->alg_region.alg &&
2095                     alg_region->type == ctl->alg_region.type) {
2096                         ctl->alg_region.base = alg_region->base;
2097                 }
2098         }
2099 }
2100
2101 static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs,
2102                                const struct wm_adsp_region *mem,
2103                                unsigned int pos, unsigned int len)
2104 {
2105         void *alg;
2106         unsigned int reg;
2107         int ret;
2108         __be32 val;
2109
2110         if (n_algs == 0) {
2111                 adsp_err(dsp, "No algorithms\n");
2112                 return ERR_PTR(-EINVAL);
2113         }
2114
2115         if (n_algs > 1024) {
2116                 adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs);
2117                 return ERR_PTR(-EINVAL);
2118         }
2119
2120         /* Read the terminator first to validate the length */
2121         reg = dsp->ops->region_to_reg(mem, pos + len);
2122
2123         ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
2124         if (ret != 0) {
2125                 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
2126                         ret);
2127                 return ERR_PTR(ret);
2128         }
2129
2130         if (be32_to_cpu(val) != 0xbedead)
2131                 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbedead\n",
2132                           reg, be32_to_cpu(val));
2133
2134         /* Convert length from DSP words to bytes */
2135         len *= sizeof(u32);
2136
2137         alg = kzalloc(len, GFP_KERNEL | GFP_DMA);
2138         if (!alg)
2139                 return ERR_PTR(-ENOMEM);
2140
2141         reg = dsp->ops->region_to_reg(mem, pos);
2142
2143         ret = regmap_raw_read(dsp->regmap, reg, alg, len);
2144         if (ret != 0) {
2145                 adsp_err(dsp, "Failed to read algorithm list: %d\n", ret);
2146                 kfree(alg);
2147                 return ERR_PTR(ret);
2148         }
2149
2150         return alg;
2151 }
2152
2153 static struct wm_adsp_alg_region *
2154         wm_adsp_find_alg_region(struct wm_adsp *dsp, int type, unsigned int id)
2155 {
2156         struct wm_adsp_alg_region *alg_region;
2157
2158         list_for_each_entry(alg_region, &dsp->alg_regions, list) {
2159                 if (id == alg_region->alg && type == alg_region->type)
2160                         return alg_region;
2161         }
2162
2163         return NULL;
2164 }
2165
2166 static struct wm_adsp_alg_region *wm_adsp_create_region(struct wm_adsp *dsp,
2167                                                         int type, __be32 id,
2168                                                         __be32 base)
2169 {
2170         struct wm_adsp_alg_region *alg_region;
2171
2172         alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL);
2173         if (!alg_region)
2174                 return ERR_PTR(-ENOMEM);
2175
2176         alg_region->type = type;
2177         alg_region->alg = be32_to_cpu(id);
2178         alg_region->base = be32_to_cpu(base);
2179
2180         list_add_tail(&alg_region->list, &dsp->alg_regions);
2181
2182         if (dsp->fw_ver > 0)
2183                 wm_adsp_ctl_fixup_base(dsp, alg_region);
2184
2185         return alg_region;
2186 }
2187
2188 static void wm_adsp_free_alg_regions(struct wm_adsp *dsp)
2189 {
2190         struct wm_adsp_alg_region *alg_region;
2191
2192         while (!list_empty(&dsp->alg_regions)) {
2193                 alg_region = list_first_entry(&dsp->alg_regions,
2194                                               struct wm_adsp_alg_region,
2195                                               list);
2196                 list_del(&alg_region->list);
2197                 kfree(alg_region);
2198         }
2199 }
2200
2201 static void wmfw_parse_id_header(struct wm_adsp *dsp,
2202                                  struct wmfw_id_hdr *fw, int nalgs)
2203 {
2204         dsp->fw_id = be32_to_cpu(fw->id);
2205         dsp->fw_id_version = be32_to_cpu(fw->ver);
2206
2207         adsp_info(dsp, "Firmware: %x v%d.%d.%d, %d algorithms\n",
2208                   dsp->fw_id, (dsp->fw_id_version & 0xff0000) >> 16,
2209                   (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff,
2210                   nalgs);
2211 }
2212
2213 static void wmfw_v3_parse_id_header(struct wm_adsp *dsp,
2214                                     struct wmfw_v3_id_hdr *fw, int nalgs)
2215 {
2216         dsp->fw_id = be32_to_cpu(fw->id);
2217         dsp->fw_id_version = be32_to_cpu(fw->ver);
2218         dsp->fw_vendor_id = be32_to_cpu(fw->vendor_id);
2219
2220         adsp_info(dsp, "Firmware: %x vendor: 0x%x v%d.%d.%d, %d algorithms\n",
2221                   dsp->fw_id, dsp->fw_vendor_id,
2222                   (dsp->fw_id_version & 0xff0000) >> 16,
2223                   (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff,
2224                   nalgs);
2225 }
2226
2227 static int wm_adsp_create_regions(struct wm_adsp *dsp, __be32 id, int nregions,
2228                                 int *type, __be32 *base)
2229 {
2230         struct wm_adsp_alg_region *alg_region;
2231         int i;
2232
2233         for (i = 0; i < nregions; i++) {
2234                 alg_region = wm_adsp_create_region(dsp, type[i], id, base[i]);
2235                 if (IS_ERR(alg_region))
2236                         return PTR_ERR(alg_region);
2237         }
2238
2239         return 0;
2240 }
2241
2242 static int wm_adsp1_setup_algs(struct wm_adsp *dsp)
2243 {
2244         struct wmfw_adsp1_id_hdr adsp1_id;
2245         struct wmfw_adsp1_alg_hdr *adsp1_alg;
2246         struct wm_adsp_alg_region *alg_region;
2247         const struct wm_adsp_region *mem;
2248         unsigned int pos, len;
2249         size_t n_algs;
2250         int i, ret;
2251
2252         mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
2253         if (WARN_ON(!mem))
2254                 return -EINVAL;
2255
2256         ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id,
2257                               sizeof(adsp1_id));
2258         if (ret != 0) {
2259                 adsp_err(dsp, "Failed to read algorithm info: %d\n",
2260                          ret);
2261                 return ret;
2262         }
2263
2264         n_algs = be32_to_cpu(adsp1_id.n_algs);
2265
2266         wmfw_parse_id_header(dsp, &adsp1_id.fw, n_algs);
2267
2268         alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
2269                                            adsp1_id.fw.id, adsp1_id.zm);
2270         if (IS_ERR(alg_region))
2271                 return PTR_ERR(alg_region);
2272
2273         alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
2274                                            adsp1_id.fw.id, adsp1_id.dm);
2275         if (IS_ERR(alg_region))
2276                 return PTR_ERR(alg_region);
2277
2278         /* Calculate offset and length in DSP words */
2279         pos = sizeof(adsp1_id) / sizeof(u32);
2280         len = (sizeof(*adsp1_alg) * n_algs) / sizeof(u32);
2281
2282         adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len);
2283         if (IS_ERR(adsp1_alg))
2284                 return PTR_ERR(adsp1_alg);
2285
2286         for (i = 0; i < n_algs; i++) {
2287                 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
2288                           i, be32_to_cpu(adsp1_alg[i].alg.id),
2289                           (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
2290                           (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
2291                           be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
2292                           be32_to_cpu(adsp1_alg[i].dm),
2293                           be32_to_cpu(adsp1_alg[i].zm));
2294
2295                 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
2296                                                    adsp1_alg[i].alg.id,
2297                                                    adsp1_alg[i].dm);
2298                 if (IS_ERR(alg_region)) {
2299                         ret = PTR_ERR(alg_region);
2300                         goto out;
2301                 }
2302                 if (dsp->fw_ver == 0) {
2303                         if (i + 1 < n_algs) {
2304                                 len = be32_to_cpu(adsp1_alg[i + 1].dm);
2305                                 len -= be32_to_cpu(adsp1_alg[i].dm);
2306                                 len *= 4;
2307                                 wm_adsp_create_control(dsp, alg_region, 0,
2308                                                      len, NULL, 0, 0,
2309                                                      SNDRV_CTL_ELEM_TYPE_BYTES);
2310                         } else {
2311                                 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
2312                                           be32_to_cpu(adsp1_alg[i].alg.id));
2313                         }
2314                 }
2315
2316                 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
2317                                                    adsp1_alg[i].alg.id,
2318                                                    adsp1_alg[i].zm);
2319                 if (IS_ERR(alg_region)) {
2320                         ret = PTR_ERR(alg_region);
2321                         goto out;
2322                 }
2323                 if (dsp->fw_ver == 0) {
2324                         if (i + 1 < n_algs) {
2325                                 len = be32_to_cpu(adsp1_alg[i + 1].zm);
2326                                 len -= be32_to_cpu(adsp1_alg[i].zm);
2327                                 len *= 4;
2328                                 wm_adsp_create_control(dsp, alg_region, 0,
2329                                                      len, NULL, 0, 0,
2330                                                      SNDRV_CTL_ELEM_TYPE_BYTES);
2331                         } else {
2332                                 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
2333                                           be32_to_cpu(adsp1_alg[i].alg.id));
2334                         }
2335                 }
2336         }
2337
2338 out:
2339         kfree(adsp1_alg);
2340         return ret;
2341 }
2342
2343 static int wm_adsp2_setup_algs(struct wm_adsp *dsp)
2344 {
2345         struct wmfw_adsp2_id_hdr adsp2_id;
2346         struct wmfw_adsp2_alg_hdr *adsp2_alg;
2347         struct wm_adsp_alg_region *alg_region;
2348         const struct wm_adsp_region *mem;
2349         unsigned int pos, len;
2350         size_t n_algs;
2351         int i, ret;
2352
2353         mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
2354         if (WARN_ON(!mem))
2355                 return -EINVAL;
2356
2357         ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id,
2358                               sizeof(adsp2_id));
2359         if (ret != 0) {
2360                 adsp_err(dsp, "Failed to read algorithm info: %d\n",
2361                          ret);
2362                 return ret;
2363         }
2364
2365         n_algs = be32_to_cpu(adsp2_id.n_algs);
2366
2367         wmfw_parse_id_header(dsp, &adsp2_id.fw, n_algs);
2368
2369         alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
2370                                            adsp2_id.fw.id, adsp2_id.xm);
2371         if (IS_ERR(alg_region))
2372                 return PTR_ERR(alg_region);
2373
2374         alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
2375                                            adsp2_id.fw.id, adsp2_id.ym);
2376         if (IS_ERR(alg_region))
2377                 return PTR_ERR(alg_region);
2378
2379         alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
2380                                            adsp2_id.fw.id, adsp2_id.zm);
2381         if (IS_ERR(alg_region))
2382                 return PTR_ERR(alg_region);
2383
2384         /* Calculate offset and length in DSP words */
2385         pos = sizeof(adsp2_id) / sizeof(u32);
2386         len = (sizeof(*adsp2_alg) * n_algs) / sizeof(u32);
2387
2388         adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len);
2389         if (IS_ERR(adsp2_alg))
2390                 return PTR_ERR(adsp2_alg);
2391
2392         for (i = 0; i < n_algs; i++) {
2393                 adsp_info(dsp,
2394                           "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
2395                           i, be32_to_cpu(adsp2_alg[i].alg.id),
2396                           (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
2397                           (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
2398                           be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
2399                           be32_to_cpu(adsp2_alg[i].xm),
2400                           be32_to_cpu(adsp2_alg[i].ym),
2401                           be32_to_cpu(adsp2_alg[i].zm));
2402
2403                 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
2404                                                    adsp2_alg[i].alg.id,
2405                                                    adsp2_alg[i].xm);
2406                 if (IS_ERR(alg_region)) {
2407                         ret = PTR_ERR(alg_region);
2408                         goto out;
2409                 }
2410                 if (dsp->fw_ver == 0) {
2411                         if (i + 1 < n_algs) {
2412                                 len = be32_to_cpu(adsp2_alg[i + 1].xm);
2413                                 len -= be32_to_cpu(adsp2_alg[i].xm);
2414                                 len *= 4;
2415                                 wm_adsp_create_control(dsp, alg_region, 0,
2416                                                      len, NULL, 0, 0,
2417                                                      SNDRV_CTL_ELEM_TYPE_BYTES);
2418                         } else {
2419                                 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
2420                                           be32_to_cpu(adsp2_alg[i].alg.id));
2421                         }
2422                 }
2423
2424                 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
2425                                                    adsp2_alg[i].alg.id,
2426                                                    adsp2_alg[i].ym);
2427                 if (IS_ERR(alg_region)) {
2428                         ret = PTR_ERR(alg_region);
2429                         goto out;
2430                 }
2431                 if (dsp->fw_ver == 0) {
2432                         if (i + 1 < n_algs) {
2433                                 len = be32_to_cpu(adsp2_alg[i + 1].ym);
2434                                 len -= be32_to_cpu(adsp2_alg[i].ym);
2435                                 len *= 4;
2436                                 wm_adsp_create_control(dsp, alg_region, 0,
2437                                                      len, NULL, 0, 0,
2438                                                      SNDRV_CTL_ELEM_TYPE_BYTES);
2439                         } else {
2440                                 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
2441                                           be32_to_cpu(adsp2_alg[i].alg.id));
2442                         }
2443                 }
2444
2445                 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
2446                                                    adsp2_alg[i].alg.id,
2447                                                    adsp2_alg[i].zm);
2448                 if (IS_ERR(alg_region)) {
2449                         ret = PTR_ERR(alg_region);
2450                         goto out;
2451                 }
2452                 if (dsp->fw_ver == 0) {
2453                         if (i + 1 < n_algs) {
2454                                 len = be32_to_cpu(adsp2_alg[i + 1].zm);
2455                                 len -= be32_to_cpu(adsp2_alg[i].zm);
2456                                 len *= 4;
2457                                 wm_adsp_create_control(dsp, alg_region, 0,
2458                                                      len, NULL, 0, 0,
2459                                                      SNDRV_CTL_ELEM_TYPE_BYTES);
2460                         } else {
2461                                 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
2462                                           be32_to_cpu(adsp2_alg[i].alg.id));
2463                         }
2464                 }
2465         }
2466
2467 out:
2468         kfree(adsp2_alg);
2469         return ret;
2470 }
2471
2472 static int wm_halo_create_regions(struct wm_adsp *dsp, __be32 id,
2473                                   __be32 xm_base, __be32 ym_base)
2474 {
2475         int types[] = {
2476                 WMFW_ADSP2_XM, WMFW_HALO_XM_PACKED,
2477                 WMFW_ADSP2_YM, WMFW_HALO_YM_PACKED
2478         };
2479         __be32 bases[] = { xm_base, xm_base, ym_base, ym_base };
2480
2481         return wm_adsp_create_regions(dsp, id, ARRAY_SIZE(types), types, bases);
2482 }
2483
2484 static int wm_halo_setup_algs(struct wm_adsp *dsp)
2485 {
2486         struct wmfw_halo_id_hdr halo_id;
2487         struct wmfw_halo_alg_hdr *halo_alg;
2488         const struct wm_adsp_region *mem;
2489         unsigned int pos, len;
2490         size_t n_algs;
2491         int i, ret;
2492
2493         mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
2494         if (WARN_ON(!mem))
2495                 return -EINVAL;
2496
2497         ret = regmap_raw_read(dsp->regmap, mem->base, &halo_id,
2498                               sizeof(halo_id));
2499         if (ret != 0) {
2500                 adsp_err(dsp, "Failed to read algorithm info: %d\n",
2501                          ret);
2502                 return ret;
2503         }
2504
2505         n_algs = be32_to_cpu(halo_id.n_algs);
2506
2507         wmfw_v3_parse_id_header(dsp, &halo_id.fw, n_algs);
2508
2509         ret = wm_halo_create_regions(dsp, halo_id.fw.id,
2510                                      halo_id.xm_base, halo_id.ym_base);
2511         if (ret)
2512                 return ret;
2513
2514         /* Calculate offset and length in DSP words */
2515         pos = sizeof(halo_id) / sizeof(u32);
2516         len = (sizeof(*halo_alg) * n_algs) / sizeof(u32);
2517
2518         halo_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len);
2519         if (IS_ERR(halo_alg))
2520                 return PTR_ERR(halo_alg);
2521
2522         for (i = 0; i < n_algs; i++) {
2523                 adsp_info(dsp,
2524                           "%d: ID %x v%d.%d.%d XM@%x YM@%x\n",
2525                           i, be32_to_cpu(halo_alg[i].alg.id),
2526                           (be32_to_cpu(halo_alg[i].alg.ver) & 0xff0000) >> 16,
2527                           (be32_to_cpu(halo_alg[i].alg.ver) & 0xff00) >> 8,
2528                           be32_to_cpu(halo_alg[i].alg.ver) & 0xff,
2529                           be32_to_cpu(halo_alg[i].xm_base),
2530                           be32_to_cpu(halo_alg[i].ym_base));
2531
2532                 ret = wm_halo_create_regions(dsp, halo_alg[i].alg.id,
2533                                              halo_alg[i].xm_base,
2534                                              halo_alg[i].ym_base);
2535                 if (ret)
2536                         goto out;
2537         }
2538
2539 out:
2540         kfree(halo_alg);
2541         return ret;
2542 }
2543
2544 static int wm_adsp_load_coeff(struct wm_adsp *dsp)
2545 {
2546         LIST_HEAD(buf_list);
2547         struct regmap *regmap = dsp->regmap;
2548         struct wmfw_coeff_hdr *hdr;
2549         struct wmfw_coeff_item *blk;
2550         const struct firmware *firmware;
2551         const struct wm_adsp_region *mem;
2552         struct wm_adsp_alg_region *alg_region;
2553         const char *region_name;
2554         int ret, pos, blocks, type, offset, reg;
2555         char *file;
2556         struct wm_adsp_buf *buf;
2557
2558         file = kzalloc(PAGE_SIZE, GFP_KERNEL);
2559         if (file == NULL)
2560                 return -ENOMEM;
2561
2562         snprintf(file, PAGE_SIZE, "%s-%s-%s.bin", dsp->part, dsp->fwf_name,
2563                  wm_adsp_fw[dsp->fw].file);
2564         file[PAGE_SIZE - 1] = '\0';
2565
2566         ret = request_firmware(&firmware, file, dsp->dev);
2567         if (ret != 0) {
2568                 adsp_warn(dsp, "Failed to request '%s'\n", file);
2569                 ret = 0;
2570                 goto out;
2571         }
2572         ret = -EINVAL;
2573
2574         if (sizeof(*hdr) >= firmware->size) {
2575                 adsp_err(dsp, "%s: file too short, %zu bytes\n",
2576                         file, firmware->size);
2577                 goto out_fw;
2578         }
2579
2580         hdr = (void *)&firmware->data[0];
2581         if (memcmp(hdr->magic, "WMDR", 4) != 0) {
2582                 adsp_err(dsp, "%s: invalid magic\n", file);
2583                 goto out_fw;
2584         }
2585
2586         switch (be32_to_cpu(hdr->rev) & 0xff) {
2587         case 1:
2588                 break;
2589         default:
2590                 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
2591                          file, be32_to_cpu(hdr->rev) & 0xff);
2592                 ret = -EINVAL;
2593                 goto out_fw;
2594         }
2595
2596         adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
2597                 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
2598                 (le32_to_cpu(hdr->ver) >>  8) & 0xff,
2599                 le32_to_cpu(hdr->ver) & 0xff);
2600
2601         pos = le32_to_cpu(hdr->len);
2602
2603         blocks = 0;
2604         while (pos < firmware->size &&
2605                sizeof(*blk) < firmware->size - pos) {
2606                 blk = (void *)(&firmware->data[pos]);
2607
2608                 type = le16_to_cpu(blk->type);
2609                 offset = le16_to_cpu(blk->offset);
2610
2611                 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
2612                          file, blocks, le32_to_cpu(blk->id),
2613                          (le32_to_cpu(blk->ver) >> 16) & 0xff,
2614                          (le32_to_cpu(blk->ver) >>  8) & 0xff,
2615                          le32_to_cpu(blk->ver) & 0xff);
2616                 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
2617                          file, blocks, le32_to_cpu(blk->len), offset, type);
2618
2619                 reg = 0;
2620                 region_name = "Unknown";
2621                 switch (type) {
2622                 case (WMFW_NAME_TEXT << 8):
2623                 case (WMFW_INFO_TEXT << 8):
2624                         break;
2625                 case (WMFW_ABSOLUTE << 8):
2626                         /*
2627                          * Old files may use this for global
2628                          * coefficients.
2629                          */
2630                         if (le32_to_cpu(blk->id) == dsp->fw_id &&
2631                             offset == 0) {
2632                                 region_name = "global coefficients";
2633                                 mem = wm_adsp_find_region(dsp, type);
2634                                 if (!mem) {
2635                                         adsp_err(dsp, "No ZM\n");
2636                                         break;
2637                                 }
2638                                 reg = dsp->ops->region_to_reg(mem, 0);
2639
2640                         } else {
2641                                 region_name = "register";
2642                                 reg = offset;
2643                         }
2644                         break;
2645
2646                 case WMFW_ADSP1_DM:
2647                 case WMFW_ADSP1_ZM:
2648                 case WMFW_ADSP2_XM:
2649                 case WMFW_ADSP2_YM:
2650                 case WMFW_HALO_XM_PACKED:
2651                 case WMFW_HALO_YM_PACKED:
2652                 case WMFW_HALO_PM_PACKED:
2653                         adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
2654                                  file, blocks, le32_to_cpu(blk->len),
2655                                  type, le32_to_cpu(blk->id));
2656
2657                         mem = wm_adsp_find_region(dsp, type);
2658                         if (!mem) {
2659                                 adsp_err(dsp, "No base for region %x\n", type);
2660                                 break;
2661                         }
2662
2663                         alg_region = wm_adsp_find_alg_region(dsp, type,
2664                                                 le32_to_cpu(blk->id));
2665                         if (alg_region) {
2666                                 reg = alg_region->base;
2667                                 reg = dsp->ops->region_to_reg(mem, reg);
2668                                 reg += offset;
2669                         } else {
2670                                 adsp_err(dsp, "No %x for algorithm %x\n",
2671                                          type, le32_to_cpu(blk->id));
2672                         }
2673                         break;
2674
2675                 default:
2676                         adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
2677                                  file, blocks, type, pos);
2678                         break;
2679                 }
2680
2681                 if (reg) {
2682                         if (le32_to_cpu(blk->len) >
2683                             firmware->size - pos - sizeof(*blk)) {
2684                                 adsp_err(dsp,
2685                                          "%s.%d: %s region len %d bytes exceeds file length %zu\n",
2686                                          file, blocks, region_name,
2687                                          le32_to_cpu(blk->len),
2688                                          firmware->size);
2689                                 ret = -EINVAL;
2690                                 goto out_fw;
2691                         }
2692
2693                         buf = wm_adsp_buf_alloc(blk->data,
2694                                                 le32_to_cpu(blk->len),
2695                                                 &buf_list);
2696                         if (!buf) {
2697                                 adsp_err(dsp, "Out of memory\n");
2698                                 ret = -ENOMEM;
2699                                 goto out_fw;
2700                         }
2701
2702                         adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
2703                                  file, blocks, le32_to_cpu(blk->len),
2704                                  reg);
2705                         ret = regmap_raw_write_async(regmap, reg, buf->buf,
2706                                                      le32_to_cpu(blk->len));
2707                         if (ret != 0) {
2708                                 adsp_err(dsp,
2709                                         "%s.%d: Failed to write to %x in %s: %d\n",
2710                                         file, blocks, reg, region_name, ret);
2711                         }
2712                 }
2713
2714                 pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03;
2715                 blocks++;
2716         }
2717
2718         ret = regmap_async_complete(regmap);
2719         if (ret != 0)
2720                 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
2721
2722         if (pos > firmware->size)
2723                 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
2724                           file, blocks, pos - firmware->size);
2725
2726         wm_adsp_debugfs_save_binname(dsp, file);
2727
2728 out_fw:
2729         regmap_async_complete(regmap);
2730         release_firmware(firmware);
2731         wm_adsp_buf_free(&buf_list);
2732 out:
2733         kfree(file);
2734         return ret;
2735 }
2736
2737 static int wm_adsp_create_name(struct wm_adsp *dsp)
2738 {
2739         char *p;
2740
2741         if (!dsp->name) {
2742                 dsp->name = devm_kasprintf(dsp->dev, GFP_KERNEL, "DSP%d",
2743                                            dsp->num);
2744                 if (!dsp->name)
2745                         return -ENOMEM;
2746         }
2747
2748         if (!dsp->fwf_name) {
2749                 p = devm_kstrdup(dsp->dev, dsp->name, GFP_KERNEL);
2750                 if (!p)
2751                         return -ENOMEM;
2752
2753                 dsp->fwf_name = p;
2754                 for (; *p != 0; ++p)
2755                         *p = tolower(*p);
2756         }
2757
2758         return 0;
2759 }
2760
2761 static int wm_adsp_common_init(struct wm_adsp *dsp)
2762 {
2763         int ret;
2764
2765         ret = wm_adsp_create_name(dsp);
2766         if (ret)
2767                 return ret;
2768
2769         INIT_LIST_HEAD(&dsp->alg_regions);
2770         INIT_LIST_HEAD(&dsp->ctl_list);
2771         INIT_LIST_HEAD(&dsp->compr_list);
2772         INIT_LIST_HEAD(&dsp->buffer_list);
2773
2774         mutex_init(&dsp->pwr_lock);
2775
2776         return 0;
2777 }
2778
2779 int wm_adsp1_init(struct wm_adsp *dsp)
2780 {
2781         dsp->ops = &wm_adsp1_ops;
2782
2783         return wm_adsp_common_init(dsp);
2784 }
2785 EXPORT_SYMBOL_GPL(wm_adsp1_init);
2786
2787 int wm_adsp1_event(struct snd_soc_dapm_widget *w,
2788                    struct snd_kcontrol *kcontrol,
2789                    int event)
2790 {
2791         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2792         struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
2793         struct wm_adsp *dsp = &dsps[w->shift];
2794         struct wm_coeff_ctl *ctl;
2795         int ret;
2796         unsigned int val;
2797
2798         dsp->component = component;
2799
2800         mutex_lock(&dsp->pwr_lock);
2801
2802         switch (event) {
2803         case SND_SOC_DAPM_POST_PMU:
2804                 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2805                                    ADSP1_SYS_ENA, ADSP1_SYS_ENA);
2806
2807                 /*
2808                  * For simplicity set the DSP clock rate to be the
2809                  * SYSCLK rate rather than making it configurable.
2810                  */
2811                 if (dsp->sysclk_reg) {
2812                         ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
2813                         if (ret != 0) {
2814                                 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
2815                                 ret);
2816                                 goto err_mutex;
2817                         }
2818
2819                         val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift;
2820
2821                         ret = regmap_update_bits(dsp->regmap,
2822                                                  dsp->base + ADSP1_CONTROL_31,
2823                                                  ADSP1_CLK_SEL_MASK, val);
2824                         if (ret != 0) {
2825                                 adsp_err(dsp, "Failed to set clock rate: %d\n",
2826                                          ret);
2827                                 goto err_mutex;
2828                         }
2829                 }
2830
2831                 ret = wm_adsp_load(dsp);
2832                 if (ret != 0)
2833                         goto err_ena;
2834
2835                 ret = wm_adsp1_setup_algs(dsp);
2836                 if (ret != 0)
2837                         goto err_ena;
2838
2839                 ret = wm_adsp_load_coeff(dsp);
2840                 if (ret != 0)
2841                         goto err_ena;
2842
2843                 /* Initialize caches for enabled and unset controls */
2844                 ret = wm_coeff_init_control_caches(dsp);
2845                 if (ret != 0)
2846                         goto err_ena;
2847
2848                 /* Sync set controls */
2849                 ret = wm_coeff_sync_controls(dsp);
2850                 if (ret != 0)
2851                         goto err_ena;
2852
2853                 dsp->booted = true;
2854
2855                 /* Start the core running */
2856                 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2857                                    ADSP1_CORE_ENA | ADSP1_START,
2858                                    ADSP1_CORE_ENA | ADSP1_START);
2859
2860                 dsp->running = true;
2861                 break;
2862
2863         case SND_SOC_DAPM_PRE_PMD:
2864                 dsp->running = false;
2865                 dsp->booted = false;
2866
2867                 /* Halt the core */
2868                 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2869                                    ADSP1_CORE_ENA | ADSP1_START, 0);
2870
2871                 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
2872                                    ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
2873
2874                 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2875                                    ADSP1_SYS_ENA, 0);
2876
2877                 list_for_each_entry(ctl, &dsp->ctl_list, list)
2878                         ctl->enabled = 0;
2879
2880
2881                 wm_adsp_free_alg_regions(dsp);
2882                 break;
2883
2884         default:
2885                 break;
2886         }
2887
2888         mutex_unlock(&dsp->pwr_lock);
2889
2890         return 0;
2891
2892 err_ena:
2893         regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2894                            ADSP1_SYS_ENA, 0);
2895 err_mutex:
2896         mutex_unlock(&dsp->pwr_lock);
2897
2898         return ret;
2899 }
2900 EXPORT_SYMBOL_GPL(wm_adsp1_event);
2901
2902 static int wm_adsp2v2_enable_core(struct wm_adsp *dsp)
2903 {
2904         unsigned int val;
2905         int ret, count;
2906
2907         /* Wait for the RAM to start, should be near instantaneous */
2908         for (count = 0; count < 10; ++count) {
2909                 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val);
2910                 if (ret != 0)
2911                         return ret;
2912
2913                 if (val & ADSP2_RAM_RDY)
2914                         break;
2915
2916                 usleep_range(250, 500);
2917         }
2918
2919         if (!(val & ADSP2_RAM_RDY)) {
2920                 adsp_err(dsp, "Failed to start DSP RAM\n");
2921                 return -EBUSY;
2922         }
2923
2924         adsp_dbg(dsp, "RAM ready after %d polls\n", count);
2925
2926         return 0;
2927 }
2928
2929 static int wm_adsp2_enable_core(struct wm_adsp *dsp)
2930 {
2931         int ret;
2932
2933         ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL,
2934                                        ADSP2_SYS_ENA, ADSP2_SYS_ENA);
2935         if (ret != 0)
2936                 return ret;
2937
2938         return wm_adsp2v2_enable_core(dsp);
2939 }
2940
2941 static int wm_adsp2_lock(struct wm_adsp *dsp, unsigned int lock_regions)
2942 {
2943         struct regmap *regmap = dsp->regmap;
2944         unsigned int code0, code1, lock_reg;
2945
2946         if (!(lock_regions & WM_ADSP2_REGION_ALL))
2947                 return 0;
2948
2949         lock_regions &= WM_ADSP2_REGION_ALL;
2950         lock_reg = dsp->base + ADSP2_LOCK_REGION_1_LOCK_REGION_0;
2951
2952         while (lock_regions) {
2953                 code0 = code1 = 0;
2954                 if (lock_regions & BIT(0)) {
2955                         code0 = ADSP2_LOCK_CODE_0;
2956                         code1 = ADSP2_LOCK_CODE_1;
2957                 }
2958                 if (lock_regions & BIT(1)) {
2959                         code0 |= ADSP2_LOCK_CODE_0 << ADSP2_LOCK_REGION_SHIFT;
2960                         code1 |= ADSP2_LOCK_CODE_1 << ADSP2_LOCK_REGION_SHIFT;
2961                 }
2962                 regmap_write(regmap, lock_reg, code0);
2963                 regmap_write(regmap, lock_reg, code1);
2964                 lock_regions >>= 2;
2965                 lock_reg += 2;
2966         }
2967
2968         return 0;
2969 }
2970
2971 static int wm_adsp2_enable_memory(struct wm_adsp *dsp)
2972 {
2973         return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2974                                   ADSP2_MEM_ENA, ADSP2_MEM_ENA);
2975 }
2976
2977 static void wm_adsp2_disable_memory(struct wm_adsp *dsp)
2978 {
2979         regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2980                            ADSP2_MEM_ENA, 0);
2981 }
2982
2983 static void wm_adsp2_disable_core(struct wm_adsp *dsp)
2984 {
2985         regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2986         regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2987         regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
2988
2989         regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2990                            ADSP2_SYS_ENA, 0);
2991 }
2992
2993 static void wm_adsp2v2_disable_core(struct wm_adsp *dsp)
2994 {
2995         regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2996         regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2997         regmap_write(dsp->regmap, dsp->base + ADSP2V2_WDMA_CONFIG_2, 0);
2998 }
2999
3000 static void wm_adsp_boot_work(struct work_struct *work)
3001 {
3002         struct wm_adsp *dsp = container_of(work,
3003                                            struct wm_adsp,
3004                                            boot_work);
3005         int ret;
3006
3007         mutex_lock(&dsp->pwr_lock);
3008
3009         if (dsp->ops->enable_memory) {
3010                 ret = dsp->ops->enable_memory(dsp);
3011                 if (ret != 0)
3012                         goto err_mutex;
3013         }
3014
3015         if (dsp->ops->enable_core) {
3016                 ret = dsp->ops->enable_core(dsp);
3017                 if (ret != 0)
3018                         goto err_mem;
3019         }
3020
3021         ret = wm_adsp_load(dsp);
3022         if (ret != 0)
3023                 goto err_ena;
3024
3025         ret = dsp->ops->setup_algs(dsp);
3026         if (ret != 0)
3027                 goto err_ena;
3028
3029         ret = wm_adsp_load_coeff(dsp);
3030         if (ret != 0)
3031                 goto err_ena;
3032
3033         /* Initialize caches for enabled and unset controls */
3034         ret = wm_coeff_init_control_caches(dsp);
3035         if (ret != 0)
3036                 goto err_ena;
3037
3038         if (dsp->ops->disable_core)
3039                 dsp->ops->disable_core(dsp);
3040
3041         dsp->booted = true;
3042
3043         mutex_unlock(&dsp->pwr_lock);
3044
3045         return;
3046
3047 err_ena:
3048         if (dsp->ops->disable_core)
3049                 dsp->ops->disable_core(dsp);
3050 err_mem:
3051         if (dsp->ops->disable_memory)
3052                 dsp->ops->disable_memory(dsp);
3053 err_mutex:
3054         mutex_unlock(&dsp->pwr_lock);
3055 }
3056
3057 static int wm_halo_configure_mpu(struct wm_adsp *dsp, unsigned int lock_regions)
3058 {
3059         struct reg_sequence config[] = {
3060                 { dsp->base + HALO_MPU_LOCK_CONFIG,     0x5555 },
3061                 { dsp->base + HALO_MPU_LOCK_CONFIG,     0xAAAA },
3062                 { dsp->base + HALO_MPU_XMEM_ACCESS_0,   0xFFFFFFFF },
3063                 { dsp->base + HALO_MPU_YMEM_ACCESS_0,   0xFFFFFFFF },
3064                 { dsp->base + HALO_MPU_WINDOW_ACCESS_0, lock_regions },
3065                 { dsp->base + HALO_MPU_XREG_ACCESS_0,   lock_regions },
3066                 { dsp->base + HALO_MPU_YREG_ACCESS_0,   lock_regions },
3067                 { dsp->base + HALO_MPU_XMEM_ACCESS_1,   0xFFFFFFFF },
3068                 { dsp->base + HALO_MPU_YMEM_ACCESS_1,   0xFFFFFFFF },
3069                 { dsp->base + HALO_MPU_WINDOW_ACCESS_1, lock_regions },
3070                 { dsp->base + HALO_MPU_XREG_ACCESS_1,   lock_regions },
3071                 { dsp->base + HALO_MPU_YREG_ACCESS_1,   lock_regions },
3072                 { dsp->base + HALO_MPU_XMEM_ACCESS_2,   0xFFFFFFFF },
3073                 { dsp->base + HALO_MPU_YMEM_ACCESS_2,   0xFFFFFFFF },
3074                 { dsp->base + HALO_MPU_WINDOW_ACCESS_2, lock_regions },
3075                 { dsp->base + HALO_MPU_XREG_ACCESS_2,   lock_regions },
3076                 { dsp->base + HALO_MPU_YREG_ACCESS_2,   lock_regions },
3077                 { dsp->base + HALO_MPU_XMEM_ACCESS_3,   0xFFFFFFFF },
3078                 { dsp->base + HALO_MPU_YMEM_ACCESS_3,   0xFFFFFFFF },
3079                 { dsp->base + HALO_MPU_WINDOW_ACCESS_3, lock_regions },
3080                 { dsp->base + HALO_MPU_XREG_ACCESS_3,   lock_regions },
3081                 { dsp->base + HALO_MPU_YREG_ACCESS_3,   lock_regions },
3082                 { dsp->base + HALO_MPU_LOCK_CONFIG,     0 },
3083         };
3084
3085         return regmap_multi_reg_write(dsp->regmap, config, ARRAY_SIZE(config));
3086 }
3087
3088 int wm_adsp2_set_dspclk(struct snd_soc_dapm_widget *w, unsigned int freq)
3089 {
3090         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
3091         struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
3092         struct wm_adsp *dsp = &dsps[w->shift];
3093         int ret;
3094
3095         ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CLOCKING,
3096                                  ADSP2_CLK_SEL_MASK,
3097                                  freq << ADSP2_CLK_SEL_SHIFT);
3098         if (ret)
3099                 adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
3100
3101         return ret;
3102 }
3103 EXPORT_SYMBOL_GPL(wm_adsp2_set_dspclk);
3104
3105 int wm_adsp2_preloader_get(struct snd_kcontrol *kcontrol,
3106                            struct snd_ctl_elem_value *ucontrol)
3107 {
3108         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
3109         struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
3110         struct soc_mixer_control *mc =
3111                 (struct soc_mixer_control *)kcontrol->private_value;
3112         struct wm_adsp *dsp = &dsps[mc->shift - 1];
3113
3114         ucontrol->value.integer.value[0] = dsp->preloaded;
3115
3116         return 0;
3117 }
3118 EXPORT_SYMBOL_GPL(wm_adsp2_preloader_get);
3119
3120 int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol,
3121                            struct snd_ctl_elem_value *ucontrol)
3122 {
3123         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
3124         struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
3125         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3126         struct soc_mixer_control *mc =
3127                 (struct soc_mixer_control *)kcontrol->private_value;
3128         struct wm_adsp *dsp = &dsps[mc->shift - 1];
3129         char preload[32];
3130
3131         snprintf(preload, ARRAY_SIZE(preload), "%s Preload", dsp->name);
3132
3133         dsp->preloaded = ucontrol->value.integer.value[0];
3134
3135         if (ucontrol->value.integer.value[0])
3136                 snd_soc_component_force_enable_pin(component, preload);
3137         else
3138                 snd_soc_component_disable_pin(component, preload);
3139
3140         snd_soc_dapm_sync(dapm);
3141
3142         flush_work(&dsp->boot_work);
3143
3144         return 0;
3145 }
3146 EXPORT_SYMBOL_GPL(wm_adsp2_preloader_put);
3147
3148 static void wm_adsp_stop_watchdog(struct wm_adsp *dsp)
3149 {
3150         regmap_update_bits(dsp->regmap, dsp->base + ADSP2_WATCHDOG,
3151                            ADSP2_WDT_ENA_MASK, 0);
3152 }
3153
3154 static void wm_halo_stop_watchdog(struct wm_adsp *dsp)
3155 {
3156         regmap_update_bits(dsp->regmap, dsp->base + HALO_WDT_CONTROL,
3157                            HALO_WDT_EN_MASK, 0);
3158 }
3159
3160 int wm_adsp_early_event(struct snd_soc_dapm_widget *w,
3161                         struct snd_kcontrol *kcontrol, int event)
3162 {
3163         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
3164         struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
3165         struct wm_adsp *dsp = &dsps[w->shift];
3166         struct wm_coeff_ctl *ctl;
3167
3168         switch (event) {
3169         case SND_SOC_DAPM_PRE_PMU:
3170                 queue_work(system_unbound_wq, &dsp->boot_work);
3171                 break;
3172         case SND_SOC_DAPM_PRE_PMD:
3173                 mutex_lock(&dsp->pwr_lock);
3174
3175                 wm_adsp_debugfs_clear(dsp);
3176
3177                 dsp->fw_id = 0;
3178                 dsp->fw_id_version = 0;
3179
3180                 dsp->booted = false;
3181
3182                 if (dsp->ops->disable_memory)
3183                         dsp->ops->disable_memory(dsp);
3184
3185                 list_for_each_entry(ctl, &dsp->ctl_list, list)
3186                         ctl->enabled = 0;
3187
3188                 wm_adsp_free_alg_regions(dsp);
3189
3190                 mutex_unlock(&dsp->pwr_lock);
3191
3192                 adsp_dbg(dsp, "Shutdown complete\n");
3193                 break;
3194         default:
3195                 break;
3196         }
3197
3198         return 0;
3199 }
3200 EXPORT_SYMBOL_GPL(wm_adsp_early_event);
3201
3202 static int wm_adsp2_start_core(struct wm_adsp *dsp)
3203 {
3204         return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
3205                                  ADSP2_CORE_ENA | ADSP2_START,
3206                                  ADSP2_CORE_ENA | ADSP2_START);
3207 }
3208
3209 static void wm_adsp2_stop_core(struct wm_adsp *dsp)
3210 {
3211         regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
3212                            ADSP2_CORE_ENA | ADSP2_START, 0);
3213 }
3214
3215 int wm_adsp_event(struct snd_soc_dapm_widget *w,
3216                   struct snd_kcontrol *kcontrol, int event)
3217 {
3218         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
3219         struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
3220         struct wm_adsp *dsp = &dsps[w->shift];
3221         int ret;
3222
3223         switch (event) {
3224         case SND_SOC_DAPM_POST_PMU:
3225                 flush_work(&dsp->boot_work);
3226
3227                 mutex_lock(&dsp->pwr_lock);
3228
3229                 if (!dsp->booted) {
3230                         ret = -EIO;
3231                         goto err;
3232                 }
3233
3234                 if (dsp->ops->enable_core) {
3235                         ret = dsp->ops->enable_core(dsp);
3236                         if (ret != 0)
3237                                 goto err;
3238                 }
3239
3240                 /* Sync set controls */
3241                 ret = wm_coeff_sync_controls(dsp);
3242                 if (ret != 0)
3243                         goto err;
3244
3245                 if (dsp->ops->lock_memory) {
3246                         ret = dsp->ops->lock_memory(dsp, dsp->lock_regions);
3247                         if (ret != 0) {
3248                                 adsp_err(dsp, "Error configuring MPU: %d\n",
3249                                          ret);
3250                                 goto err;
3251                         }
3252                 }
3253
3254                 if (dsp->ops->start_core) {
3255                         ret = dsp->ops->start_core(dsp);
3256                         if (ret != 0)
3257                                 goto err;
3258                 }
3259
3260                 if (wm_adsp_fw[dsp->fw].num_caps != 0) {
3261                         ret = wm_adsp_buffer_init(dsp);
3262                         if (ret < 0)
3263                                 goto err;
3264                 }
3265
3266                 dsp->running = true;
3267
3268                 mutex_unlock(&dsp->pwr_lock);
3269                 break;
3270
3271         case SND_SOC_DAPM_PRE_PMD:
3272                 /* Tell the firmware to cleanup */
3273                 wm_adsp_signal_event_controls(dsp, WM_ADSP_FW_EVENT_SHUTDOWN);
3274
3275                 if (dsp->ops->stop_watchdog)
3276                         dsp->ops->stop_watchdog(dsp);
3277
3278                 /* Log firmware state, it can be useful for analysis */
3279                 if (dsp->ops->show_fw_status)
3280                         dsp->ops->show_fw_status(dsp);
3281
3282                 mutex_lock(&dsp->pwr_lock);
3283
3284                 dsp->running = false;
3285
3286                 if (dsp->ops->stop_core)
3287                         dsp->ops->stop_core(dsp);
3288                 if (dsp->ops->disable_core)
3289                         dsp->ops->disable_core(dsp);
3290
3291                 if (wm_adsp_fw[dsp->fw].num_caps != 0)
3292                         wm_adsp_buffer_free(dsp);
3293
3294                 dsp->fatal_error = false;
3295
3296                 mutex_unlock(&dsp->pwr_lock);
3297
3298                 adsp_dbg(dsp, "Execution stopped\n");
3299                 break;
3300
3301         default:
3302                 break;
3303         }
3304
3305         return 0;
3306 err:
3307         if (dsp->ops->stop_core)
3308                 dsp->ops->stop_core(dsp);
3309         if (dsp->ops->disable_core)
3310                 dsp->ops->disable_core(dsp);
3311         mutex_unlock(&dsp->pwr_lock);
3312         return ret;
3313 }
3314 EXPORT_SYMBOL_GPL(wm_adsp_event);
3315
3316 static int wm_halo_start_core(struct wm_adsp *dsp)
3317 {
3318         return regmap_update_bits(dsp->regmap,
3319                                   dsp->base + HALO_CCM_CORE_CONTROL,
3320                                   HALO_CORE_EN, HALO_CORE_EN);
3321 }
3322
3323 static void wm_halo_stop_core(struct wm_adsp *dsp)
3324 {
3325         regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL,
3326                            HALO_CORE_EN, 0);
3327
3328         /* reset halo core with CORE_SOFT_RESET */
3329         regmap_update_bits(dsp->regmap, dsp->base + HALO_CORE_SOFT_RESET,
3330                            HALO_CORE_SOFT_RESET_MASK, 1);
3331 }
3332
3333 int wm_adsp2_component_probe(struct wm_adsp *dsp, struct snd_soc_component *component)
3334 {
3335         char preload[32];
3336
3337         snprintf(preload, ARRAY_SIZE(preload), "%s Preload", dsp->name);
3338         snd_soc_component_disable_pin(component, preload);
3339
3340         wm_adsp2_init_debugfs(dsp, component);
3341
3342         dsp->component = component;
3343
3344         return 0;
3345 }
3346 EXPORT_SYMBOL_GPL(wm_adsp2_component_probe);
3347
3348 int wm_adsp2_component_remove(struct wm_adsp *dsp, struct snd_soc_component *component)
3349 {
3350         wm_adsp2_cleanup_debugfs(dsp);
3351
3352         return 0;
3353 }
3354 EXPORT_SYMBOL_GPL(wm_adsp2_component_remove);
3355
3356 int wm_adsp2_init(struct wm_adsp *dsp)
3357 {
3358         int ret;
3359
3360         ret = wm_adsp_common_init(dsp);
3361         if (ret)
3362                 return ret;
3363
3364         switch (dsp->rev) {
3365         case 0:
3366                 /*
3367                  * Disable the DSP memory by default when in reset for a small
3368                  * power saving.
3369                  */
3370                 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
3371                                          ADSP2_MEM_ENA, 0);
3372                 if (ret) {
3373                         adsp_err(dsp,
3374                                  "Failed to clear memory retention: %d\n", ret);
3375                         return ret;
3376                 }
3377
3378                 dsp->ops = &wm_adsp2_ops[0];
3379                 break;
3380         case 1:
3381                 dsp->ops = &wm_adsp2_ops[1];
3382                 break;
3383         default:
3384                 dsp->ops = &wm_adsp2_ops[2];
3385                 break;
3386         }
3387
3388         INIT_WORK(&dsp->boot_work, wm_adsp_boot_work);
3389
3390         return 0;
3391 }
3392 EXPORT_SYMBOL_GPL(wm_adsp2_init);
3393
3394 int wm_halo_init(struct wm_adsp *dsp)
3395 {
3396         int ret;
3397
3398         ret = wm_adsp_common_init(dsp);
3399         if (ret)
3400                 return ret;
3401
3402         dsp->ops = &wm_halo_ops;
3403
3404         INIT_WORK(&dsp->boot_work, wm_adsp_boot_work);
3405
3406         return 0;
3407 }
3408 EXPORT_SYMBOL_GPL(wm_halo_init);
3409
3410 void wm_adsp2_remove(struct wm_adsp *dsp)
3411 {
3412         struct wm_coeff_ctl *ctl;
3413
3414         while (!list_empty(&dsp->ctl_list)) {
3415                 ctl = list_first_entry(&dsp->ctl_list, struct wm_coeff_ctl,
3416                                         list);
3417                 list_del(&ctl->list);
3418                 wm_adsp_free_ctl_blk(ctl);
3419         }
3420 }
3421 EXPORT_SYMBOL_GPL(wm_adsp2_remove);
3422
3423 static inline int wm_adsp_compr_attached(struct wm_adsp_compr *compr)
3424 {
3425         return compr->buf != NULL;
3426 }
3427
3428 static int wm_adsp_compr_attach(struct wm_adsp_compr *compr)
3429 {
3430         struct wm_adsp_compr_buf *buf = NULL, *tmp;
3431
3432         if (compr->dsp->fatal_error)
3433                 return -EINVAL;
3434
3435         list_for_each_entry(tmp, &compr->dsp->buffer_list, list) {
3436                 if (!tmp->name || !strcmp(compr->name, tmp->name)) {
3437                         buf = tmp;
3438                         break;
3439                 }
3440         }
3441
3442         if (!buf)
3443                 return -EINVAL;
3444
3445         compr->buf = buf;
3446         buf->compr = compr;
3447
3448         return 0;
3449 }
3450
3451 static void wm_adsp_compr_detach(struct wm_adsp_compr *compr)
3452 {
3453         if (!compr)
3454                 return;
3455
3456         /* Wake the poll so it can see buffer is no longer attached */
3457         if (compr->stream)
3458                 snd_compr_fragment_elapsed(compr->stream);
3459
3460         if (wm_adsp_compr_attached(compr)) {
3461                 compr->buf->compr = NULL;
3462                 compr->buf = NULL;
3463         }
3464 }
3465
3466 int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream)
3467 {
3468         struct wm_adsp_compr *compr, *tmp;
3469         struct snd_soc_pcm_runtime *rtd = stream->private_data;
3470         int ret = 0;
3471
3472         mutex_lock(&dsp->pwr_lock);
3473
3474         if (wm_adsp_fw[dsp->fw].num_caps == 0) {
3475                 adsp_err(dsp, "%s: Firmware does not support compressed API\n",
3476                          asoc_rtd_to_codec(rtd, 0)->name);
3477                 ret = -ENXIO;
3478                 goto out;
3479         }
3480
3481         if (wm_adsp_fw[dsp->fw].compr_direction != stream->direction) {
3482                 adsp_err(dsp, "%s: Firmware does not support stream direction\n",
3483                          asoc_rtd_to_codec(rtd, 0)->name);
3484                 ret = -EINVAL;
3485                 goto out;
3486         }
3487
3488         list_for_each_entry(tmp, &dsp->compr_list, list) {
3489                 if (!strcmp(tmp->name, asoc_rtd_to_codec(rtd, 0)->name)) {
3490                         adsp_err(dsp, "%s: Only a single stream supported per dai\n",
3491                                  asoc_rtd_to_codec(rtd, 0)->name);
3492                         ret = -EBUSY;
3493                         goto out;
3494                 }
3495         }
3496
3497         compr = kzalloc(sizeof(*compr), GFP_KERNEL);
3498         if (!compr) {
3499                 ret = -ENOMEM;
3500                 goto out;
3501         }
3502
3503         compr->dsp = dsp;
3504         compr->stream = stream;
3505         compr->name = asoc_rtd_to_codec(rtd, 0)->name;
3506
3507         list_add_tail(&compr->list, &dsp->compr_list);
3508
3509         stream->runtime->private_data = compr;
3510
3511 out:
3512         mutex_unlock(&dsp->pwr_lock);
3513
3514         return ret;
3515 }
3516 EXPORT_SYMBOL_GPL(wm_adsp_compr_open);
3517
3518 int wm_adsp_compr_free(struct snd_soc_component *component,
3519                        struct snd_compr_stream *stream)
3520 {
3521         struct wm_adsp_compr *compr = stream->runtime->private_data;
3522         struct wm_adsp *dsp = compr->dsp;
3523
3524         mutex_lock(&dsp->pwr_lock);
3525
3526         wm_adsp_compr_detach(compr);
3527         list_del(&compr->list);
3528
3529         kfree(compr->raw_buf);
3530         kfree(compr);
3531
3532         mutex_unlock(&dsp->pwr_lock);
3533
3534         return 0;
3535 }
3536 EXPORT_SYMBOL_GPL(wm_adsp_compr_free);
3537
3538 static int wm_adsp_compr_check_params(struct snd_compr_stream *stream,
3539                                       struct snd_compr_params *params)
3540 {
3541         struct wm_adsp_compr *compr = stream->runtime->private_data;
3542         struct wm_adsp *dsp = compr->dsp;
3543         const struct wm_adsp_fw_caps *caps;
3544         const struct snd_codec_desc *desc;
3545         int i, j;
3546
3547         if (params->buffer.fragment_size < WM_ADSP_MIN_FRAGMENT_SIZE ||
3548             params->buffer.fragment_size > WM_ADSP_MAX_FRAGMENT_SIZE ||
3549             params->buffer.fragments < WM_ADSP_MIN_FRAGMENTS ||
3550             params->buffer.fragments > WM_ADSP_MAX_FRAGMENTS ||
3551             params->buffer.fragment_size % WM_ADSP_DATA_WORD_SIZE) {
3552                 compr_err(compr, "Invalid buffer fragsize=%d fragments=%d\n",
3553                           params->buffer.fragment_size,
3554                           params->buffer.fragments);
3555
3556                 return -EINVAL;
3557         }
3558
3559         for (i = 0; i < wm_adsp_fw[dsp->fw].num_caps; i++) {
3560                 caps = &wm_adsp_fw[dsp->fw].caps[i];
3561                 desc = &caps->desc;
3562
3563                 if (caps->id != params->codec.id)
3564                         continue;
3565
3566                 if (stream->direction == SND_COMPRESS_PLAYBACK) {
3567                         if (desc->max_ch < params->codec.ch_out)
3568                                 continue;
3569                 } else {
3570                         if (desc->max_ch < params->codec.ch_in)
3571                                 continue;
3572                 }
3573
3574                 if (!(desc->formats & (1 << params->codec.format)))
3575                         continue;
3576
3577                 for (j = 0; j < desc->num_sample_rates; ++j)
3578                         if (desc->sample_rates[j] == params->codec.sample_rate)
3579                                 return 0;
3580         }
3581
3582         compr_err(compr, "Invalid params id=%u ch=%u,%u rate=%u fmt=%u\n",
3583                   params->codec.id, params->codec.ch_in, params->codec.ch_out,
3584                   params->codec.sample_rate, params->codec.format);
3585         return -EINVAL;
3586 }
3587
3588 static inline unsigned int wm_adsp_compr_frag_words(struct wm_adsp_compr *compr)
3589 {
3590         return compr->size.fragment_size / WM_ADSP_DATA_WORD_SIZE;
3591 }
3592
3593 int wm_adsp_compr_set_params(struct snd_soc_component *component,
3594                              struct snd_compr_stream *stream,
3595                              struct snd_compr_params *params)
3596 {
3597         struct wm_adsp_compr *compr = stream->runtime->private_data;
3598         unsigned int size;
3599         int ret;
3600
3601         ret = wm_adsp_compr_check_params(stream, params);
3602         if (ret)
3603                 return ret;
3604
3605         compr->size = params->buffer;
3606
3607         compr_dbg(compr, "fragment_size=%d fragments=%d\n",
3608                   compr->size.fragment_size, compr->size.fragments);
3609
3610         size = wm_adsp_compr_frag_words(compr) * sizeof(*compr->raw_buf);
3611         compr->raw_buf = kmalloc(size, GFP_DMA | GFP_KERNEL);
3612         if (!compr->raw_buf)
3613                 return -ENOMEM;
3614
3615         compr->sample_rate = params->codec.sample_rate;
3616
3617         return 0;
3618 }
3619 EXPORT_SYMBOL_GPL(wm_adsp_compr_set_params);
3620
3621 int wm_adsp_compr_get_caps(struct snd_soc_component *component,
3622                            struct snd_compr_stream *stream,
3623                            struct snd_compr_caps *caps)
3624 {
3625         struct wm_adsp_compr *compr = stream->runtime->private_data;
3626         int fw = compr->dsp->fw;
3627         int i;
3628
3629         if (wm_adsp_fw[fw].caps) {
3630                 for (i = 0; i < wm_adsp_fw[fw].num_caps; i++)
3631                         caps->codecs[i] = wm_adsp_fw[fw].caps[i].id;
3632
3633                 caps->num_codecs = i;
3634                 caps->direction = wm_adsp_fw[fw].compr_direction;
3635
3636                 caps->min_fragment_size = WM_ADSP_MIN_FRAGMENT_SIZE;
3637                 caps->max_fragment_size = WM_ADSP_MAX_FRAGMENT_SIZE;
3638                 caps->min_fragments = WM_ADSP_MIN_FRAGMENTS;
3639                 caps->max_fragments = WM_ADSP_MAX_FRAGMENTS;
3640         }
3641
3642         return 0;
3643 }
3644 EXPORT_SYMBOL_GPL(wm_adsp_compr_get_caps);
3645
3646 static int wm_adsp_read_data_block(struct wm_adsp *dsp, int mem_type,
3647                                    unsigned int mem_addr,
3648                                    unsigned int num_words, u32 *data)
3649 {
3650         struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
3651         unsigned int i, reg;
3652         int ret;
3653
3654         if (!mem)
3655                 return -EINVAL;
3656
3657         reg = dsp->ops->region_to_reg(mem, mem_addr);
3658
3659         ret = regmap_raw_read(dsp->regmap, reg, data,
3660                               sizeof(*data) * num_words);
3661         if (ret < 0)
3662                 return ret;
3663
3664         for (i = 0; i < num_words; ++i)
3665                 data[i] = be32_to_cpu(data[i]) & 0x00ffffffu;
3666
3667         return 0;
3668 }
3669
3670 static inline int wm_adsp_read_data_word(struct wm_adsp *dsp, int mem_type,
3671                                          unsigned int mem_addr, u32 *data)
3672 {
3673         return wm_adsp_read_data_block(dsp, mem_type, mem_addr, 1, data);
3674 }
3675
3676 static int wm_adsp_write_data_word(struct wm_adsp *dsp, int mem_type,
3677                                    unsigned int mem_addr, u32 data)
3678 {
3679         struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
3680         unsigned int reg;
3681
3682         if (!mem)
3683                 return -EINVAL;
3684
3685         reg = dsp->ops->region_to_reg(mem, mem_addr);
3686
3687         data = cpu_to_be32(data & 0x00ffffffu);
3688
3689         return regmap_raw_write(dsp->regmap, reg, &data, sizeof(data));
3690 }
3691
3692 static inline int wm_adsp_buffer_read(struct wm_adsp_compr_buf *buf,
3693                                       unsigned int field_offset, u32 *data)
3694 {
3695         return wm_adsp_read_data_word(buf->dsp, buf->host_buf_mem_type,
3696                                       buf->host_buf_ptr + field_offset, data);
3697 }
3698
3699 static inline int wm_adsp_buffer_write(struct wm_adsp_compr_buf *buf,
3700                                        unsigned int field_offset, u32 data)
3701 {
3702         return wm_adsp_write_data_word(buf->dsp, buf->host_buf_mem_type,
3703                                        buf->host_buf_ptr + field_offset, data);
3704 }
3705
3706 static void wm_adsp_remove_padding(u32 *buf, int nwords, int data_word_size)
3707 {
3708         u8 *pack_in = (u8 *)buf;
3709         u8 *pack_out = (u8 *)buf;
3710         int i, j;
3711
3712         /* Remove the padding bytes from the data read from the DSP */
3713         for (i = 0; i < nwords; i++) {
3714                 for (j = 0; j < data_word_size; j++)
3715                         *pack_out++ = *pack_in++;
3716
3717                 pack_in += sizeof(*buf) - data_word_size;
3718         }
3719 }
3720
3721 static int wm_adsp_buffer_populate(struct wm_adsp_compr_buf *buf)
3722 {
3723         const struct wm_adsp_fw_caps *caps = wm_adsp_fw[buf->dsp->fw].caps;
3724         struct wm_adsp_buffer_region *region;
3725         u32 offset = 0;
3726         int i, ret;
3727
3728         buf->regions = kcalloc(caps->num_regions, sizeof(*buf->regions),
3729                                GFP_KERNEL);
3730         if (!buf->regions)
3731                 return -ENOMEM;
3732
3733         for (i = 0; i < caps->num_regions; ++i) {
3734                 region = &buf->regions[i];
3735
3736                 region->offset = offset;
3737                 region->mem_type = caps->region_defs[i].mem_type;
3738
3739                 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].base_offset,
3740                                           &region->base_addr);
3741                 if (ret < 0)
3742                         return ret;
3743
3744                 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].size_offset,
3745                                           &offset);
3746                 if (ret < 0)
3747                         return ret;
3748
3749                 region->cumulative_size = offset;
3750
3751                 compr_dbg(buf,
3752                           "region=%d type=%d base=%08x off=%08x size=%08x\n",
3753                           i, region->mem_type, region->base_addr,
3754                           region->offset, region->cumulative_size);
3755         }
3756
3757         return 0;
3758 }
3759
3760 static void wm_adsp_buffer_clear(struct wm_adsp_compr_buf *buf)
3761 {
3762         buf->irq_count = 0xFFFFFFFF;
3763         buf->read_index = -1;
3764         buf->avail = 0;
3765 }
3766
3767 static struct wm_adsp_compr_buf *wm_adsp_buffer_alloc(struct wm_adsp *dsp)
3768 {
3769         struct wm_adsp_compr_buf *buf;
3770
3771         buf = kzalloc(sizeof(*buf), GFP_KERNEL);
3772         if (!buf)
3773                 return NULL;
3774
3775         buf->dsp = dsp;
3776
3777         wm_adsp_buffer_clear(buf);
3778
3779         list_add_tail(&buf->list, &dsp->buffer_list);
3780
3781         return buf;
3782 }
3783
3784 static int wm_adsp_buffer_parse_legacy(struct wm_adsp *dsp)
3785 {
3786         struct wm_adsp_alg_region *alg_region;
3787         struct wm_adsp_compr_buf *buf;
3788         u32 xmalg, addr, magic;
3789         int i, ret;
3790
3791         alg_region = wm_adsp_find_alg_region(dsp, WMFW_ADSP2_XM, dsp->fw_id);
3792         if (!alg_region) {
3793                 adsp_err(dsp, "No algorithm region found\n");
3794                 return -EINVAL;
3795         }
3796
3797         buf = wm_adsp_buffer_alloc(dsp);
3798         if (!buf)
3799                 return -ENOMEM;
3800
3801         xmalg = dsp->ops->sys_config_size / sizeof(__be32);
3802
3803         addr = alg_region->base + xmalg + ALG_XM_FIELD(magic);
3804         ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, &magic);
3805         if (ret < 0)
3806                 return ret;
3807
3808         if (magic != WM_ADSP_ALG_XM_STRUCT_MAGIC)
3809                 return -ENODEV;
3810
3811         addr = alg_region->base + xmalg + ALG_XM_FIELD(host_buf_ptr);
3812         for (i = 0; i < 5; ++i) {
3813                 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr,
3814                                              &buf->host_buf_ptr);
3815                 if (ret < 0)
3816                         return ret;
3817
3818                 if (buf->host_buf_ptr)
3819                         break;
3820
3821                 usleep_range(1000, 2000);
3822         }
3823
3824         if (!buf->host_buf_ptr)
3825                 return -EIO;
3826
3827         buf->host_buf_mem_type = WMFW_ADSP2_XM;
3828
3829         ret = wm_adsp_buffer_populate(buf);
3830         if (ret < 0)
3831                 return ret;
3832
3833         compr_dbg(buf, "legacy host_buf_ptr=%x\n", buf->host_buf_ptr);
3834
3835         return 0;
3836 }
3837
3838 static int wm_adsp_buffer_parse_coeff(struct wm_coeff_ctl *ctl)
3839 {
3840         struct wm_adsp_host_buf_coeff_v1 coeff_v1;
3841         struct wm_adsp_compr_buf *buf;
3842         unsigned int val, reg;
3843         int ret, i;
3844
3845         ret = wm_coeff_base_reg(ctl, &reg);
3846         if (ret)
3847                 return ret;
3848
3849         for (i = 0; i < 5; ++i) {
3850                 ret = regmap_raw_read(ctl->dsp->regmap, reg, &val, sizeof(val));
3851                 if (ret < 0)
3852                         return ret;
3853
3854                 if (val)
3855                         break;
3856
3857                 usleep_range(1000, 2000);
3858         }
3859
3860         if (!val) {
3861                 adsp_err(ctl->dsp, "Failed to acquire host buffer\n");
3862                 return -EIO;
3863         }
3864
3865         buf = wm_adsp_buffer_alloc(ctl->dsp);
3866         if (!buf)
3867                 return -ENOMEM;
3868
3869         buf->host_buf_mem_type = ctl->alg_region.type;
3870         buf->host_buf_ptr = be32_to_cpu(val);
3871
3872         ret = wm_adsp_buffer_populate(buf);
3873         if (ret < 0)
3874                 return ret;
3875
3876         /*
3877          * v0 host_buffer coefficients didn't have versioning, so if the
3878          * control is one word, assume version 0.
3879          */
3880         if (ctl->len == 4) {
3881                 compr_dbg(buf, "host_buf_ptr=%x\n", buf->host_buf_ptr);
3882                 return 0;
3883         }
3884
3885         ret = regmap_raw_read(ctl->dsp->regmap, reg, &coeff_v1,
3886                               sizeof(coeff_v1));
3887         if (ret < 0)
3888                 return ret;
3889
3890         coeff_v1.versions = be32_to_cpu(coeff_v1.versions);
3891         val = coeff_v1.versions & HOST_BUF_COEFF_COMPAT_VER_MASK;
3892         val >>= HOST_BUF_COEFF_COMPAT_VER_SHIFT;
3893
3894         if (val > HOST_BUF_COEFF_SUPPORTED_COMPAT_VER) {
3895                 adsp_err(ctl->dsp,
3896                          "Host buffer coeff ver %u > supported version %u\n",
3897                          val, HOST_BUF_COEFF_SUPPORTED_COMPAT_VER);
3898                 return -EINVAL;
3899         }
3900
3901         for (i = 0; i < ARRAY_SIZE(coeff_v1.name); i++)
3902                 coeff_v1.name[i] = be32_to_cpu(coeff_v1.name[i]);
3903
3904         wm_adsp_remove_padding((u32 *)&coeff_v1.name,
3905                                ARRAY_SIZE(coeff_v1.name),
3906                                WM_ADSP_DATA_WORD_SIZE);
3907
3908         buf->name = kasprintf(GFP_KERNEL, "%s-dsp-%s", ctl->dsp->part,
3909                               (char *)&coeff_v1.name);
3910
3911         compr_dbg(buf, "host_buf_ptr=%x coeff version %u\n",
3912                   buf->host_buf_ptr, val);
3913
3914         return val;
3915 }
3916
3917 static int wm_adsp_buffer_init(struct wm_adsp *dsp)
3918 {
3919         struct wm_coeff_ctl *ctl;
3920         int ret;
3921
3922         list_for_each_entry(ctl, &dsp->ctl_list, list) {
3923                 if (ctl->type != WMFW_CTL_TYPE_HOST_BUFFER)
3924                         continue;
3925
3926                 if (!ctl->enabled)
3927                         continue;
3928
3929                 ret = wm_adsp_buffer_parse_coeff(ctl);
3930                 if (ret < 0) {
3931                         adsp_err(dsp, "Failed to parse coeff: %d\n", ret);
3932                         goto error;
3933                 } else if (ret == 0) {
3934                         /* Only one buffer supported for version 0 */
3935                         return 0;
3936                 }
3937         }
3938
3939         if (list_empty(&dsp->buffer_list)) {
3940                 /* Fall back to legacy support */
3941                 ret = wm_adsp_buffer_parse_legacy(dsp);
3942                 if (ret) {
3943                         adsp_err(dsp, "Failed to parse legacy: %d\n", ret);
3944                         goto error;
3945                 }
3946         }
3947
3948         return 0;
3949
3950 error:
3951         wm_adsp_buffer_free(dsp);
3952         return ret;
3953 }
3954
3955 static int wm_adsp_buffer_free(struct wm_adsp *dsp)
3956 {
3957         struct wm_adsp_compr_buf *buf, *tmp;
3958
3959         list_for_each_entry_safe(buf, tmp, &dsp->buffer_list, list) {
3960                 wm_adsp_compr_detach(buf->compr);
3961
3962                 kfree(buf->name);
3963                 kfree(buf->regions);
3964                 list_del(&buf->list);
3965                 kfree(buf);
3966         }
3967
3968         return 0;
3969 }
3970
3971 static int wm_adsp_buffer_get_error(struct wm_adsp_compr_buf *buf)
3972 {
3973         int ret;
3974
3975         ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(error), &buf->error);
3976         if (ret < 0) {
3977                 compr_err(buf, "Failed to check buffer error: %d\n", ret);
3978                 return ret;
3979         }
3980         if (buf->error != 0) {
3981                 compr_err(buf, "Buffer error occurred: %d\n", buf->error);
3982                 return -EIO;
3983         }
3984
3985         return 0;
3986 }
3987
3988 int wm_adsp_compr_trigger(struct snd_soc_component *component,
3989                           struct snd_compr_stream *stream, int cmd)
3990 {
3991         struct wm_adsp_compr *compr = stream->runtime->private_data;
3992         struct wm_adsp *dsp = compr->dsp;
3993         int ret = 0;
3994
3995         compr_dbg(compr, "Trigger: %d\n", cmd);
3996
3997         mutex_lock(&dsp->pwr_lock);
3998
3999         switch (cmd) {
4000         case SNDRV_PCM_TRIGGER_START:
4001                 if (!wm_adsp_compr_attached(compr)) {
4002                         ret = wm_adsp_compr_attach(compr);
4003                         if (ret < 0) {
4004                                 compr_err(compr, "Failed to link buffer and stream: %d\n",
4005                                           ret);
4006                                 break;
4007                         }
4008                 }
4009
4010                 ret = wm_adsp_buffer_get_error(compr->buf);
4011                 if (ret < 0)
4012                         break;
4013
4014                 /* Trigger the IRQ at one fragment of data */
4015                 ret = wm_adsp_buffer_write(compr->buf,
4016                                            HOST_BUFFER_FIELD(high_water_mark),
4017                                            wm_adsp_compr_frag_words(compr));
4018                 if (ret < 0) {
4019                         compr_err(compr, "Failed to set high water mark: %d\n",
4020                                   ret);
4021                         break;
4022                 }
4023                 break;
4024         case SNDRV_PCM_TRIGGER_STOP:
4025                 if (wm_adsp_compr_attached(compr))
4026                         wm_adsp_buffer_clear(compr->buf);
4027                 break;
4028         default:
4029                 ret = -EINVAL;
4030                 break;
4031         }
4032
4033         mutex_unlock(&dsp->pwr_lock);
4034
4035         return ret;
4036 }
4037 EXPORT_SYMBOL_GPL(wm_adsp_compr_trigger);
4038
4039 static inline int wm_adsp_buffer_size(struct wm_adsp_compr_buf *buf)
4040 {
4041         int last_region = wm_adsp_fw[buf->dsp->fw].caps->num_regions - 1;
4042
4043         return buf->regions[last_region].cumulative_size;
4044 }
4045
4046 static int wm_adsp_buffer_update_avail(struct wm_adsp_compr_buf *buf)
4047 {
4048         u32 next_read_index, next_write_index;
4049         int write_index, read_index, avail;
4050         int ret;
4051
4052         /* Only sync read index if we haven't already read a valid index */
4053         if (buf->read_index < 0) {
4054                 ret = wm_adsp_buffer_read(buf,
4055                                 HOST_BUFFER_FIELD(next_read_index),
4056                                 &next_read_index);
4057                 if (ret < 0)
4058                         return ret;
4059
4060                 read_index = sign_extend32(next_read_index, 23);
4061
4062                 if (read_index < 0) {
4063                         compr_dbg(buf, "Avail check on unstarted stream\n");
4064                         return 0;
4065                 }
4066
4067                 buf->read_index = read_index;
4068         }
4069
4070         ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(next_write_index),
4071                         &next_write_index);
4072         if (ret < 0)
4073                 return ret;
4074
4075         write_index = sign_extend32(next_write_index, 23);
4076
4077         avail = write_index - buf->read_index;
4078         if (avail < 0)
4079                 avail += wm_adsp_buffer_size(buf);
4080
4081         compr_dbg(buf, "readindex=0x%x, writeindex=0x%x, avail=%d\n",
4082                   buf->read_index, write_index, avail * WM_ADSP_DATA_WORD_SIZE);
4083
4084         buf->avail = avail;
4085
4086         return 0;
4087 }
4088
4089 int wm_adsp_compr_handle_irq(struct wm_adsp *dsp)
4090 {
4091         struct wm_adsp_compr_buf *buf;
4092         struct wm_adsp_compr *compr;
4093         int ret = 0;
4094
4095         mutex_lock(&dsp->pwr_lock);
4096
4097         if (list_empty(&dsp->buffer_list)) {
4098                 ret = -ENODEV;
4099                 goto out;
4100         }
4101
4102         adsp_dbg(dsp, "Handling buffer IRQ\n");
4103
4104         list_for_each_entry(buf, &dsp->buffer_list, list) {
4105                 compr = buf->compr;
4106
4107                 ret = wm_adsp_buffer_get_error(buf);
4108                 if (ret < 0)
4109                         goto out_notify; /* Wake poll to report error */
4110
4111                 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(irq_count),
4112                                           &buf->irq_count);
4113                 if (ret < 0) {
4114                         compr_err(buf, "Failed to get irq_count: %d\n", ret);
4115                         goto out;
4116                 }
4117
4118                 ret = wm_adsp_buffer_update_avail(buf);
4119                 if (ret < 0) {
4120                         compr_err(buf, "Error reading avail: %d\n", ret);
4121                         goto out;
4122                 }
4123
4124                 if (wm_adsp_fw[dsp->fw].voice_trigger && buf->irq_count == 2)
4125                         ret = WM_ADSP_COMPR_VOICE_TRIGGER;
4126
4127 out_notify:
4128                 if (compr && compr->stream)
4129                         snd_compr_fragment_elapsed(compr->stream);
4130         }
4131
4132 out:
4133         mutex_unlock(&dsp->pwr_lock);
4134
4135         return ret;
4136 }
4137 EXPORT_SYMBOL_GPL(wm_adsp_compr_handle_irq);
4138
4139 static int wm_adsp_buffer_reenable_irq(struct wm_adsp_compr_buf *buf)
4140 {
4141         if (buf->irq_count & 0x01)
4142                 return 0;
4143
4144         compr_dbg(buf, "Enable IRQ(0x%x) for next fragment\n", buf->irq_count);
4145
4146         buf->irq_count |= 0x01;
4147
4148         return wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(irq_ack),
4149                                     buf->irq_count);
4150 }
4151
4152 int wm_adsp_compr_pointer(struct snd_soc_component *component,
4153                           struct snd_compr_stream *stream,
4154                           struct snd_compr_tstamp *tstamp)
4155 {
4156         struct wm_adsp_compr *compr = stream->runtime->private_data;
4157         struct wm_adsp *dsp = compr->dsp;
4158         struct wm_adsp_compr_buf *buf;
4159         int ret = 0;
4160
4161         compr_dbg(compr, "Pointer request\n");
4162
4163         mutex_lock(&dsp->pwr_lock);
4164
4165         buf = compr->buf;
4166
4167         if (dsp->fatal_error || !buf || buf->error) {
4168                 snd_compr_stop_error(stream, SNDRV_PCM_STATE_XRUN);
4169                 ret = -EIO;
4170                 goto out;
4171         }
4172
4173         if (buf->avail < wm_adsp_compr_frag_words(compr)) {
4174                 ret = wm_adsp_buffer_update_avail(buf);
4175                 if (ret < 0) {
4176                         compr_err(compr, "Error reading avail: %d\n", ret);
4177                         goto out;
4178                 }
4179
4180                 /*
4181                  * If we really have less than 1 fragment available tell the
4182                  * DSP to inform us once a whole fragment is available.
4183                  */
4184                 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
4185                         ret = wm_adsp_buffer_get_error(buf);
4186                         if (ret < 0) {
4187                                 if (buf->error)
4188                                         snd_compr_stop_error(stream,
4189                                                         SNDRV_PCM_STATE_XRUN);
4190                                 goto out;
4191                         }
4192
4193                         ret = wm_adsp_buffer_reenable_irq(buf);
4194                         if (ret < 0) {
4195                                 compr_err(compr, "Failed to re-enable buffer IRQ: %d\n",
4196                                           ret);
4197                                 goto out;
4198                         }
4199                 }
4200         }
4201
4202         tstamp->copied_total = compr->copied_total;
4203         tstamp->copied_total += buf->avail * WM_ADSP_DATA_WORD_SIZE;
4204         tstamp->sampling_rate = compr->sample_rate;
4205
4206 out:
4207         mutex_unlock(&dsp->pwr_lock);
4208
4209         return ret;
4210 }
4211 EXPORT_SYMBOL_GPL(wm_adsp_compr_pointer);
4212
4213 static int wm_adsp_buffer_capture_block(struct wm_adsp_compr *compr, int target)
4214 {
4215         struct wm_adsp_compr_buf *buf = compr->buf;
4216         unsigned int adsp_addr;
4217         int mem_type, nwords, max_read;
4218         int i, ret;
4219
4220         /* Calculate read parameters */
4221         for (i = 0; i < wm_adsp_fw[buf->dsp->fw].caps->num_regions; ++i)
4222                 if (buf->read_index < buf->regions[i].cumulative_size)
4223                         break;
4224
4225         if (i == wm_adsp_fw[buf->dsp->fw].caps->num_regions)
4226                 return -EINVAL;
4227
4228         mem_type = buf->regions[i].mem_type;
4229         adsp_addr = buf->regions[i].base_addr +
4230                     (buf->read_index - buf->regions[i].offset);
4231
4232         max_read = wm_adsp_compr_frag_words(compr);
4233         nwords = buf->regions[i].cumulative_size - buf->read_index;
4234
4235         if (nwords > target)
4236                 nwords = target;
4237         if (nwords > buf->avail)
4238                 nwords = buf->avail;
4239         if (nwords > max_read)
4240                 nwords = max_read;
4241         if (!nwords)
4242                 return 0;
4243
4244         /* Read data from DSP */
4245         ret = wm_adsp_read_data_block(buf->dsp, mem_type, adsp_addr,
4246                                       nwords, compr->raw_buf);
4247         if (ret < 0)
4248                 return ret;
4249
4250         wm_adsp_remove_padding(compr->raw_buf, nwords, WM_ADSP_DATA_WORD_SIZE);
4251
4252         /* update read index to account for words read */
4253         buf->read_index += nwords;
4254         if (buf->read_index == wm_adsp_buffer_size(buf))
4255                 buf->read_index = 0;
4256
4257         ret = wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(next_read_index),
4258                                    buf->read_index);
4259         if (ret < 0)
4260                 return ret;
4261
4262         /* update avail to account for words read */
4263         buf->avail -= nwords;
4264
4265         return nwords;
4266 }
4267
4268 static int wm_adsp_compr_read(struct wm_adsp_compr *compr,
4269                               char __user *buf, size_t count)
4270 {
4271         struct wm_adsp *dsp = compr->dsp;
4272         int ntotal = 0;
4273         int nwords, nbytes;
4274
4275         compr_dbg(compr, "Requested read of %zu bytes\n", count);
4276
4277         if (dsp->fatal_error || !compr->buf || compr->buf->error) {
4278                 snd_compr_stop_error(compr->stream, SNDRV_PCM_STATE_XRUN);
4279                 return -EIO;
4280         }
4281
4282         count /= WM_ADSP_DATA_WORD_SIZE;
4283
4284         do {
4285                 nwords = wm_adsp_buffer_capture_block(compr, count);
4286                 if (nwords < 0) {
4287                         compr_err(compr, "Failed to capture block: %d\n",
4288                                   nwords);
4289                         return nwords;
4290                 }
4291
4292                 nbytes = nwords * WM_ADSP_DATA_WORD_SIZE;
4293
4294                 compr_dbg(compr, "Read %d bytes\n", nbytes);
4295
4296                 if (copy_to_user(buf + ntotal, compr->raw_buf, nbytes)) {
4297                         compr_err(compr, "Failed to copy data to user: %d, %d\n",
4298                                   ntotal, nbytes);
4299                         return -EFAULT;
4300                 }
4301
4302                 count -= nwords;
4303                 ntotal += nbytes;
4304         } while (nwords > 0 && count > 0);
4305
4306         compr->copied_total += ntotal;
4307
4308         return ntotal;
4309 }
4310
4311 int wm_adsp_compr_copy(struct snd_soc_component *component,
4312                        struct snd_compr_stream *stream, char __user *buf,
4313                        size_t count)
4314 {
4315         struct wm_adsp_compr *compr = stream->runtime->private_data;
4316         struct wm_adsp *dsp = compr->dsp;
4317         int ret;
4318
4319         mutex_lock(&dsp->pwr_lock);
4320
4321         if (stream->direction == SND_COMPRESS_CAPTURE)
4322                 ret = wm_adsp_compr_read(compr, buf, count);
4323         else
4324                 ret = -ENOTSUPP;
4325
4326         mutex_unlock(&dsp->pwr_lock);
4327
4328         return ret;
4329 }
4330 EXPORT_SYMBOL_GPL(wm_adsp_compr_copy);
4331
4332 static void wm_adsp_fatal_error(struct wm_adsp *dsp)
4333 {
4334         struct wm_adsp_compr *compr;
4335
4336         dsp->fatal_error = true;
4337
4338         list_for_each_entry(compr, &dsp->compr_list, list) {
4339                 if (compr->stream)
4340                         snd_compr_fragment_elapsed(compr->stream);
4341         }
4342 }
4343
4344 irqreturn_t wm_adsp2_bus_error(int irq, void *data)
4345 {
4346         struct wm_adsp *dsp = (struct wm_adsp *)data;
4347         unsigned int val;
4348         struct regmap *regmap = dsp->regmap;
4349         int ret = 0;
4350
4351         mutex_lock(&dsp->pwr_lock);
4352
4353         ret = regmap_read(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, &val);
4354         if (ret) {
4355                 adsp_err(dsp,
4356                         "Failed to read Region Lock Ctrl register: %d\n", ret);
4357                 goto error;
4358         }
4359
4360         if (val & ADSP2_WDT_TIMEOUT_STS_MASK) {
4361                 adsp_err(dsp, "watchdog timeout error\n");
4362                 dsp->ops->stop_watchdog(dsp);
4363                 wm_adsp_fatal_error(dsp);
4364         }
4365
4366         if (val & (ADSP2_SLAVE_ERR_MASK | ADSP2_REGION_LOCK_ERR_MASK)) {
4367                 if (val & ADSP2_SLAVE_ERR_MASK)
4368                         adsp_err(dsp, "bus error: slave error\n");
4369                 else
4370                         adsp_err(dsp, "bus error: region lock error\n");
4371
4372                 ret = regmap_read(regmap, dsp->base + ADSP2_BUS_ERR_ADDR, &val);
4373                 if (ret) {
4374                         adsp_err(dsp,
4375                                  "Failed to read Bus Err Addr register: %d\n",
4376                                  ret);
4377                         goto error;
4378                 }
4379
4380                 adsp_err(dsp, "bus error address = 0x%x\n",
4381                          val & ADSP2_BUS_ERR_ADDR_MASK);
4382
4383                 ret = regmap_read(regmap,
4384                                   dsp->base + ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR,
4385                                   &val);
4386                 if (ret) {
4387                         adsp_err(dsp,
4388                                  "Failed to read Pmem Xmem Err Addr register: %d\n",
4389                                  ret);
4390                         goto error;
4391                 }
4392
4393                 adsp_err(dsp, "xmem error address = 0x%x\n",
4394                          val & ADSP2_XMEM_ERR_ADDR_MASK);
4395                 adsp_err(dsp, "pmem error address = 0x%x\n",
4396                          (val & ADSP2_PMEM_ERR_ADDR_MASK) >>
4397                          ADSP2_PMEM_ERR_ADDR_SHIFT);
4398         }
4399
4400         regmap_update_bits(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL,
4401                            ADSP2_CTRL_ERR_EINT, ADSP2_CTRL_ERR_EINT);
4402
4403 error:
4404         mutex_unlock(&dsp->pwr_lock);
4405
4406         return IRQ_HANDLED;
4407 }
4408 EXPORT_SYMBOL_GPL(wm_adsp2_bus_error);
4409
4410 irqreturn_t wm_halo_bus_error(int irq, void *data)
4411 {
4412         struct wm_adsp *dsp = (struct wm_adsp *)data;
4413         struct regmap *regmap = dsp->regmap;
4414         unsigned int fault[6];
4415         struct reg_sequence clear[] = {
4416                 { dsp->base + HALO_MPU_XM_VIO_STATUS,     0x0 },
4417                 { dsp->base + HALO_MPU_YM_VIO_STATUS,     0x0 },
4418                 { dsp->base + HALO_MPU_PM_VIO_STATUS,     0x0 },
4419         };
4420         int ret;
4421
4422         mutex_lock(&dsp->pwr_lock);
4423
4424         ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_1,
4425                           fault);
4426         if (ret) {
4427                 adsp_warn(dsp, "Failed to read AHB DEBUG_1: %d\n", ret);
4428                 goto exit_unlock;
4429         }
4430
4431         adsp_warn(dsp, "AHB: STATUS: 0x%x ADDR: 0x%x\n",
4432                   *fault & HALO_AHBM_FLAGS_ERR_MASK,
4433                   (*fault & HALO_AHBM_CORE_ERR_ADDR_MASK) >>
4434                   HALO_AHBM_CORE_ERR_ADDR_SHIFT);
4435
4436         ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_0,
4437                           fault);
4438         if (ret) {
4439                 adsp_warn(dsp, "Failed to read AHB DEBUG_0: %d\n", ret);
4440                 goto exit_unlock;
4441         }
4442
4443         adsp_warn(dsp, "AHB: SYS_ADDR: 0x%x\n", *fault);
4444
4445         ret = regmap_bulk_read(regmap, dsp->base + HALO_MPU_XM_VIO_ADDR,
4446                                fault, ARRAY_SIZE(fault));
4447         if (ret) {
4448                 adsp_warn(dsp, "Failed to read MPU fault info: %d\n", ret);
4449                 goto exit_unlock;
4450         }
4451
4452         adsp_warn(dsp, "XM: STATUS:0x%x ADDR:0x%x\n", fault[1], fault[0]);
4453         adsp_warn(dsp, "YM: STATUS:0x%x ADDR:0x%x\n", fault[3], fault[2]);
4454         adsp_warn(dsp, "PM: STATUS:0x%x ADDR:0x%x\n", fault[5], fault[4]);
4455
4456         ret = regmap_multi_reg_write(dsp->regmap, clear, ARRAY_SIZE(clear));
4457         if (ret)
4458                 adsp_warn(dsp, "Failed to clear MPU status: %d\n", ret);
4459
4460 exit_unlock:
4461         mutex_unlock(&dsp->pwr_lock);
4462
4463         return IRQ_HANDLED;
4464 }
4465 EXPORT_SYMBOL_GPL(wm_halo_bus_error);
4466
4467 irqreturn_t wm_halo_wdt_expire(int irq, void *data)
4468 {
4469         struct wm_adsp *dsp = data;
4470
4471         mutex_lock(&dsp->pwr_lock);
4472
4473         adsp_warn(dsp, "WDT Expiry Fault\n");
4474         dsp->ops->stop_watchdog(dsp);
4475         wm_adsp_fatal_error(dsp);
4476
4477         mutex_unlock(&dsp->pwr_lock);
4478
4479         return IRQ_HANDLED;
4480 }
4481 EXPORT_SYMBOL_GPL(wm_halo_wdt_expire);
4482
4483 static struct wm_adsp_ops wm_adsp1_ops = {
4484         .validate_version = wm_adsp_validate_version,
4485         .parse_sizes = wm_adsp1_parse_sizes,
4486         .region_to_reg = wm_adsp_region_to_reg,
4487 };
4488
4489 static struct wm_adsp_ops wm_adsp2_ops[] = {
4490         {
4491                 .sys_config_size = sizeof(struct wm_adsp_system_config_xm_hdr),
4492                 .parse_sizes = wm_adsp2_parse_sizes,
4493                 .validate_version = wm_adsp_validate_version,
4494                 .setup_algs = wm_adsp2_setup_algs,
4495                 .region_to_reg = wm_adsp_region_to_reg,
4496
4497                 .show_fw_status = wm_adsp2_show_fw_status,
4498
4499                 .enable_memory = wm_adsp2_enable_memory,
4500                 .disable_memory = wm_adsp2_disable_memory,
4501
4502                 .enable_core = wm_adsp2_enable_core,
4503                 .disable_core = wm_adsp2_disable_core,
4504
4505                 .start_core = wm_adsp2_start_core,
4506                 .stop_core = wm_adsp2_stop_core,
4507
4508         },
4509         {
4510                 .sys_config_size = sizeof(struct wm_adsp_system_config_xm_hdr),
4511                 .parse_sizes = wm_adsp2_parse_sizes,
4512                 .validate_version = wm_adsp_validate_version,
4513                 .setup_algs = wm_adsp2_setup_algs,
4514                 .region_to_reg = wm_adsp_region_to_reg,
4515
4516                 .show_fw_status = wm_adsp2v2_show_fw_status,
4517
4518                 .enable_memory = wm_adsp2_enable_memory,
4519                 .disable_memory = wm_adsp2_disable_memory,
4520                 .lock_memory = wm_adsp2_lock,
4521
4522                 .enable_core = wm_adsp2v2_enable_core,
4523                 .disable_core = wm_adsp2v2_disable_core,
4524
4525                 .start_core = wm_adsp2_start_core,
4526                 .stop_core = wm_adsp2_stop_core,
4527         },
4528         {
4529                 .sys_config_size = sizeof(struct wm_adsp_system_config_xm_hdr),
4530                 .parse_sizes = wm_adsp2_parse_sizes,
4531                 .validate_version = wm_adsp_validate_version,
4532                 .setup_algs = wm_adsp2_setup_algs,
4533                 .region_to_reg = wm_adsp_region_to_reg,
4534
4535                 .show_fw_status = wm_adsp2v2_show_fw_status,
4536                 .stop_watchdog = wm_adsp_stop_watchdog,
4537
4538                 .enable_memory = wm_adsp2_enable_memory,
4539                 .disable_memory = wm_adsp2_disable_memory,
4540                 .lock_memory = wm_adsp2_lock,
4541
4542                 .enable_core = wm_adsp2v2_enable_core,
4543                 .disable_core = wm_adsp2v2_disable_core,
4544
4545                 .start_core = wm_adsp2_start_core,
4546                 .stop_core = wm_adsp2_stop_core,
4547         },
4548 };
4549
4550 static struct wm_adsp_ops wm_halo_ops = {
4551         .sys_config_size = sizeof(struct wm_halo_system_config_xm_hdr),
4552         .parse_sizes = wm_adsp2_parse_sizes,
4553         .validate_version = wm_halo_validate_version,
4554         .setup_algs = wm_halo_setup_algs,
4555         .region_to_reg = wm_halo_region_to_reg,
4556
4557         .show_fw_status = wm_halo_show_fw_status,
4558         .stop_watchdog = wm_halo_stop_watchdog,
4559
4560         .lock_memory = wm_halo_configure_mpu,
4561
4562         .start_core = wm_halo_start_core,
4563         .stop_core = wm_halo_stop_core,
4564 };
4565
4566 MODULE_LICENSE("GPL v2");